From: Andrea Parri <parri.andrea@gmail.com>
To: Alexandre Ghiti <alex@ghiti.fr>
Cc: Alexandre Ghiti <alexghiti@rivosinc.com>,
Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Nathan Chancellor <nathan@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
Waiman Long <longman@redhat.com>,
Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH v2 03/10] riscv: Implement cmpxchg8/16() using Zabha
Date: Wed, 10 Jul 2024 01:51:32 +0200 [thread overview]
Message-ID: <Zo3NBHUEMMec/6uD@andrea> (raw)
In-Reply-To: <1cd452af-58cd-468c-9bb6-90f67711d0b0@ghiti.fr>
> > I admit that I found this all quite difficult to read; IIUC, this is
> > missing an IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) check.
>
> I'm not sure we need the zacas check here, since we could use a toolchain
> that supports zabha but not zacas, run this on a zabha/zacas platform and it
> would work.
One specific set-up I was concerned about is as follows:
1) hardware implements both zabha and zacas
2) toolchain supports both zabha and zacas
3) CONFIG_RISCV_ISA_ZABHA=y and CONFIG_RISCV_ISA_ZACAS=n
Since CONFIG_RISCV_ISA_ZABHA=y, the first asm goto will get executed
and, since the hardware implements zacas, that will result in a nop.
Then the second asm goto will get executed and, since the hardware
implements zabha, it will result in the j zabha. In conclusion, the
amocas instruction following the zabha: label will get executed, thus
violating (the semantics of) CONFIG_RISCV_ISA_ZACAS=n. IIUC, the diff
I've posted previously in this thread shared a similar limitation/bug.
Andrea
WARNING: multiple messages have this Message-ID (diff)
From: Andrea Parri <parri.andrea@gmail.com>
To: Alexandre Ghiti <alex@ghiti.fr>
Cc: Alexandre Ghiti <alexghiti@rivosinc.com>,
Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Nathan Chancellor <nathan@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
Waiman Long <longman@redhat.com>,
Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH v2 03/10] riscv: Implement cmpxchg8/16() using Zabha
Date: Wed, 10 Jul 2024 01:51:32 +0200 [thread overview]
Message-ID: <Zo3NBHUEMMec/6uD@andrea> (raw)
In-Reply-To: <1cd452af-58cd-468c-9bb6-90f67711d0b0@ghiti.fr>
> > I admit that I found this all quite difficult to read; IIUC, this is
> > missing an IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) check.
>
> I'm not sure we need the zacas check here, since we could use a toolchain
> that supports zabha but not zacas, run this on a zabha/zacas platform and it
> would work.
One specific set-up I was concerned about is as follows:
1) hardware implements both zabha and zacas
2) toolchain supports both zabha and zacas
3) CONFIG_RISCV_ISA_ZABHA=y and CONFIG_RISCV_ISA_ZACAS=n
Since CONFIG_RISCV_ISA_ZABHA=y, the first asm goto will get executed
and, since the hardware implements zacas, that will result in a nop.
Then the second asm goto will get executed and, since the hardware
implements zabha, it will result in the j zabha. In conclusion, the
amocas instruction following the zabha: label will get executed, thus
violating (the semantics of) CONFIG_RISCV_ISA_ZACAS=n. IIUC, the diff
I've posted previously in this thread shared a similar limitation/bug.
Andrea
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next prev parent reply other threads:[~2024-07-09 23:51 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-26 13:03 [PATCH v2 00/10] Zacas/Zabha support and qspinlocks Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 01/10] riscv: Implement cmpxchg32/64() using Zacas Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 11:06 ` Andrea Parri
2024-06-27 11:06 ` Andrea Parri
2024-07-04 16:25 ` Alexandre Ghiti
2024-07-04 16:25 ` Alexandre Ghiti
2024-07-09 23:47 ` Andrea Parri
2024-07-09 23:47 ` Andrea Parri
2024-07-15 11:48 ` Alexandre Ghiti
2024-07-15 11:48 ` Alexandre Ghiti
2024-07-04 3:38 ` kernel test robot
2024-07-04 3:38 ` kernel test robot
2024-07-05 17:27 ` Nathan Chancellor
2024-07-05 17:27 ` Nathan Chancellor
2024-07-16 12:19 ` Alexandre Ghiti
2024-07-16 12:19 ` Alexandre Ghiti
2024-07-16 14:00 ` Nathan Chancellor
2024-07-16 14:00 ` Nathan Chancellor
2024-06-26 13:03 ` [PATCH v2 02/10] dt-bindings: riscv: Add Zabha ISA extension description Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-26 14:20 ` Krzysztof Kozlowski
2024-06-26 14:20 ` Krzysztof Kozlowski
2024-06-26 13:03 ` [PATCH v2 03/10] riscv: Implement cmpxchg8/16() using Zabha Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 11:53 ` Andrea Parri
2024-06-27 11:53 ` Andrea Parri
2024-06-29 19:19 ` Andrea Parri
2024-06-29 19:19 ` Andrea Parri
2024-07-04 16:36 ` Alexandre Ghiti
2024-07-04 16:36 ` Alexandre Ghiti
2024-07-09 23:51 ` Andrea Parri [this message]
2024-07-09 23:51 ` Andrea Parri
2024-07-15 12:56 ` Alexandre Ghiti
2024-07-15 12:56 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 04/10] riscv: Improve amocas.X use in cmpxchg() Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 13:31 ` Andrea Parri
2024-06-27 13:31 ` Andrea Parri
2024-07-04 16:40 ` Alexandre Ghiti
2024-07-04 16:40 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 05/10] riscv: Implement arch_cmpxchg128() using Zacas Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 06/10] riscv: Implement xchg8/16() using Zabha Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 13:45 ` Andrea Parri
2024-06-27 13:45 ` Andrea Parri
2024-07-04 17:25 ` Alexandre Ghiti
2024-07-04 17:25 ` Alexandre Ghiti
2024-07-10 1:37 ` Guo Ren
2024-07-10 1:37 ` Guo Ren
2024-07-15 13:20 ` Alexandre Ghiti
2024-07-15 13:20 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 07/10] riscv: Improve amoswap.X use in xchg() Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 13:58 ` Andrea Parri
2024-06-27 13:58 ` Andrea Parri
2024-07-04 17:26 ` Alexandre Ghiti
2024-07-04 17:26 ` Alexandre Ghiti
2024-07-10 0:09 ` Andrea Parri
2024-07-10 0:09 ` Andrea Parri
2024-06-26 13:03 ` [PATCH v2 08/10] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 09/10] asm-generic: ticket-lock: Add separate ticket-lock.h Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 10/10] riscv: Add qspinlock support based on Zabha extension Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 15:19 ` Andrea Parri
2024-06-27 15:19 ` Andrea Parri
2024-07-04 17:33 ` Alexandre Ghiti
2024-07-04 17:33 ` Alexandre Ghiti
2024-07-07 2:20 ` Guo Ren
2024-07-07 2:20 ` Guo Ren
2024-07-08 11:51 ` Guo Ren
2024-07-08 11:51 ` Guo Ren
2024-07-15 7:33 ` Alexandre Ghiti
2024-07-15 7:33 ` Alexandre Ghiti
2024-07-15 7:27 ` Alexandre Ghiti
2024-07-15 7:27 ` Alexandre Ghiti
2024-07-15 19:30 ` Waiman Long
2024-07-15 19:30 ` Waiman Long
2024-07-16 1:04 ` Guo Ren
2024-07-16 1:04 ` Guo Ren
2024-07-16 6:43 ` Alexandre Ghiti
2024-07-16 6:43 ` Alexandre Ghiti
2024-07-16 8:31 ` Guo Ren
2024-07-16 8:31 ` Guo Ren
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
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