From: Andrea Parri <parri.andrea@gmail.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Nathan Chancellor <nathan@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
Waiman Long <longman@redhat.com>,
Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH v2 03/10] riscv: Implement cmpxchg8/16() using Zabha
Date: Sat, 29 Jun 2024 21:19:41 +0200 [thread overview]
Message-ID: <ZoBeTTdMYdXU8gxD@andrea> (raw)
In-Reply-To: <Zn1StcN3H0r/eHjh@andrea>
> I admit that I found this all quite difficult to read; IIUC, this is
> missing an IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) check. How about adding
> such a check under the zabha: label (replacing/in place of the second
> IS_ENABLED(CONFIG_RISCV_ISA_ZABHA) check) and moving the corresponding
> asm goto statement there, perhaps as follows? (on top of this patch)
[...]
> diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> index b9a3fdcec919..3c913afec150 100644
> --- a/arch/riscv/include/asm/cmpxchg.h
> +++ b/arch/riscv/include/asm/cmpxchg.h
> @@ -110,15 +110,12 @@
> __label__ no_zacas, zabha, end; \
> \
> if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA)) { \
> - asm goto(ALTERNATIVE("j %[no_zacas]", "nop", 0, \
> - RISCV_ISA_EXT_ZACAS, 1) \
> - : : : : no_zacas); \
> asm goto(ALTERNATIVE("nop", "j %[zabha]", 0, \
> RISCV_ISA_EXT_ZABHA, 1) \
> : : : : zabha); \
> } \
> \
> -no_zacas:; \
> +no_zacas: \
> u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \
> ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \
> ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \
> @@ -148,16 +145,20 @@ no_zacas:; \
> goto end; \
> \
> zabha: \
> - if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA)) { \
> - __asm__ __volatile__ ( \
> - prepend \
> - " amocas" cas_sfx " %0, %z2, %1\n" \
> - append \
> - : "+&r" (r), "+A" (*(p)) \
> - : "rJ" (n) \
> - : "memory"); \
> + if (IS_ENABLED(CONFIG_RISCV_ISA_ZAZAS)) { \
> + asm goto(ALTERNATIVE("j %[no_zacas]", "nop", 0, \
> + RISCV_ISA_EXT_ZACAS, 1) \
> + : : : : no_zacas); \
> } \
> -end:; \
> + \
> + __asm__ __volatile__ ( \
> + prepend \
> + " amocas" cas_sfx " %0, %z2, %1\n" \
> + append \
> + : "+&r" (r), "+A" (*(p)) \
> + : "rJ" (n) \
> + : "memory"); \
> +end: \
> })
>
> #define __arch_cmpxchg(lr_sfx, sc_cas_sfx, prepend, append, r, p, co, o, n) \
Unfortunately, this diff won't work e.g. when ZABHA is supported and
detected at boot while ZACAS is not supported; more thinking required...
Andrea
WARNING: multiple messages have this Message-ID (diff)
From: Andrea Parri <parri.andrea@gmail.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Nathan Chancellor <nathan@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
Waiman Long <longman@redhat.com>,
Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH v2 03/10] riscv: Implement cmpxchg8/16() using Zabha
Date: Sat, 29 Jun 2024 21:19:41 +0200 [thread overview]
Message-ID: <ZoBeTTdMYdXU8gxD@andrea> (raw)
In-Reply-To: <Zn1StcN3H0r/eHjh@andrea>
> I admit that I found this all quite difficult to read; IIUC, this is
> missing an IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) check. How about adding
> such a check under the zabha: label (replacing/in place of the second
> IS_ENABLED(CONFIG_RISCV_ISA_ZABHA) check) and moving the corresponding
> asm goto statement there, perhaps as follows? (on top of this patch)
[...]
> diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> index b9a3fdcec919..3c913afec150 100644
> --- a/arch/riscv/include/asm/cmpxchg.h
> +++ b/arch/riscv/include/asm/cmpxchg.h
> @@ -110,15 +110,12 @@
> __label__ no_zacas, zabha, end; \
> \
> if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA)) { \
> - asm goto(ALTERNATIVE("j %[no_zacas]", "nop", 0, \
> - RISCV_ISA_EXT_ZACAS, 1) \
> - : : : : no_zacas); \
> asm goto(ALTERNATIVE("nop", "j %[zabha]", 0, \
> RISCV_ISA_EXT_ZABHA, 1) \
> : : : : zabha); \
> } \
> \
> -no_zacas:; \
> +no_zacas: \
> u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \
> ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \
> ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \
> @@ -148,16 +145,20 @@ no_zacas:; \
> goto end; \
> \
> zabha: \
> - if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA)) { \
> - __asm__ __volatile__ ( \
> - prepend \
> - " amocas" cas_sfx " %0, %z2, %1\n" \
> - append \
> - : "+&r" (r), "+A" (*(p)) \
> - : "rJ" (n) \
> - : "memory"); \
> + if (IS_ENABLED(CONFIG_RISCV_ISA_ZAZAS)) { \
> + asm goto(ALTERNATIVE("j %[no_zacas]", "nop", 0, \
> + RISCV_ISA_EXT_ZACAS, 1) \
> + : : : : no_zacas); \
> } \
> -end:; \
> + \
> + __asm__ __volatile__ ( \
> + prepend \
> + " amocas" cas_sfx " %0, %z2, %1\n" \
> + append \
> + : "+&r" (r), "+A" (*(p)) \
> + : "rJ" (n) \
> + : "memory"); \
> +end: \
> })
>
> #define __arch_cmpxchg(lr_sfx, sc_cas_sfx, prepend, append, r, p, co, o, n) \
Unfortunately, this diff won't work e.g. when ZABHA is supported and
detected at boot while ZACAS is not supported; more thinking required...
Andrea
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next prev parent reply other threads:[~2024-06-29 19:20 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-26 13:03 [PATCH v2 00/10] Zacas/Zabha support and qspinlocks Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 01/10] riscv: Implement cmpxchg32/64() using Zacas Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 11:06 ` Andrea Parri
2024-06-27 11:06 ` Andrea Parri
2024-07-04 16:25 ` Alexandre Ghiti
2024-07-04 16:25 ` Alexandre Ghiti
2024-07-09 23:47 ` Andrea Parri
2024-07-09 23:47 ` Andrea Parri
2024-07-15 11:48 ` Alexandre Ghiti
2024-07-15 11:48 ` Alexandre Ghiti
2024-07-04 3:38 ` kernel test robot
2024-07-04 3:38 ` kernel test robot
2024-07-05 17:27 ` Nathan Chancellor
2024-07-05 17:27 ` Nathan Chancellor
2024-07-16 12:19 ` Alexandre Ghiti
2024-07-16 12:19 ` Alexandre Ghiti
2024-07-16 14:00 ` Nathan Chancellor
2024-07-16 14:00 ` Nathan Chancellor
2024-06-26 13:03 ` [PATCH v2 02/10] dt-bindings: riscv: Add Zabha ISA extension description Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-26 14:20 ` Krzysztof Kozlowski
2024-06-26 14:20 ` Krzysztof Kozlowski
2024-06-26 13:03 ` [PATCH v2 03/10] riscv: Implement cmpxchg8/16() using Zabha Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 11:53 ` Andrea Parri
2024-06-27 11:53 ` Andrea Parri
2024-06-29 19:19 ` Andrea Parri [this message]
2024-06-29 19:19 ` Andrea Parri
2024-07-04 16:36 ` Alexandre Ghiti
2024-07-04 16:36 ` Alexandre Ghiti
2024-07-09 23:51 ` Andrea Parri
2024-07-09 23:51 ` Andrea Parri
2024-07-15 12:56 ` Alexandre Ghiti
2024-07-15 12:56 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 04/10] riscv: Improve amocas.X use in cmpxchg() Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 13:31 ` Andrea Parri
2024-06-27 13:31 ` Andrea Parri
2024-07-04 16:40 ` Alexandre Ghiti
2024-07-04 16:40 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 05/10] riscv: Implement arch_cmpxchg128() using Zacas Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 06/10] riscv: Implement xchg8/16() using Zabha Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 13:45 ` Andrea Parri
2024-06-27 13:45 ` Andrea Parri
2024-07-04 17:25 ` Alexandre Ghiti
2024-07-04 17:25 ` Alexandre Ghiti
2024-07-10 1:37 ` Guo Ren
2024-07-10 1:37 ` Guo Ren
2024-07-15 13:20 ` Alexandre Ghiti
2024-07-15 13:20 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 07/10] riscv: Improve amoswap.X use in xchg() Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 13:58 ` Andrea Parri
2024-06-27 13:58 ` Andrea Parri
2024-07-04 17:26 ` Alexandre Ghiti
2024-07-04 17:26 ` Alexandre Ghiti
2024-07-10 0:09 ` Andrea Parri
2024-07-10 0:09 ` Andrea Parri
2024-06-26 13:03 ` [PATCH v2 08/10] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 09/10] asm-generic: ticket-lock: Add separate ticket-lock.h Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-26 13:03 ` [PATCH v2 10/10] riscv: Add qspinlock support based on Zabha extension Alexandre Ghiti
2024-06-26 13:03 ` Alexandre Ghiti
2024-06-27 15:19 ` Andrea Parri
2024-06-27 15:19 ` Andrea Parri
2024-07-04 17:33 ` Alexandre Ghiti
2024-07-04 17:33 ` Alexandre Ghiti
2024-07-07 2:20 ` Guo Ren
2024-07-07 2:20 ` Guo Ren
2024-07-08 11:51 ` Guo Ren
2024-07-08 11:51 ` Guo Ren
2024-07-15 7:33 ` Alexandre Ghiti
2024-07-15 7:33 ` Alexandre Ghiti
2024-07-15 7:27 ` Alexandre Ghiti
2024-07-15 7:27 ` Alexandre Ghiti
2024-07-15 19:30 ` Waiman Long
2024-07-15 19:30 ` Waiman Long
2024-07-16 1:04 ` Guo Ren
2024-07-16 1:04 ` Guo Ren
2024-07-16 6:43 ` Alexandre Ghiti
2024-07-16 6:43 ` Alexandre Ghiti
2024-07-16 8:31 ` Guo Ren
2024-07-16 8:31 ` Guo Ren
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
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