* [PATCH v2 0/2] riscv: spacemit: bananapi_f3: add support for Banana Pi F3 board
@ 2024-07-18 4:33 Kongyang Liu
2024-07-18 4:33 ` [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added Kongyang Liu
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Kongyang Liu @ 2024-07-18 4:33 UTC (permalink / raw)
To: u-boot
Cc: Ben Dooks, Bin Meng, Dan Carpenter, Frieder Schrempf,
Heinrich Schuchardt, Jonas Schwöbel, Kever Yang, Leo,
Michal Simek, Nishanth Menon, Padmarao Begari, Quentin Schulz,
Randolph, Rick Chen, Samuel Holland, Sumit Garg, Svyatoslav Ryhel,
Tom Rini, Yu Chien Peter Lin
Banana Pi F3 board is a industrial grade RISC-V development board, it
design with SpacemiT K1 8 core RISC-V chip, CPU integrates 2.0 TOPs AI
computing power. 4G DDR and 16G eMMC onboard.2x GbE Ethernet prot, 4x USB
3.0 and PCIe for M.2 interface, support HDMI and Dual MIPI-CSI Camera.
This patch introduces fundamental support for the Banana Pi F3 board,
encompassing UART, CPU, and PLIC support. This ensures that U-Boot can
operate in serial console mode.
Changes in v2:
- Change license to GPL-2.0-or-later
- Add memory node for dts
- Add ft_board_setup function for kernel memory init
- Use default prompt
Kongyang Liu (2):
riscv: spacemit: bananapi_f3: initial support added
doc: spacemit: bananapi_f3: document Banana Pi F3 board
arch/riscv/Kconfig | 5 +
arch/riscv/cpu/k1/Kconfig | 18 ++
arch/riscv/cpu/k1/Makefile | 6 +
arch/riscv/cpu/k1/cpu.c | 9 +
arch/riscv/cpu/k1/dram.c | 54 ++++
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/k1-bananapi-f3.dts | 25 ++
arch/riscv/dts/k1.dtsi | 375 +++++++++++++++++++++++++
board/spacemit/bananapi_f3/Kconfig | 25 ++
board/spacemit/bananapi_f3/MAINTAINERS | 6 +
board/spacemit/bananapi_f3/Makefile | 5 +
board/spacemit/bananapi_f3/board.c | 9 +
configs/bananapi_f3_defconfig | 20 ++
doc/board/index.rst | 1 +
doc/board/spacemit/bananapi_f3.rst | 78 +++++
doc/board/spacemit/index.rst | 8 +
include/configs/bananapi_f3.h | 15 +
17 files changed, 660 insertions(+)
create mode 100644 arch/riscv/cpu/k1/Kconfig
create mode 100644 arch/riscv/cpu/k1/Makefile
create mode 100644 arch/riscv/cpu/k1/cpu.c
create mode 100644 arch/riscv/cpu/k1/dram.c
create mode 100644 arch/riscv/dts/k1-bananapi-f3.dts
create mode 100644 arch/riscv/dts/k1.dtsi
create mode 100644 board/spacemit/bananapi_f3/Kconfig
create mode 100644 board/spacemit/bananapi_f3/MAINTAINERS
create mode 100644 board/spacemit/bananapi_f3/Makefile
create mode 100644 board/spacemit/bananapi_f3/board.c
create mode 100644 configs/bananapi_f3_defconfig
create mode 100644 doc/board/spacemit/bananapi_f3.rst
create mode 100644 doc/board/spacemit/index.rst
create mode 100644 include/configs/bananapi_f3.h
--
2.41.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added 2024-07-18 4:33 [PATCH v2 0/2] riscv: spacemit: bananapi_f3: add support for Banana Pi F3 board Kongyang Liu @ 2024-07-18 4:33 ` Kongyang Liu 2024-09-09 6:40 ` Leo Liang ` (2 more replies) 2024-07-18 4:33 ` [PATCH v2 2/2] doc: spacemit: bananapi_f3: document Banana Pi F3 board Kongyang Liu 2024-09-12 21:09 ` [PATCH v2 0/2] riscv: spacemit: bananapi_f3: add support for " Marcel Ziswiler 2 siblings, 3 replies; 9+ messages in thread From: Kongyang Liu @ 2024-07-18 4:33 UTC (permalink / raw) To: u-boot Cc: Ben Dooks, Bin Meng, Dan Carpenter, Heinrich Schuchardt, Leo, Michal Simek, Padmarao Begari, Randolph, Rick Chen, Samuel Holland, Tom Rini, Yu Chien Peter Lin Add basic support for SpacemiT's Banana Pi F3 board Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> --- Changes in v2: - Change license to GPL-2.0-or-later - Add memory node for dts - Add ft_board_setup function for kernel memory init - Use default prompt arch/riscv/Kconfig | 5 + arch/riscv/cpu/k1/Kconfig | 18 ++ arch/riscv/cpu/k1/Makefile | 6 + arch/riscv/cpu/k1/cpu.c | 9 + arch/riscv/cpu/k1/dram.c | 54 ++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ arch/riscv/dts/k1.dtsi | 375 +++++++++++++++++++++++++ board/spacemit/bananapi_f3/Kconfig | 25 ++ board/spacemit/bananapi_f3/MAINTAINERS | 6 + board/spacemit/bananapi_f3/Makefile | 5 + board/spacemit/bananapi_f3/board.c | 9 + configs/bananapi_f3_defconfig | 20 ++ include/configs/bananapi_f3.h | 15 + 14 files changed, 573 insertions(+) create mode 100644 arch/riscv/cpu/k1/Kconfig create mode 100644 arch/riscv/cpu/k1/Makefile create mode 100644 arch/riscv/cpu/k1/cpu.c create mode 100644 arch/riscv/cpu/k1/dram.c create mode 100644 arch/riscv/dts/k1-bananapi-f3.dts create mode 100644 arch/riscv/dts/k1.dtsi create mode 100644 board/spacemit/bananapi_f3/Kconfig create mode 100644 board/spacemit/bananapi_f3/MAINTAINERS create mode 100644 board/spacemit/bananapi_f3/Makefile create mode 100644 board/spacemit/bananapi_f3/board.c create mode 100644 configs/bananapi_f3_defconfig create mode 100644 include/configs/bananapi_f3.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa3b016c52..211f19a585 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,9 @@ choice config TARGET_ANDES_AE350 bool "Support Andes ae350" +config TARGET_BANANAPI_F3 + bool "Support BananaPi F3 Board" + config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" @@ -88,6 +91,7 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/sophgo/milkv_duo/Kconfig" +source "board/spacemit/bananapi_f3/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" @@ -99,6 +103,7 @@ source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" source "arch/riscv/cpu/jh7110/Kconfig" +source "arch/riscv/cpu/k1/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig new file mode 100644 index 0000000000..d9cd8dce96 --- /dev/null +++ b/arch/riscv/cpu/k1/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2024, Kongyang Liu <seashell11234455@gmail.com> + +config SPACEMIT_K1 + bool + select BINMAN + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply RISCV_ACLINT if RISCV_MMODE + imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE + imply CMD_CPU + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT diff --git a/arch/riscv/cpu/k1/Makefile b/arch/riscv/cpu/k1/Makefile new file mode 100644 index 0000000000..bad4f4cf46 --- /dev/null +++ b/arch/riscv/cpu/k1/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/k1/cpu.c b/arch/riscv/cpu/k1/cpu.c new file mode 100644 index 0000000000..41a4a1b95e --- /dev/null +++ b/arch/riscv/cpu/k1/cpu.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +int cleanup_before_linux(void) +{ + return 0; +} diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c new file mode 100644 index 0000000000..c477c15cbf --- /dev/null +++ b/arch/riscv/cpu/k1/dram.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +#include <asm/global_data.h> +#include <config.h> +#include <fdt_support.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_base = CFG_SYS_SDRAM_BASE; + /* TODO get ram size from ddr controller */ + gd->ram_size = SZ_4G; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); + + if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) { + gd->bd->bi_dram[1].start = 0x100000000; + gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + } + + return 0; +} + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + if (gd->ram_size > SZ_2G) + return SZ_2G; + + return gd->ram_size; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + start[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + + return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); +} diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 17cda483e1..71267f96f8 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts new file mode 100644 index 0000000000..06fd26578f --- /dev/null +++ b/arch/riscv/dts/k1-bananapi-f3.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> + */ + +#include "k1.dtsi" +#include "binman.dtsi" + +/ { + model = "Banana Pi BPI-F3"; + compatible = "bananapi,bpi-f3", "spacemit,k1"; + + chosen { + stdout-path = "serial0"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi new file mode 100644 index 0000000000..b301f45fd5 --- /dev/null +++ b/arch/riscv/dts/k1.dtsi @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> + */ + +/dts-v1/; +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SpacemiT K1"; + compatible = "spacemit,k1"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + serial8 = &uart9; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_0>; + }; + core1 { + cpu = <&cpu_1>; + }; + core2 { + cpu = <&cpu_2>; + }; + core3 { + cpu = <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_4>; + }; + core1 { + cpu = <&cpu_5>; + }; + core2 { + cpu = <&cpu_6>; + }; + core3 { + cpu = <&cpu_7>; + }; + }; + }; + + cpu_0: cpu@0 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_1: cpu@1 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <1>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_2: cpu@2 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <2>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_3: cpu@3 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <3>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_4: cpu@4 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <4>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + mmu-type = "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_5: cpu@5 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <5>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + mmu-type = "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_6: cpu@6 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <6>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + mmu-type = "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_7: cpu@7 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <7>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + mmu-type = "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + ranges; + + uart0: serial@d4017000 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017000 0x0 0x100>; + interrupts = <42>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@d4017100 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017100 0x0 0x100>; + interrupts = <44>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@d4017200 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017200 0x0 0x100>; + interrupts = <45>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@d4017300 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017300 0x0 0x100>; + interrupts = <46>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@d4017400 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017400 0x0 0x100>; + interrupts = <47>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart6: serial@d4017500 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017500 0x0 0x100>; + interrupts = <48>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart7: serial@d4017600 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017600 0x0 0x100>; + interrupts = <49>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart8: serial@d4017700 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017700 0x0 0x100>; + interrupts = <50>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart9: serial@d4017800 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017800 0x0 0x100>; + interrupts = <51>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xe0000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>, + <&cpu5_intc 11>, <&cpu5_intc 9>, + <&cpu6_intc 11>, <&cpu6_intc 9>, + <&cpu7_intc 11>, <&cpu7_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + riscv,ndev = <159>; + }; + + clint: timer@e4000000 { + compatible = "spacemit,k1-clint", "sifive,clint0"; + reg = <0x0 0xe4000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + }; +}; diff --git a/board/spacemit/bananapi_f3/Kconfig b/board/spacemit/bananapi_f3/Kconfig new file mode 100644 index 0000000000..0082a0d2af --- /dev/null +++ b/board/spacemit/bananapi_f3/Kconfig @@ -0,0 +1,25 @@ +if TARGET_BANANAPI_F3 + +config SYS_BOARD + default "bananapi_f3" + +config SYS_VENDOR + default "spacemit" + +config SYS_CPU + default "k1" + +config SYS_CONFIG_NAME + default "bananapi_f3" + +config TEXT_BASE + default 0x00200000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x00000000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SPACEMIT_K1 + +endif diff --git a/board/spacemit/bananapi_f3/MAINTAINERS b/board/spacemit/bananapi_f3/MAINTAINERS new file mode 100644 index 0000000000..fc0f8487e6 --- /dev/null +++ b/board/spacemit/bananapi_f3/MAINTAINERS @@ -0,0 +1,6 @@ +BananaPi F3 +M: Kongyang Liu <seashell11234455@gmail.com> +S: Maintained +F: board/spacemit/bananapi_f3/ +F: configs/bananapi_f3_defconfig +F: doc/board/spacemit/bananapi_f3.rst diff --git a/board/spacemit/bananapi_f3/Makefile b/board/spacemit/bananapi_f3/Makefile new file mode 100644 index 0000000000..2168698402 --- /dev/null +++ b/board/spacemit/bananapi_f3/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +obj-y := board.o diff --git a/board/spacemit/bananapi_f3/board.c b/board/spacemit/bananapi_f3/board.c new file mode 100644 index 0000000000..2631cdd49e --- /dev/null +++ b/board/spacemit/bananapi_f3/board.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +int board_init(void) +{ + return 0; +} diff --git a/configs/bananapi_f3_defconfig b/configs/bananapi_f3_defconfig new file mode 100644 index 0000000000..6363620208 --- /dev/null +++ b/configs/bananapi_f3_defconfig @@ -0,0 +1,20 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 +CONFIG_DEFAULT_DEVICE_TREE="k1-bananapi-f3" +CONFIG_SYS_LOAD_ADDR=0x200000 +CONFIG_TARGET_BANANAPI_F3=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0xa000000 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_HUSH_PARSER=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y diff --git a/include/configs/bananapi_f3.h b/include/configs/bananapi_f3.h new file mode 100644 index 0000000000..723bbaab69 --- /dev/null +++ b/include/configs/bananapi_f3.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/serial_reg.h> + +#define CFG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_NS16550_IER UART_IER_UUE + +#endif /* __CONFIG_H */ -- 2.41.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added 2024-07-18 4:33 ` [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added Kongyang Liu @ 2024-09-09 6:40 ` Leo Liang 2024-09-10 2:57 ` Leo Liang 2024-09-12 21:10 ` Marcel Ziswiler 2 siblings, 0 replies; 9+ messages in thread From: Leo Liang @ 2024-09-09 6:40 UTC (permalink / raw) To: Kongyang Liu Cc: u-boot, Ben Dooks, Bin Meng, Dan Carpenter, Heinrich Schuchardt, Michal Simek, Padmarao Begari, Randolph, Rick Chen, Samuel Holland, Tom Rini, Yu Chien Peter Lin On Thu, Jul 18, 2024 at 12:33:22PM +0800, Kongyang Liu wrote: > Add basic support for SpacemiT's Banana Pi F3 board > > Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> > --- > > Changes in v2: > - Change license to GPL-2.0-or-later > - Add memory node for dts > - Add ft_board_setup function for kernel memory init > - Use default prompt > > arch/riscv/Kconfig | 5 + > arch/riscv/cpu/k1/Kconfig | 18 ++ > arch/riscv/cpu/k1/Makefile | 6 + > arch/riscv/cpu/k1/cpu.c | 9 + > arch/riscv/cpu/k1/dram.c | 54 ++++ > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ > arch/riscv/dts/k1.dtsi | 375 +++++++++++++++++++++++++ > board/spacemit/bananapi_f3/Kconfig | 25 ++ > board/spacemit/bananapi_f3/MAINTAINERS | 6 + > board/spacemit/bananapi_f3/Makefile | 5 + > board/spacemit/bananapi_f3/board.c | 9 + > configs/bananapi_f3_defconfig | 20 ++ > include/configs/bananapi_f3.h | 15 + > 14 files changed, 573 insertions(+) > create mode 100644 arch/riscv/cpu/k1/Kconfig > create mode 100644 arch/riscv/cpu/k1/Makefile > create mode 100644 arch/riscv/cpu/k1/cpu.c > create mode 100644 arch/riscv/cpu/k1/dram.c > create mode 100644 arch/riscv/dts/k1-bananapi-f3.dts > create mode 100644 arch/riscv/dts/k1.dtsi > create mode 100644 board/spacemit/bananapi_f3/Kconfig > create mode 100644 board/spacemit/bananapi_f3/MAINTAINERS > create mode 100644 board/spacemit/bananapi_f3/Makefile > create mode 100644 board/spacemit/bananapi_f3/board.c > create mode 100644 configs/bananapi_f3_defconfig > create mode 100644 include/configs/bananapi_f3.h Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added 2024-07-18 4:33 ` [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added Kongyang Liu 2024-09-09 6:40 ` Leo Liang @ 2024-09-10 2:57 ` Leo Liang 2024-09-12 21:10 ` Marcel Ziswiler 2 siblings, 0 replies; 9+ messages in thread From: Leo Liang @ 2024-09-10 2:57 UTC (permalink / raw) To: Kongyang Liu Cc: u-boot, Ben Dooks, Bin Meng, Dan Carpenter, Heinrich Schuchardt, Michal Simek, Padmarao Begari, Randolph, Rick Chen, Samuel Holland, Tom Rini, Yu Chien Peter Lin On Thu, Jul 18, 2024 at 12:33:22PM +0800, Kongyang Liu wrote: > Add basic support for SpacemiT's Banana Pi F3 board > > Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> > --- > > Changes in v2: > - Change license to GPL-2.0-or-later > - Add memory node for dts > - Add ft_board_setup function for kernel memory init > - Use default prompt > > arch/riscv/Kconfig | 5 + > arch/riscv/cpu/k1/Kconfig | 18 ++ > arch/riscv/cpu/k1/Makefile | 6 + > arch/riscv/cpu/k1/cpu.c | 9 + > arch/riscv/cpu/k1/dram.c | 54 ++++ > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ > arch/riscv/dts/k1.dtsi | 375 +++++++++++++++++++++++++ > board/spacemit/bananapi_f3/Kconfig | 25 ++ > board/spacemit/bananapi_f3/MAINTAINERS | 6 + > board/spacemit/bananapi_f3/Makefile | 5 + > board/spacemit/bananapi_f3/board.c | 9 + > configs/bananapi_f3_defconfig | 20 ++ > include/configs/bananapi_f3.h | 15 + > 14 files changed, 573 insertions(+) > create mode 100644 arch/riscv/cpu/k1/Kconfig > create mode 100644 arch/riscv/cpu/k1/Makefile > create mode 100644 arch/riscv/cpu/k1/cpu.c > create mode 100644 arch/riscv/cpu/k1/dram.c > create mode 100644 arch/riscv/dts/k1-bananapi-f3.dts > create mode 100644 arch/riscv/dts/k1.dtsi > create mode 100644 board/spacemit/bananapi_f3/Kconfig > create mode 100644 board/spacemit/bananapi_f3/MAINTAINERS > create mode 100644 board/spacemit/bananapi_f3/Makefile > create mode 100644 board/spacemit/bananapi_f3/board.c > create mode 100644 configs/bananapi_f3_defconfig > create mode 100644 include/configs/bananapi_f3.h Hi Kongyang, `$ make bananapi_f3_defconfig && make` produces the following warning. In file included from drivers/serial/ns16550.c:13: include/ns16550.h:205:9: warning: "UART_IIR_ID" redefined 205 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | ^~~~~~~~~~~ In file included from include/configs/bananapi_f3.h:10, from include/config.h:3, from drivers/serial/ns16550.c:8: include/linux/serial_reg.h:33:9: note: this is the location of the previous definition 33 | #define UART_IIR_ID 0x0e /* Mask for the interrupt ID */ | ^~~~~~~~~~~ There seems to be Macro redefinition. Could you please take a look? Best regards, Leo > diff --git a/configs/bananapi_f3_defconfig b/configs/bananapi_f3_defconfig > new file mode 100644 > index 0000000000..6363620208 > --- /dev/null > +++ b/configs/bananapi_f3_defconfig > @@ -0,0 +1,20 @@ > +CONFIG_RISCV=y > +CONFIG_SYS_MALLOC_LEN=0x1000000 > +CONFIG_NR_DRAM_BANKS=2 > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 > +CONFIG_DEFAULT_DEVICE_TREE="k1-bananapi-f3" > +CONFIG_SYS_LOAD_ADDR=0x200000 > +CONFIG_TARGET_BANANAPI_F3=y > +CONFIG_ARCH_RV64I=y > +CONFIG_RISCV_SMODE=y > +CONFIG_FIT=y > +CONFIG_SYS_BOOTM_LEN=0xa000000 > +CONFIG_SUPPORT_RAW_INITRD=y > +CONFIG_OF_BOARD_SETUP=y > +CONFIG_SYS_CBSIZE=256 > +CONFIG_SYS_PBSIZE=276 > +CONFIG_HUSH_PARSER=y > +CONFIG_ENV_OVERWRITE=y > +CONFIG_SYS_NS16550=y > +CONFIG_SYS_NS16550_MEM32=y > diff --git a/include/configs/bananapi_f3.h b/include/configs/bananapi_f3.h > new file mode 100644 > index 0000000000..723bbaab69 > --- /dev/null > +++ b/include/configs/bananapi_f3.h > @@ -0,0 +1,15 @@ > +/* SPDX-License-Identifier: GPL-2.0-or-later */ > +/* > + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> > + * > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#include <linux/serial_reg.h> > + > +#define CFG_SYS_SDRAM_BASE 0x0 > +#define CFG_SYS_NS16550_IER UART_IER_UUE > + > +#endif /* __CONFIG_H */ ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added 2024-07-18 4:33 ` [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added Kongyang Liu 2024-09-09 6:40 ` Leo Liang 2024-09-10 2:57 ` Leo Liang @ 2024-09-12 21:10 ` Marcel Ziswiler 2 siblings, 0 replies; 9+ messages in thread From: Marcel Ziswiler @ 2024-09-12 21:10 UTC (permalink / raw) To: Kongyang Liu, u-boot Cc: Ben Dooks, Bin Meng, Dan Carpenter, Heinrich Schuchardt, Leo, Michal Simek, Padmarao Begari, Randolph, Rick Chen, Samuel Holland, Tom Rini, Yu Chien Peter Lin On Thu, 2024-07-18 at 12:33 +0800, Kongyang Liu wrote: > Add basic support for SpacemiT's Banana Pi F3 board > > Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> > > --- > > Changes in v2: > - Change license to GPL-2.0-or-later > - Add memory node for dts > - Add ft_board_setup function for kernel memory init > - Use default prompt > > arch/riscv/Kconfig | 5 + > arch/riscv/cpu/k1/Kconfig | 18 ++ > arch/riscv/cpu/k1/Makefile | 6 + > arch/riscv/cpu/k1/cpu.c | 9 + > arch/riscv/cpu/k1/dram.c | 54 ++++ > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ > arch/riscv/dts/k1.dtsi | 375 +++++++++++++++++++++++++ > board/spacemit/bananapi_f3/Kconfig | 25 ++ > board/spacemit/bananapi_f3/MAINTAINERS | 6 + > board/spacemit/bananapi_f3/Makefile | 5 + > board/spacemit/bananapi_f3/board.c | 9 + > configs/bananapi_f3_defconfig | 20 ++ > include/configs/bananapi_f3.h | 15 + > 14 files changed, 573 insertions(+) > create mode 100644 arch/riscv/cpu/k1/Kconfig > create mode 100644 arch/riscv/cpu/k1/Makefile > create mode 100644 arch/riscv/cpu/k1/cpu.c > create mode 100644 arch/riscv/cpu/k1/dram.c > create mode 100644 arch/riscv/dts/k1-bananapi-f3.dts > create mode 100644 arch/riscv/dts/k1.dtsi > create mode 100644 board/spacemit/bananapi_f3/Kconfig > create mode 100644 board/spacemit/bananapi_f3/MAINTAINERS > create mode 100644 board/spacemit/bananapi_f3/Makefile > create mode 100644 board/spacemit/bananapi_f3/board.c > create mode 100644 configs/bananapi_f3_defconfig > create mode 100644 include/configs/bananapi_f3.h > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index fa3b016c52..211f19a585 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -11,6 +11,9 @@ choice > config TARGET_ANDES_AE350 > bool "Support Andes ae350" > > +config TARGET_BANANAPI_F3 > + bool "Support BananaPi F3 Board" > + > config TARGET_MICROCHIP_ICICLE > bool "Support Microchip PolarFire-SoC Icicle Board" > > @@ -88,6 +91,7 @@ source "board/sifive/unleashed/Kconfig" > source "board/sifive/unmatched/Kconfig" > source "board/sipeed/maix/Kconfig" > source "board/sophgo/milkv_duo/Kconfig" > +source "board/spacemit/bananapi_f3/Kconfig" Other Banana Pi stuff already upstream uses dash rather than underscore: user@host:~/u-boot.git$ find doc/board/ -name '*banana*' doc/board/amlogic/bananapi-cm4io.rst doc/board/amlogic/bananapi-m2pro.rst doc/board/amlogic/bananapi-m2s.rst doc/board/amlogic/bananapi-m5.rst doc/board/spacemit/bananapi_f3.rst > source "board/starfive/visionfive2/Kconfig" > source "board/thead/th1520_lpi4a/Kconfig" > source "board/xilinx/mbv/Kconfig" > @@ -99,6 +103,7 @@ source "arch/riscv/cpu/fu540/Kconfig" > source "arch/riscv/cpu/fu740/Kconfig" > source "arch/riscv/cpu/generic/Kconfig" > source "arch/riscv/cpu/jh7110/Kconfig" > +source "arch/riscv/cpu/k1/Kconfig" > > # architecture-specific options below > > diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig > new file mode 100644 > index 0000000000..d9cd8dce96 > --- /dev/null > +++ b/arch/riscv/cpu/k1/Kconfig > @@ -0,0 +1,18 @@ > +# SPDX-License-Identifier: GPL-2.0-or-later > +# > +# Copyright (C) 2024, Kongyang Liu <seashell11234455@gmail.com> > + > +config SPACEMIT_K1 > + bool > + select BINMAN > + select ARCH_EARLY_INIT_R > + select SYS_CACHE_SHIFT_6 > + imply CPU > + imply CPU_RISCV > + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) > + imply RISCV_ACLINT if RISCV_MMODE > + imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE > + imply CMD_CPU > + imply SPL_CPU > + imply SPL_OPENSBI > + imply SPL_LOAD_FIT > diff --git a/arch/riscv/cpu/k1/Makefile b/arch/riscv/cpu/k1/Makefile > new file mode 100644 > index 0000000000..bad4f4cf46 > --- /dev/null > +++ b/arch/riscv/cpu/k1/Makefile > @@ -0,0 +1,6 @@ > +# SPDX-License-Identifier: GPL-2.0-or-later > +# > +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> > + > +obj-y += dram.o > +obj-y += cpu.o > diff --git a/arch/riscv/cpu/k1/cpu.c b/arch/riscv/cpu/k1/cpu.c > new file mode 100644 > index 0000000000..41a4a1b95e > --- /dev/null > +++ b/arch/riscv/cpu/k1/cpu.c > @@ -0,0 +1,9 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> > + */ > + > +int cleanup_before_linux(void) > +{ > + return 0; > +} > diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c > new file mode 100644 > index 0000000000..c477c15cbf > --- /dev/null > +++ b/arch/riscv/cpu/k1/dram.c > @@ -0,0 +1,54 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> > + */ > + > +#include <asm/global_data.h> > +#include <config.h> > +#include <fdt_support.h> > +#include <linux/sizes.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int dram_init(void) > +{ > + gd->ram_base = CFG_SYS_SDRAM_BASE; > + /* TODO get ram size from ddr controller */ > + gd->ram_size = SZ_4G; > + return 0; > +} > + > +int dram_init_banksize(void) > +{ > + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; > + gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); > + > + if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) { > + gd->bd->bi_dram[1].start = 0x100000000; > + gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; > + } > + > + return 0; > +} > + > +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) > +{ > + if (gd->ram_size > SZ_2G) > + return SZ_2G; > + > + return gd->ram_size; > +} > + > +int ft_board_setup(void *blob, struct bd_info *bd) > +{ > + u64 start[CONFIG_NR_DRAM_BANKS]; > + u64 size[CONFIG_NR_DRAM_BANKS]; > + int i; > + > + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { > + start[i] = gd->bd->bi_dram[i].start; > + size[i] = gd->bd->bi_dram[i].size; > + } > + > + return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); > +} > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile > index 17cda483e1..71267f96f8 100644 > --- a/arch/riscv/dts/Makefile > +++ b/arch/riscv/dts/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0+ > > dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb > +dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb > dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb > dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb > dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb > diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts > new file mode 100644 > index 0000000000..06fd26578f > --- /dev/null > +++ b/arch/riscv/dts/k1-bananapi-f3.dts > @@ -0,0 +1,25 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT Usually device tree sources use: GPL-2.0-or-later OR MIT > +/* > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> > + */ > + > +#include "k1.dtsi" > +#include "binman.dtsi" > + > +/ { > + model = "Banana Pi BPI-F3"; > + compatible = "bananapi,bpi-f3", "spacemit,k1"; > + > + chosen { > + stdout-path = "serial0"; > + }; > + > + memory@0 { > + device_type = "memory"; > + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi > new file mode 100644 > index 0000000000..b301f45fd5 > --- /dev/null > +++ b/arch/riscv/dts/k1.dtsi > @@ -0,0 +1,375 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT Ditto. > +/* > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> > + */ > + > +/dts-v1/; > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + model = "SpacemiT K1"; > + compatible = "spacemit,k1"; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart2; Intentional to skip uart1? > + serial2 = &uart3; > + serial3 = &uart4; > + serial4 = &uart5; > + serial5 = &uart6; > + serial6 = &uart7; > + serial7 = &uart8; > + serial8 = &uart9; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <24000000>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu_0>; > + }; > + core1 { > + cpu = <&cpu_1>; > + }; > + core2 { > + cpu = <&cpu_2>; > + }; > + core3 { > + cpu = <&cpu_3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu_4>; > + }; > + core1 { > + cpu = <&cpu_5>; > + }; > + core2 { > + cpu = <&cpu_6>; > + }; > + core3 { > + cpu = <&cpu_7>; > + }; > + }; > + }; > + > + cpu_0: cpu@0 { > + compatible = "spacemit,x60", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + riscv,isa = > "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh > _zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", > + "zifencei", "zihintpause", "zihpm", "zfh", "zba", > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; > + riscv,cbom-block-size = <64>; > + riscv,cbop-block-size = <64>; > + riscv,cboz-block-size = <64>; > + mmu-type = "riscv,sv39"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu_1: cpu@1 { > + compatible = "spacemit,x60", "riscv"; > + device_type = "cpu"; > + reg = <1>; > + riscv,isa = > "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh > _zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", > + "zifencei", "zihintpause", "zihpm", "zfh", "zba", > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; > + riscv,cbom-block-size = <64>; > + riscv,cbop-block-size = <64>; > + riscv,cboz-block-size = <64>; > + mmu-type = "riscv,sv39"; > + > + cpu1_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu_2: cpu@2 { > + compatible = "spacemit,x60", "riscv"; > + device_type = "cpu"; > + reg = <2>; > + riscv,isa = > "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh > _zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", > + "zifencei", "zihintpause", "zihpm", "zfh", "zba", > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; > + riscv,cbom-block-size = <64>; > + riscv,cbop-block-size = <64>; > + riscv,cboz-block-size = <64>; > + mmu-type = "riscv,sv39"; > + > + cpu2_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu_3: cpu@3 { > + compatible = "spacemit,x60", "riscv"; > + device_type = "cpu"; > + reg = <3>; > + riscv,isa = > "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh > _zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", > + "zifencei", "zihintpause", "zihpm", "zfh", "zba", > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; > + riscv,cbom-block-size = <64>; > + riscv,cbop-block-size = <64>; > + riscv,cboz-block-size = <64>; > + mmu-type = "riscv,sv39"; > + > + cpu3_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu_4: cpu@4 { > + compatible = "spacemit,x60", "riscv"; > + device_type = "cpu"; > + reg = <4>; > + riscv,isa = > "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh > _zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", > + "zifencei", "zihintpause", "zihpm", "zfh", "zba", > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; > + riscv,cbom-block-size = <64>; > + riscv,cbop-block-size = <64>; > + riscv,cboz-block-size = <64>; > + mmu-type = "riscv,sv39"; > + > + cpu4_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu_5: cpu@5 { > + compatible = "spacemit,x60", "riscv"; > + device_type = "cpu"; > + reg = <5>; > + riscv,isa = > "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh > _zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", > + "zifencei", "zihintpause", "zihpm", "zfh", "zba", > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; > + riscv,cbom-block-size = <64>; > + riscv,cbop-block-size = <64>; > + riscv,cboz-block-size = <64>; > + mmu-type = "riscv,sv39"; > + > + cpu5_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu_6: cpu@6 { > + compatible = "spacemit,x60", "riscv"; > + device_type = "cpu"; > + reg = <6>; > + riscv,isa = > "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh > _zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", > + "zifencei", "zihintpause", "zihpm", "zfh", "zba", > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; > + riscv,cbom-block-size = <64>; > + riscv,cbop-block-size = <64>; > + riscv,cboz-block-size = <64>; > + mmu-type = "riscv,sv39"; > + > + cpu6_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu_7: cpu@7 { > + compatible = "spacemit,x60", "riscv"; > + device_type = "cpu"; > + reg = <7>; > + riscv,isa = > "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh > _zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", > + "zifencei", "zihintpause", "zihpm", "zfh", "zba", > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; > + riscv,cbom-block-size = <64>; > + riscv,cbop-block-size = <64>; > + riscv,cboz-block-size = <64>; > + mmu-type = "riscv,sv39"; > + > + cpu7_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + soc { > + compatible = "simple-bus"; > + interrupt-parent = <&plic>; > + #address-cells = <2>; > + #size-cells = <2>; > + dma-noncoherent; > + ranges; > + > + uart0: serial@d4017000 { > + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xd4017000 0x0 0x100>; > + interrupts = <42>; > + clock-frequency = <14857000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart2: serial@d4017100 { > + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xd4017100 0x0 0x100>; > + interrupts = <44>; > + clock-frequency = <14857000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart3: serial@d4017200 { > + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xd4017200 0x0 0x100>; > + interrupts = <45>; > + clock-frequency = <14857000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart4: serial@d4017300 { > + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xd4017300 0x0 0x100>; > + interrupts = <46>; > + clock-frequency = <14857000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart5: serial@d4017400 { > + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xd4017400 0x0 0x100>; > + interrupts = <47>; > + clock-frequency = <14857000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart6: serial@d4017500 { > + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xd4017500 0x0 0x100>; > + interrupts = <48>; > + clock-frequency = <14857000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart7: serial@d4017600 { > + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xd4017600 0x0 0x100>; > + interrupts = <49>; > + clock-frequency = <14857000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart8: serial@d4017700 { > + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xd4017700 0x0 0x100>; > + interrupts = <50>; > + clock-frequency = <14857000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart9: serial@d4017800 { > + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xd4017800 0x0 0x100>; > + interrupts = <51>; > + clock-frequency = <14857000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + plic: interrupt-controller@e0000000 { > + compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; > + reg = <0x0 0xe0000000 0x0 0x4000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, > + <&cpu1_intc 11>, <&cpu1_intc 9>, > + <&cpu2_intc 11>, <&cpu2_intc 9>, > + <&cpu3_intc 11>, <&cpu3_intc 9>, > + <&cpu4_intc 11>, <&cpu4_intc 9>, > + <&cpu5_intc 11>, <&cpu5_intc 9>, > + <&cpu6_intc 11>, <&cpu6_intc 9>, > + <&cpu7_intc 11>, <&cpu7_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + riscv,ndev = <159>; > + }; > + > + clint: timer@e4000000 { > + compatible = "spacemit,k1-clint", "sifive,clint0"; > + reg = <0x0 0xe4000000 0x0 0x10000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > + <&cpu1_intc 3>, <&cpu1_intc 7>, > + <&cpu2_intc 3>, <&cpu2_intc 7>, > + <&cpu3_intc 3>, <&cpu3_intc 7>, > + <&cpu4_intc 3>, <&cpu4_intc 7>, > + <&cpu5_intc 3>, <&cpu5_intc 7>, > + <&cpu6_intc 3>, <&cpu6_intc 7>, > + <&cpu7_intc 3>, <&cpu7_intc 7>; > + }; > + }; > +}; > diff --git a/board/spacemit/bananapi_f3/Kconfig b/board/spacemit/bananapi_f3/Kconfig Ditto with the underscore vs. dash in the file resp. folder name. > new file mode 100644 > index 0000000000..0082a0d2af > --- /dev/null > +++ b/board/spacemit/bananapi_f3/Kconfig > @@ -0,0 +1,25 @@ > +if TARGET_BANANAPI_F3 > + > +config SYS_BOARD > + default "bananapi_f3" > + > +config SYS_VENDOR > + default "spacemit" > + > +config SYS_CPU > + default "k1" > + > +config SYS_CONFIG_NAME > + default "bananapi_f3" > + > +config TEXT_BASE > + default 0x00200000 > + > +config SPL_OPENSBI_LOAD_ADDR > + default 0x00000000 > + > +config BOARD_SPECIFIC_OPTIONS > + def_bool y > + select SPACEMIT_K1 > + > +endif > diff --git a/board/spacemit/bananapi_f3/MAINTAINERS b/board/spacemit/bananapi_f3/MAINTAINERS > new file mode 100644 > index 0000000000..fc0f8487e6 > --- /dev/null > +++ b/board/spacemit/bananapi_f3/MAINTAINERS > @@ -0,0 +1,6 @@ > +BananaPi F3 > +M: Kongyang Liu <seashell11234455@gmail.com> > +S: Maintained > +F: board/spacemit/bananapi_f3/ > +F: configs/bananapi_f3_defconfig > +F: doc/board/spacemit/bananapi_f3.rst > diff --git a/board/spacemit/bananapi_f3/Makefile b/board/spacemit/bananapi_f3/Makefile > new file mode 100644 > index 0000000000..2168698402 > --- /dev/null > +++ b/board/spacemit/bananapi_f3/Makefile > @@ -0,0 +1,5 @@ > +# SPDX-License-Identifier: GPL-2.0-or-later > +# > +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> > + > +obj-y := board.o > diff --git a/board/spacemit/bananapi_f3/board.c b/board/spacemit/bananapi_f3/board.c > new file mode 100644 > index 0000000000..2631cdd49e > --- /dev/null > +++ b/board/spacemit/bananapi_f3/board.c > @@ -0,0 +1,9 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> > + */ > + > +int board_init(void) > +{ > + return 0; > +} > diff --git a/configs/bananapi_f3_defconfig b/configs/bananapi_f3_defconfig do. > new file mode 100644 > index 0000000000..6363620208 > --- /dev/null > +++ b/configs/bananapi_f3_defconfig > @@ -0,0 +1,20 @@ > +CONFIG_RISCV=y > +CONFIG_SYS_MALLOC_LEN=0x1000000 > +CONFIG_NR_DRAM_BANKS=2 > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 > +CONFIG_DEFAULT_DEVICE_TREE="k1-bananapi-f3" > +CONFIG_SYS_LOAD_ADDR=0x200000 > +CONFIG_TARGET_BANANAPI_F3=y > +CONFIG_ARCH_RV64I=y > +CONFIG_RISCV_SMODE=y > +CONFIG_FIT=y > +CONFIG_SYS_BOOTM_LEN=0xa000000 > +CONFIG_SUPPORT_RAW_INITRD=y > +CONFIG_OF_BOARD_SETUP=y > +CONFIG_SYS_CBSIZE=256 > +CONFIG_SYS_PBSIZE=276 > +CONFIG_HUSH_PARSER=y > +CONFIG_ENV_OVERWRITE=y > +CONFIG_SYS_NS16550=y > +CONFIG_SYS_NS16550_MEM32=y > diff --git a/include/configs/bananapi_f3.h b/include/configs/bananapi_f3.h do. > new file mode 100644 > index 0000000000..723bbaab69 > --- /dev/null > +++ b/include/configs/bananapi_f3.h > @@ -0,0 +1,15 @@ > +/* SPDX-License-Identifier: GPL-2.0-or-later */ > +/* > + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> > + * > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#include <linux/serial_reg.h> > + > +#define CFG_SYS_SDRAM_BASE 0x0 > +#define CFG_SYS_NS16550_IER UART_IER_UUE > + > +#endif /* __CONFIG_H */ ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/2] doc: spacemit: bananapi_f3: document Banana Pi F3 board 2024-07-18 4:33 [PATCH v2 0/2] riscv: spacemit: bananapi_f3: add support for Banana Pi F3 board Kongyang Liu 2024-07-18 4:33 ` [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added Kongyang Liu @ 2024-07-18 4:33 ` Kongyang Liu 2024-09-09 6:41 ` Leo Liang 2024-09-12 21:10 ` Marcel Ziswiler 2024-09-12 21:09 ` [PATCH v2 0/2] riscv: spacemit: bananapi_f3: add support for " Marcel Ziswiler 2 siblings, 2 replies; 9+ messages in thread From: Kongyang Liu @ 2024-07-18 4:33 UTC (permalink / raw) To: u-boot Cc: Frieder Schrempf, Jonas Schwöbel, Kever Yang, Leo Yu-Chi Liang, Nishanth Menon, Quentin Schulz, Sumit Garg, Svyatoslav Ryhel, Tom Rini Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> --- (no changes since v1) doc/board/index.rst | 1 + doc/board/spacemit/bananapi_f3.rst | 78 ++++++++++++++++++++++++++++++ doc/board/spacemit/index.rst | 8 +++ 3 files changed, 87 insertions(+) create mode 100644 doc/board/spacemit/bananapi_f3.rst create mode 100644 doc/board/spacemit/index.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7a..367da2d623 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -51,6 +51,7 @@ Board-specific doc sipeed/index socionext/index sophgo/index + spacemit/index st/index starfive/index ste/index diff --git a/doc/board/spacemit/bananapi_f3.rst b/doc/board/spacemit/bananapi_f3.rst new file mode 100644 index 0000000000..cf3041085f --- /dev/null +++ b/doc/board/spacemit/bananapi_f3.rst @@ -0,0 +1,78 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Banana Pi F3 +============ + +About This +---------- +Banana Pi F3 board is a industrial grade RISC-V development board, it +design with SpacemiT K1 8 core RISC-V chip, CPU integrates 2.0 TOPs AI +computing power. 4G DDR and 16G eMMC onboard.2x GbE Ethernet prot, 4x USB +3.0 and PCIe for M.2 interface, support HDMI and Dual MIPI-CSI Camera. + +Building +~~~~~~~~ +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE=<riscv64 toolchain prefix> + +3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be +built for SpacemiT K1 SoC as below: + +.. code-block:: console + + git clone https://github.com/cyyself/opensbi -b k1-opensbi + cd opensbi + make PLATFORM=generic + +4. Then build U-Boot as following: + +.. code-block:: console + + cd <U-Boot-dir> + make bananapi_f3_defconfig + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin + +This will generate u-boot.itb + +Booting +~~~~~~~ +Currently, we use a modified vendor's U-Boot SPL to load a FIT image that +includes OpenSBI and U-Boot. Fully describing how to boot into U-Boot is a +challenging task. And the booting method will be added after the SPL +support is available. + +Sample boot log from Banana Pi F3 board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none + + U-Boot 2024.07-00686-g608f2d51760c (Jul 08 2024 - 14:53:51 +0800) + + DRAM: 4 GiB + Core: 18 devices, 7 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In: serial@d4017000 + Out: serial@d4017000 + Err: serial@d4017000 + Net: No ethernet found. + bananapi_f3# cpu detail + 0: cpu@0 spacemit,x60 + ID = 0, freq = 0 Hz: MMU + 1: cpu@1 spacemit,x60 + ID = 1, freq = 0 Hz: MMU + 2: cpu@2 spacemit,x60 + ID = 2, freq = 0 Hz: MMU + 3: cpu@3 spacemit,x60 + ID = 3, freq = 0 Hz: MMU + 4: cpu@4 spacemit,x60 + ID = 4, freq = 0 Hz: MMU + 5: cpu@5 spacemit,x60 + ID = 5, freq = 0 Hz: MMU + 6: cpu@6 spacemit,x60 + ID = 6, freq = 0 Hz: MMU + 7: cpu@7 spacemit,x60 + ID = 7, freq = 0 Hz: MMU + bananapi_f3# diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst new file mode 100644 index 0000000000..78081a47ff --- /dev/null +++ b/doc/board/spacemit/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +SpacemiT +======== +.. toctree:: + :maxdepth: 1 + + bananapi_f3 -- 2.41.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] doc: spacemit: bananapi_f3: document Banana Pi F3 board 2024-07-18 4:33 ` [PATCH v2 2/2] doc: spacemit: bananapi_f3: document Banana Pi F3 board Kongyang Liu @ 2024-09-09 6:41 ` Leo Liang 2024-09-12 21:10 ` Marcel Ziswiler 1 sibling, 0 replies; 9+ messages in thread From: Leo Liang @ 2024-09-09 6:41 UTC (permalink / raw) To: Kongyang Liu Cc: u-boot, Frieder Schrempf, Jonas Schwöbel, Kever Yang, Nishanth Menon, Quentin Schulz, Sumit Garg, Svyatoslav Ryhel, Tom Rini On Thu, Jul 18, 2024 at 12:33:23PM +0800, Kongyang Liu wrote: > Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC. > > Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> > --- > > (no changes since v1) > > doc/board/index.rst | 1 + > doc/board/spacemit/bananapi_f3.rst | 78 ++++++++++++++++++++++++++++++ > doc/board/spacemit/index.rst | 8 +++ > 3 files changed, 87 insertions(+) > create mode 100644 doc/board/spacemit/bananapi_f3.rst > create mode 100644 doc/board/spacemit/index.rst Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] doc: spacemit: bananapi_f3: document Banana Pi F3 board 2024-07-18 4:33 ` [PATCH v2 2/2] doc: spacemit: bananapi_f3: document Banana Pi F3 board Kongyang Liu 2024-09-09 6:41 ` Leo Liang @ 2024-09-12 21:10 ` Marcel Ziswiler 1 sibling, 0 replies; 9+ messages in thread From: Marcel Ziswiler @ 2024-09-12 21:10 UTC (permalink / raw) To: Kongyang Liu, u-boot Cc: Frieder Schrempf, Jonas Schwöbel, Kever Yang, Leo Yu-Chi Liang, Nishanth Menon, Quentin Schulz, Sumit Garg, Svyatoslav Ryhel, Tom Rini On Thu, 2024-07-18 at 12:33 +0800, Kongyang Liu wrote: > Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC. > > Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> > --- > > (no changes since v1) > > doc/board/index.rst | 1 + > doc/board/spacemit/bananapi_f3.rst | 78 ++++++++++++++++++++++++++++++ > doc/board/spacemit/index.rst | 8 +++ > 3 files changed, 87 insertions(+) > create mode 100644 doc/board/spacemit/bananapi_f3.rst > create mode 100644 doc/board/spacemit/index.rst > > diff --git a/doc/board/index.rst b/doc/board/index.rst > index 417c128c7a..367da2d623 100644 > --- a/doc/board/index.rst > +++ b/doc/board/index.rst > @@ -51,6 +51,7 @@ Board-specific doc > sipeed/index > socionext/index > sophgo/index > + spacemit/index > st/index > starfive/index > ste/index > diff --git a/doc/board/spacemit/bananapi_f3.rst b/doc/board/spacemit/bananapi_f3.rst > new file mode 100644 > index 0000000000..cf3041085f > --- /dev/null > +++ b/doc/board/spacemit/bananapi_f3.rst > @@ -0,0 +1,78 @@ > +.. SPDX-License-Identifier: GPL-2.0-or-later > + > +Banana Pi F3 > +============ > + > +About This > +---------- > +Banana Pi F3 board is a industrial grade RISC-V development board, it > +design with SpacemiT K1 8 core RISC-V chip, CPU integrates 2.0 TOPs AI > +computing power. 4G DDR and 16G eMMC onboard.2x GbE Ethernet prot, 4x USB do. missing space before 2x and port rather than prot > +3.0 and PCIe for M.2 interface, support HDMI and Dual MIPI-CSI Camera. > + > +Building > +~~~~~~~~ > +1. Add the RISC-V toolchain to your PATH. > +2. Setup ARCH & cross compilation environment variable: > + > +.. code-block:: console > + > + export CROSS_COMPILE=<riscv64 toolchain prefix> > + > +3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be > +built for SpacemiT K1 SoC as below: > + > +.. code-block:: console > + > + git clone https://github.com/cyyself/opensbi -b k1-opensbi > + cd opensbi > + make PLATFORM=generic > + > +4. Then build U-Boot as following: > + > +.. code-block:: console > + > + cd <U-Boot-dir> > + make bananapi_f3_defconfig > + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin > + > +This will generate u-boot.itb > + > +Booting > +~~~~~~~ > +Currently, we use a modified vendor's U-Boot SPL to load a FIT image that > +includes OpenSBI and U-Boot. Fully describing how to boot into U-Boot is a > +challenging task. And the booting method will be added after the SPL > +support is available. Hm, would be great if one could at least test it somehow on real hardware. We do have boards available BTW (;- p). > + > +Sample boot log from Banana Pi F3 board > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > +.. code-block:: none > + > + U-Boot 2024.07-00686-g608f2d51760c (Jul 08 2024 - 14:53:51 +0800) > + > + DRAM: 4 GiB > + Core: 18 devices, 7 uclasses, devicetree: separate > + Loading Environment from nowhere... OK > + In: serial@d4017000 > + Out: serial@d4017000 > + Err: serial@d4017000 > + Net: No ethernet found. > + bananapi_f3# cpu detail > + 0: cpu@0 spacemit,x60 > + ID = 0, freq = 0 Hz: MMU > + 1: cpu@1 spacemit,x60 > + ID = 1, freq = 0 Hz: MMU > + 2: cpu@2 spacemit,x60 > + ID = 2, freq = 0 Hz: MMU > + 3: cpu@3 spacemit,x60 > + ID = 3, freq = 0 Hz: MMU > + 4: cpu@4 spacemit,x60 > + ID = 4, freq = 0 Hz: MMU > + 5: cpu@5 spacemit,x60 > + ID = 5, freq = 0 Hz: MMU > + 6: cpu@6 spacemit,x60 > + ID = 6, freq = 0 Hz: MMU > + 7: cpu@7 spacemit,x60 > + ID = 7, freq = 0 Hz: MMU > + bananapi_f3# > diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst > new file mode 100644 > index 0000000000..78081a47ff > --- /dev/null > +++ b/doc/board/spacemit/index.rst > @@ -0,0 +1,8 @@ > +.. SPDX-License-Identifier: GPL-2.0-or-later > + > +SpacemiT > +======== > +.. toctree:: > + :maxdepth: 1 > + > + bananapi_f3 do. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/2] riscv: spacemit: bananapi_f3: add support for Banana Pi F3 board 2024-07-18 4:33 [PATCH v2 0/2] riscv: spacemit: bananapi_f3: add support for Banana Pi F3 board Kongyang Liu 2024-07-18 4:33 ` [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added Kongyang Liu 2024-07-18 4:33 ` [PATCH v2 2/2] doc: spacemit: bananapi_f3: document Banana Pi F3 board Kongyang Liu @ 2024-09-12 21:09 ` Marcel Ziswiler 2 siblings, 0 replies; 9+ messages in thread From: Marcel Ziswiler @ 2024-09-12 21:09 UTC (permalink / raw) To: Kongyang Liu, u-boot Cc: Ben Dooks, Bin Meng, Dan Carpenter, Frieder Schrempf, Heinrich Schuchardt, Jonas Schwöbel, Kever Yang, Leo, Michal Simek, Nishanth Menon, Padmarao Begari, Quentin Schulz, Randolph, Rick Chen, Samuel Holland, Sumit Garg, Svyatoslav Ryhel, Tom Rini, Yu Chien Peter Lin On Thu, 2024-07-18 at 12:33 +0800, Kongyang Liu wrote: > Banana Pi F3 board is a industrial grade RISC-V development board, it > design with SpacemiT K1 8 core RISC-V chip, CPU integrates 2.0 TOPs AI > computing power. 4G DDR and 16G eMMC onboard.2x GbE Ethernet prot, 4x USB missing space before 2x and port rather than prot > 3.0 and PCIe for M.2 interface, support HDMI and Dual MIPI-CSI Camera. > > This patch introduces fundamental support for the Banana Pi F3 board, > encompassing UART, CPU, and PLIC support. This ensures that U-Boot can > operate in serial console mode. > > Changes in v2: > - Change license to GPL-2.0-or-later > - Add memory node for dts > - Add ft_board_setup function for kernel memory init > - Use default prompt > > Kongyang Liu (2): > riscv: spacemit: bananapi_f3: initial support added > doc: spacemit: bananapi_f3: document Banana Pi F3 board > > arch/riscv/Kconfig | 5 + > arch/riscv/cpu/k1/Kconfig | 18 ++ > arch/riscv/cpu/k1/Makefile | 6 + > arch/riscv/cpu/k1/cpu.c | 9 + > arch/riscv/cpu/k1/dram.c | 54 ++++ > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ > arch/riscv/dts/k1.dtsi | 375 +++++++++++++++++++++++++ > board/spacemit/bananapi_f3/Kconfig | 25 ++ > board/spacemit/bananapi_f3/MAINTAINERS | 6 + > board/spacemit/bananapi_f3/Makefile | 5 + > board/spacemit/bananapi_f3/board.c | 9 + > configs/bananapi_f3_defconfig | 20 ++ > doc/board/index.rst | 1 + > doc/board/spacemit/bananapi_f3.rst | 78 +++++ > doc/board/spacemit/index.rst | 8 + > include/configs/bananapi_f3.h | 15 + > 17 files changed, 660 insertions(+) > create mode 100644 arch/riscv/cpu/k1/Kconfig > create mode 100644 arch/riscv/cpu/k1/Makefile > create mode 100644 arch/riscv/cpu/k1/cpu.c > create mode 100644 arch/riscv/cpu/k1/dram.c > create mode 100644 arch/riscv/dts/k1-bananapi-f3.dts > create mode 100644 arch/riscv/dts/k1.dtsi > create mode 100644 board/spacemit/bananapi_f3/Kconfig > create mode 100644 board/spacemit/bananapi_f3/MAINTAINERS > create mode 100644 board/spacemit/bananapi_f3/Makefile > create mode 100644 board/spacemit/bananapi_f3/board.c > create mode 100644 configs/bananapi_f3_defconfig > create mode 100644 doc/board/spacemit/bananapi_f3.rst > create mode 100644 doc/board/spacemit/index.rst > create mode 100644 include/configs/bananapi_f3.h ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-09-12 21:11 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-07-18 4:33 [PATCH v2 0/2] riscv: spacemit: bananapi_f3: add support for Banana Pi F3 board Kongyang Liu 2024-07-18 4:33 ` [PATCH v2 1/2] riscv: spacemit: bananapi_f3: initial support added Kongyang Liu 2024-09-09 6:40 ` Leo Liang 2024-09-10 2:57 ` Leo Liang 2024-09-12 21:10 ` Marcel Ziswiler 2024-07-18 4:33 ` [PATCH v2 2/2] doc: spacemit: bananapi_f3: document Banana Pi F3 board Kongyang Liu 2024-09-09 6:41 ` Leo Liang 2024-09-12 21:10 ` Marcel Ziswiler 2024-09-12 21:09 ` [PATCH v2 0/2] riscv: spacemit: bananapi_f3: add support for " Marcel Ziswiler
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