* [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
@ 2024-09-30 19:50 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
This adds a pin control driver created by Emil for the T-Head TH1520
RISC-V SoC used on the Lichee Pi 4A and BeagleV Ahead boards and updates
the device trees to make use of it.
Changes in v3:
- Add Rb from Rob for the binding
- Rebase on 6.12-rc1 which enables AP_SUBSYS clock controller in dts
- Update dts to use AP_SUBSYS clock controller instead of fixed clocks
- Remove unneeded defines from the driver for dt unit addresses
- Link to v2: https://lore.kernel.org/linux-riscv/20240914-th1520-pinctrl-v2-0-3ba67dde882c@tenstorrent.com/
Changes in v2:
- Add thead,pad-group device tree property
- Change driver to use the thead,pad-group property instead of the unit
address to identify the pad group of the pin controller being probed
- Return -EINVAL if no pin group can be determined during probe. In v1,
there was a bug that instead returned an unitialized variable
- Link to v1: https://lore.kernel.org/r/20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
Emil Renner Berthing (8):
dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings
pinctrl: Add driver for the T-Head TH1520 SoC
riscv: dts: thead: Add TH1520 pin control nodes
riscv: dts: thead: Add TH1520 GPIO ranges
riscv: dts: thead: Adjust TH1520 GPIO labels
riscv: dts: thead: Add Lichee Pi 4M GPIO line names
riscv: dts: thead: Add TH1520 pinctrl settings for UART0
riscv: dtb: thead: Add BeagleV Ahead LEDs
.../bindings/pinctrl/thead,th1520-pinctrl.yaml | 176 ++++
MAINTAINERS | 2 +
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 87 ++
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 43 +
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +
arch/riscv/boot/dts/thead/th1520.dtsi | 65 +-
drivers/pinctrl/Kconfig | 13 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-th1520.c | 907 +++++++++++++++++++++
9 files changed, 1306 insertions(+), 16 deletions(-)
---
base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc
change-id: 20240930-th1520-pinctrl-d42163ea2c11
Best regards,
--
Drew Fustini <dfustini@tenstorrent.com>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
@ 2024-09-30 19:50 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
This adds a pin control driver created by Emil for the T-Head TH1520
RISC-V SoC used on the Lichee Pi 4A and BeagleV Ahead boards and updates
the device trees to make use of it.
Changes in v3:
- Add Rb from Rob for the binding
- Rebase on 6.12-rc1 which enables AP_SUBSYS clock controller in dts
- Update dts to use AP_SUBSYS clock controller instead of fixed clocks
- Remove unneeded defines from the driver for dt unit addresses
- Link to v2: https://lore.kernel.org/linux-riscv/20240914-th1520-pinctrl-v2-0-3ba67dde882c@tenstorrent.com/
Changes in v2:
- Add thead,pad-group device tree property
- Change driver to use the thead,pad-group property instead of the unit
address to identify the pad group of the pin controller being probed
- Return -EINVAL if no pin group can be determined during probe. In v1,
there was a bug that instead returned an unitialized variable
- Link to v1: https://lore.kernel.org/r/20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
Emil Renner Berthing (8):
dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings
pinctrl: Add driver for the T-Head TH1520 SoC
riscv: dts: thead: Add TH1520 pin control nodes
riscv: dts: thead: Add TH1520 GPIO ranges
riscv: dts: thead: Adjust TH1520 GPIO labels
riscv: dts: thead: Add Lichee Pi 4M GPIO line names
riscv: dts: thead: Add TH1520 pinctrl settings for UART0
riscv: dtb: thead: Add BeagleV Ahead LEDs
.../bindings/pinctrl/thead,th1520-pinctrl.yaml | 176 ++++
MAINTAINERS | 2 +
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 87 ++
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 43 +
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +
arch/riscv/boot/dts/thead/th1520.dtsi | 65 +-
drivers/pinctrl/Kconfig | 13 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-th1520.c | 907 +++++++++++++++++++++
9 files changed, 1306 insertions(+), 16 deletions(-)
---
base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc
change-id: 20240930-th1520-pinctrl-d42163ea2c11
Best regards,
--
Drew Fustini <dfustini@tenstorrent.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v3 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings
2024-09-30 19:50 ` Drew Fustini
@ 2024-09-30 19:50 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[dfustini: add thead,pad-group to select the pin controller instance]
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
.../bindings/pinctrl/thead,th1520-pinctrl.yaml | 176 +++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 177 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
new file mode 100644
index 000000000000..21f86740a63d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-Head TH1520 SoC pin controller
+
+maintainers:
+ - Emil Renner Berthing <emil.renner.berthing@canonical.com>
+
+description: |
+ Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC.
+
+ The TH1520 has 3 groups of pads each controlled from different memory ranges.
+ Confusingly the memory ranges are named
+ PADCTRL_AOSYS -> PAD Group 1
+ PADCTRL1_APSYS -> PAD Group 2
+ PADCTRL0_APSYS -> PAD Group 3
+
+ Each pad can be muxed individually to up to 6 different functions. For most
+ pads only a few of those 6 configurations are valid though, and a few pads in
+ group 1 does not support muxing at all.
+
+ Pinconf is fairly regular except for a few pads in group 1 that either can't
+ be configured or has some special functions. The rest have configurable drive
+ strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in
+ addition to a special strong pull up.
+
+ Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and
+ are then meant to be used by the audio co-processor. Each such pad can then
+ be further muxed to either audio GPIO or one of 4 functions such as UART, I2C
+ and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is
+ also configured in different registers. All of this is done from a different
+ AUDIO_IOCTRL memory range and is left to the audio co-processor for now.
+
+properties:
+ compatible:
+ enum:
+ - thead,th1520-pinctrl
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ thead,pad-group:
+ description: |
+ Select the pad group that is associated with the pin controller instance.
+
+ Base Address Name Group
+ 0xFF_FFF4_A000 PADCTRL_AOSYS 1
+ 0xFF_E7F3_C000 PADCTRL1_APSYS 2
+ 0xFF_EC00_7000 PADCTRL0_APSYS 3
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3]
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+patternProperties:
+ '-[0-9]+$':
+ type: object
+ additionalProperties: false
+
+ patternProperties:
+ '-pins$':
+ type: object
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml#
+ - $ref: /schemas/pinctrl/pinmux-node.yaml#
+
+ additionalProperties: false
+
+ description:
+ A pinctrl node should contain at least one subnode describing one
+ or more pads and their associated pinmux and pinconf settings.
+
+ properties:
+ pins:
+ description: List of pads that properties in the node apply to.
+
+ function:
+ enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s,
+ gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug,
+ clock, jtag, iso7816, efuse, reset ]
+ description: The mux function to select for the given pins.
+
+ bias-disable: true
+
+ bias-pull-up:
+ oneOf:
+ - type: boolean
+ description: Enable the regular 48kOhm pull-up
+ - enum: [ 2100, 48000 ]
+ description: Enable the strong 2.1kOhm pull-up or regular 48kOhm pull-up
+
+ bias-pull-down:
+ oneOf:
+ - type: boolean
+ - const: 44000
+ description: Enable the regular 44kOhm pull-down
+
+ drive-strength:
+ enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25 ]
+ description: Drive strength in mA
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ maximum: 1
+
+ required:
+ - pins
+
+additionalProperties: false
+
+examples:
+ - |
+ padctrl0_apsys: pinctrl@ec007000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xec007000 0x1000>;
+ clocks = <&apb_clk>;
+ thead,pad-group = <3>;
+
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pins = "UART0_TXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <3>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pins = "UART0_RXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <1>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+ };
+
+ padctrl1_apsys: pinctrl@e7f3c000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xe7f3c000 0x1000>;
+ clocks = <&apb_clk>;
+ thead,pad-group = <2>;
+
+ i2c5_pins: i2c5-0 {
+ i2c-pins {
+ pins = "QSPI1_CSN0", /* I2C5_SCL */
+ "QSPI1_D0_MOSI"; /* I2C5_SDA */
+ function = "i2c";
+ bias-pull-up = <2100>;
+ drive-strength = <7>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index c27f3190737f..dd74c9aa2009 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19942,6 +19942,7 @@ L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://github.com/pdp7/linux.git
F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
+F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
F: arch/riscv/boot/dts/thead/
F: drivers/clk/thead/clk-th1520-ap.c
F: include/dt-bindings/clock/thead,th1520-clk-ap.h
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings
@ 2024-09-30 19:50 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[dfustini: add thead,pad-group to select the pin controller instance]
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
.../bindings/pinctrl/thead,th1520-pinctrl.yaml | 176 +++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 177 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
new file mode 100644
index 000000000000..21f86740a63d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-Head TH1520 SoC pin controller
+
+maintainers:
+ - Emil Renner Berthing <emil.renner.berthing@canonical.com>
+
+description: |
+ Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC.
+
+ The TH1520 has 3 groups of pads each controlled from different memory ranges.
+ Confusingly the memory ranges are named
+ PADCTRL_AOSYS -> PAD Group 1
+ PADCTRL1_APSYS -> PAD Group 2
+ PADCTRL0_APSYS -> PAD Group 3
+
+ Each pad can be muxed individually to up to 6 different functions. For most
+ pads only a few of those 6 configurations are valid though, and a few pads in
+ group 1 does not support muxing at all.
+
+ Pinconf is fairly regular except for a few pads in group 1 that either can't
+ be configured or has some special functions. The rest have configurable drive
+ strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in
+ addition to a special strong pull up.
+
+ Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and
+ are then meant to be used by the audio co-processor. Each such pad can then
+ be further muxed to either audio GPIO or one of 4 functions such as UART, I2C
+ and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is
+ also configured in different registers. All of this is done from a different
+ AUDIO_IOCTRL memory range and is left to the audio co-processor for now.
+
+properties:
+ compatible:
+ enum:
+ - thead,th1520-pinctrl
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ thead,pad-group:
+ description: |
+ Select the pad group that is associated with the pin controller instance.
+
+ Base Address Name Group
+ 0xFF_FFF4_A000 PADCTRL_AOSYS 1
+ 0xFF_E7F3_C000 PADCTRL1_APSYS 2
+ 0xFF_EC00_7000 PADCTRL0_APSYS 3
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3]
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+patternProperties:
+ '-[0-9]+$':
+ type: object
+ additionalProperties: false
+
+ patternProperties:
+ '-pins$':
+ type: object
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml#
+ - $ref: /schemas/pinctrl/pinmux-node.yaml#
+
+ additionalProperties: false
+
+ description:
+ A pinctrl node should contain at least one subnode describing one
+ or more pads and their associated pinmux and pinconf settings.
+
+ properties:
+ pins:
+ description: List of pads that properties in the node apply to.
+
+ function:
+ enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s,
+ gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug,
+ clock, jtag, iso7816, efuse, reset ]
+ description: The mux function to select for the given pins.
+
+ bias-disable: true
+
+ bias-pull-up:
+ oneOf:
+ - type: boolean
+ description: Enable the regular 48kOhm pull-up
+ - enum: [ 2100, 48000 ]
+ description: Enable the strong 2.1kOhm pull-up or regular 48kOhm pull-up
+
+ bias-pull-down:
+ oneOf:
+ - type: boolean
+ - const: 44000
+ description: Enable the regular 44kOhm pull-down
+
+ drive-strength:
+ enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25 ]
+ description: Drive strength in mA
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ maximum: 1
+
+ required:
+ - pins
+
+additionalProperties: false
+
+examples:
+ - |
+ padctrl0_apsys: pinctrl@ec007000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xec007000 0x1000>;
+ clocks = <&apb_clk>;
+ thead,pad-group = <3>;
+
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pins = "UART0_TXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <3>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pins = "UART0_RXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <1>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+ };
+
+ padctrl1_apsys: pinctrl@e7f3c000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xe7f3c000 0x1000>;
+ clocks = <&apb_clk>;
+ thead,pad-group = <2>;
+
+ i2c5_pins: i2c5-0 {
+ i2c-pins {
+ pins = "QSPI1_CSN0", /* I2C5_SCL */
+ "QSPI1_D0_MOSI"; /* I2C5_SDA */
+ function = "i2c";
+ bias-pull-up = <2100>;
+ drive-strength = <7>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index c27f3190737f..dd74c9aa2009 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19942,6 +19942,7 @@ L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://github.com/pdp7/linux.git
F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
+F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
F: arch/riscv/boot/dts/thead/
F: drivers/clk/thead/clk-th1520-ap.c
F: include/dt-bindings/clock/thead,th1520-clk-ap.h
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
2024-09-30 19:50 ` Drew Fustini
@ 2024-09-30 19:50 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add pinctrl driver for the T-Head TH1520 RISC-V SoC.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[dfustini: use thead,pad-group to identify the pin controller instance]
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
MAINTAINERS | 1 +
drivers/pinctrl/Kconfig | 13 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-th1520.c | 907 +++++++++++++++++++++++++++++++++++++++
4 files changed, 922 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index dd74c9aa2009..67634f0ea30e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19945,6 +19945,7 @@ F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
F: arch/riscv/boot/dts/thead/
F: drivers/clk/thead/clk-th1520-ap.c
+F: drivers/pinctrl/pinctrl-th1520.c
F: include/dt-bindings/clock/thead,th1520-clk-ap.h
RNBD BLOCK DRIVERS
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 354536de564b..5bf58e138ce3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -551,6 +551,19 @@ config PINCTRL_TPS6594
This driver can also be built as a module
called tps6594-pinctrl.
+config PINCTRL_TH1520
+ tristate "Pinctrl driver for the T-Head TH1520 SoC"
+ depends on ARCH_THEAD || COMPILE_TEST
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ select PINMUX
+ help
+ This is the driver for the pin controller blocks on the
+ T-Head TH1520 SoC.
+
+ This driver is needed for RISC-V development boards like
+ the BeagleV Ahead and the LicheePi 4A.
+
config PINCTRL_ZYNQ
bool "Pinctrl driver for Xilinx Zynq"
depends on ARCH_ZYNQ
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 97823f52b972..26180a616d13 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_TPS6594) += pinctrl-tps6594.o
+obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c
new file mode 100644
index 000000000000..1bb78b212fd5
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-th1520.c
@@ -0,0 +1,907 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl driver for the T-Head TH1520 SoC
+ *
+ * Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com>
+ */
+
+#include <linux/array_size.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "core.h"
+#include "pinmux.h"
+#include "pinconf.h"
+
+#define TH1520_PADCFG_IE BIT(9)
+#define TH1520_PADCFG_SL BIT(8)
+#define TH1520_PADCFG_ST BIT(7)
+#define TH1520_PADCFG_SPU BIT(6)
+#define TH1520_PADCFG_PS BIT(5)
+#define TH1520_PADCFG_PE BIT(4)
+#define TH1520_PADCFG_BIAS (TH1520_PADCFG_SPU | TH1520_PADCFG_PS | TH1520_PADCFG_PE)
+#define TH1520_PADCFG_DS GENMASK(3, 0)
+
+#define TH1520_PULL_DOWN_OHM 44000 /* typ. 44kOhm */
+#define TH1520_PULL_UP_OHM 48000 /* typ. 48kOhm */
+#define TH1520_PULL_STRONG_OHM 2100 /* typ. 2.1kOhm */
+
+#define TH1520_PAD_NO_PADCFG BIT(30)
+#define TH1520_PAD_MUXDATA GENMASK(29, 0)
+
+struct th1520_pad_group {
+ const char *name;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+};
+
+struct th1520_pinctrl {
+ struct pinctrl_desc desc;
+ struct mutex mutex; /* serialize adding functions */
+ raw_spinlock_t lock; /* serialize register access */
+ void __iomem *base;
+ struct pinctrl_dev *pctl;
+};
+
+static void __iomem *th1520_padcfg(struct th1520_pinctrl *thp,
+ unsigned int pin)
+{
+ return thp->base + 4 * (pin / 2);
+}
+
+static unsigned int th1520_padcfg_shift(unsigned int pin)
+{
+ return 16 * (pin & BIT(0));
+}
+
+static void __iomem *th1520_muxcfg(struct th1520_pinctrl *thp,
+ unsigned int pin)
+{
+ return thp->base + 0x400 + 4 * (pin / 8);
+}
+
+static unsigned int th1520_muxcfg_shift(unsigned int pin)
+{
+ return 4 * (pin & GENMASK(2, 0));
+}
+
+enum th1520_muxtype {
+ TH1520_MUX_____,
+ TH1520_MUX_GPIO,
+ TH1520_MUX_PWM,
+ TH1520_MUX_UART,
+ TH1520_MUX_IR,
+ TH1520_MUX_I2C,
+ TH1520_MUX_SPI,
+ TH1520_MUX_QSPI,
+ TH1520_MUX_SDIO,
+ TH1520_MUX_AUD,
+ TH1520_MUX_I2S,
+ TH1520_MUX_MAC0,
+ TH1520_MUX_MAC1,
+ TH1520_MUX_DPU0,
+ TH1520_MUX_DPU1,
+ TH1520_MUX_ISP,
+ TH1520_MUX_HDMI,
+ TH1520_MUX_BSEL,
+ TH1520_MUX_DBG,
+ TH1520_MUX_CLK,
+ TH1520_MUX_JTAG,
+ TH1520_MUX_ISO,
+ TH1520_MUX_FUSE,
+ TH1520_MUX_RST,
+};
+
+static const char *const th1520_muxtype_string[] = {
+ [TH1520_MUX_GPIO] = "gpio",
+ [TH1520_MUX_PWM] = "pwm",
+ [TH1520_MUX_UART] = "uart",
+ [TH1520_MUX_IR] = "ir",
+ [TH1520_MUX_I2C] = "i2c",
+ [TH1520_MUX_SPI] = "spi",
+ [TH1520_MUX_QSPI] = "qspi",
+ [TH1520_MUX_SDIO] = "sdio",
+ [TH1520_MUX_AUD] = "audio",
+ [TH1520_MUX_I2S] = "i2s",
+ [TH1520_MUX_MAC0] = "gmac0",
+ [TH1520_MUX_MAC1] = "gmac1",
+ [TH1520_MUX_DPU0] = "dpu0",
+ [TH1520_MUX_DPU1] = "dpu1",
+ [TH1520_MUX_ISP] = "isp",
+ [TH1520_MUX_HDMI] = "hdmi",
+ [TH1520_MUX_BSEL] = "bootsel",
+ [TH1520_MUX_DBG] = "debug",
+ [TH1520_MUX_CLK] = "clock",
+ [TH1520_MUX_JTAG] = "jtag",
+ [TH1520_MUX_ISO] = "iso7816",
+ [TH1520_MUX_FUSE] = "efuse",
+ [TH1520_MUX_RST] = "reset",
+};
+
+static enum th1520_muxtype th1520_muxtype_get(const char *str)
+{
+ enum th1520_muxtype mt;
+
+ for (mt = TH1520_MUX_GPIO; mt < ARRAY_SIZE(th1520_muxtype_string); mt++) {
+ if (!strcmp(str, th1520_muxtype_string[mt]))
+ return mt;
+ }
+ return TH1520_MUX_____;
+}
+
+#define TH1520_PAD(_nr, _name, m0, m1, m2, m3, m4, m5, _flags) \
+ { .number = _nr, .name = #_name, .drv_data = (void *)((_flags) | \
+ (TH1520_MUX_##m0 << 0) | (TH1520_MUX_##m1 << 5) | (TH1520_MUX_##m2 << 10) | \
+ (TH1520_MUX_##m3 << 15) | (TH1520_MUX_##m4 << 20) | (TH1520_MUX_##m5 << 25)) }
+
+static const struct pinctrl_pin_desc th1520_group1_pins[] = {
+ TH1520_PAD(0, OSC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(1, OSC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(2, SYS_RST_N, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(3, RTC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(4, RTC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ /* skip number 5 so we can calculate register offsets and shifts from the pin number */
+ TH1520_PAD(6, TEST_MODE, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(7, DEBUG_MODE, DBG, ____, ____, GPIO, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(8, POR_SEL, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(9, I2C_AON_SCL, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(10, I2C_AON_SDA, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(11, CPU_JTG_TCLK, JTAG, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(12, CPU_JTG_TMS, JTAG, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(13, CPU_JTG_TDI, JTAG, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(14, CPU_JTG_TDO, JTAG, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(15, CPU_JTG_TRST, JTAG, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(16, AOGPIO_7, CLK, AUD, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(17, AOGPIO_8, UART, AUD, IR, GPIO, ____, ____, 0),
+ TH1520_PAD(18, AOGPIO_9, UART, AUD, IR, GPIO, ____, ____, 0),
+ TH1520_PAD(19, AOGPIO_10, CLK, AUD, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(20, AOGPIO_11, GPIO, AUD, ____, ____, ____, ____, 0),
+ TH1520_PAD(21, AOGPIO_12, GPIO, AUD, ____, ____, ____, ____, 0),
+ TH1520_PAD(22, AOGPIO_13, GPIO, AUD, ____, ____, ____, ____, 0),
+ TH1520_PAD(23, AOGPIO_14, GPIO, AUD, ____, ____, ____, ____, 0),
+ TH1520_PAD(24, AOGPIO_15, GPIO, AUD, ____, ____, ____, ____, 0),
+ TH1520_PAD(25, AUDIO_PA0, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(26, AUDIO_PA1, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(27, AUDIO_PA2, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(28, AUDIO_PA3, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(29, AUDIO_PA4, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(30, AUDIO_PA5, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(31, AUDIO_PA6, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(32, AUDIO_PA7, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(33, AUDIO_PA8, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(34, AUDIO_PA9, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(35, AUDIO_PA10, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(36, AUDIO_PA11, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(37, AUDIO_PA12, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(38, AUDIO_PA13, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(39, AUDIO_PA14, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(40, AUDIO_PA15, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(41, AUDIO_PA16, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(42, AUDIO_PA17, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(43, AUDIO_PA27, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(44, AUDIO_PA28, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(45, AUDIO_PA29, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(46, AUDIO_PA30, AUD, RST, ____, GPIO, ____, ____, 0),
+};
+
+static const struct pinctrl_pin_desc th1520_group2_pins[] = {
+ TH1520_PAD(0, QSPI1_SCLK, QSPI, ISO, ____, GPIO, FUSE, ____, 0),
+ TH1520_PAD(1, QSPI1_CSN0, QSPI, ____, I2C, GPIO, FUSE, ____, 0),
+ TH1520_PAD(2, QSPI1_D0_MOSI, QSPI, ISO, I2C, GPIO, FUSE, ____, 0),
+ TH1520_PAD(3, QSPI1_D1_MISO, QSPI, ISO, ____, GPIO, FUSE, ____, 0),
+ TH1520_PAD(4, QSPI1_D2_WP, QSPI, ISO, UART, GPIO, FUSE, ____, 0),
+ TH1520_PAD(5, QSPI1_D3_HOLD, QSPI, ISO, UART, GPIO, ____, ____, 0),
+ TH1520_PAD(6, I2C0_SCL, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(7, I2C0_SDA, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(8, I2C1_SCL, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(9, I2C1_SDA, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(10, UART1_TXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(11, UART1_RXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(12, UART4_TXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(13, UART4_RXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(14, UART4_CTSN, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(15, UART4_RTSN, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(16, UART3_TXD, DBG, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(17, UART3_RXD, DBG, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(18, GPIO0_18, GPIO, I2C, ____, ____, ____, ____, 0),
+ TH1520_PAD(19, GPIO0_19, GPIO, I2C, ____, ____, ____, ____, 0),
+ TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, ____, ____, 0),
+ TH1520_PAD(21, GPIO0_21, GPIO, UART, IR, ____, DPU0, DPU1, 0),
+ TH1520_PAD(22, GPIO0_22, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0),
+ TH1520_PAD(23, GPIO0_23, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0),
+ TH1520_PAD(24, GPIO0_24, GPIO, JTAG, QSPI, ____, DPU0, DPU1, 0),
+ TH1520_PAD(25, GPIO0_25, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(26, GPIO0_26, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(27, GPIO0_27, GPIO, ____, I2C, ____, DPU0, DPU1, 0),
+ TH1520_PAD(28, GPIO0_28, GPIO, ____, I2C, ____, DPU0, DPU1, 0),
+ TH1520_PAD(29, GPIO0_29, GPIO, ____, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(30, GPIO0_30, GPIO, ____, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(31, GPIO0_31, GPIO, ____, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(32, GPIO1_0, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(33, GPIO1_1, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(34, GPIO1_2, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(35, GPIO1_3, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(36, GPIO1_4, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(37, GPIO1_5, GPIO, ____, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(38, GPIO1_6, GPIO, ____, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(39, GPIO1_7, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(40, GPIO1_8, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(41, GPIO1_9, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(42, GPIO1_10, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(43, GPIO1_11, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(44, GPIO1_12, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(45, GPIO1_13, GPIO, UART, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(46, GPIO1_14, GPIO, UART, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(47, GPIO1_15, GPIO, UART, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(48, GPIO1_16, GPIO, UART, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(49, CLK_OUT_0, BSEL, CLK, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(50, CLK_OUT_1, BSEL, CLK, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(51, CLK_OUT_2, BSEL, CLK, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(52, CLK_OUT_3, BSEL, CLK, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(53, GPIO1_21, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(54, GPIO1_22, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(55, GPIO1_23, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(56, GPIO1_24, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(57, GPIO1_25, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(58, GPIO1_26, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(59, GPIO1_27, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(60, GPIO1_28, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(61, GPIO1_29, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(62, GPIO1_30, GPIO, ____, ISP, ____, ____, ____, 0),
+};
+
+static const struct pinctrl_pin_desc th1520_group3_pins[] = {
+ TH1520_PAD(0, UART0_TXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(1, UART0_RXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(2, QSPI0_SCLK, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(3, QSPI0_CSN0, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(4, QSPI0_CSN1, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(8, QSPI1_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(11, I2C3_SCL, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(12, I2C3_SDA, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(13, GPIO2_13, GPIO, SPI, ____, ____, ____, ____, 0),
+ TH1520_PAD(14, SPI_SCLK, SPI, UART, IR, GPIO, ____, ____, 0),
+ TH1520_PAD(15, SPI_CSN, SPI, UART, IR, GPIO, ____, ____, 0),
+ TH1520_PAD(16, SPI_MOSI, SPI, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(17, SPI_MISO, SPI, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(18, GPIO2_18, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(19, GPIO2_19, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(20, GPIO2_20, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(21, GPIO2_21, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(22, GPIO2_22, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(23, GPIO2_23, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(24, GPIO2_24, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(25, GPIO2_25, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(26, SDIO0_WPRTN, SDIO, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(27, SDIO0_DETN, SDIO, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(28, SDIO1_WPRTN, SDIO, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(29, SDIO1_DETN, SDIO, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(30, GPIO2_30, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(31, GPIO2_31, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(32, GPIO3_0, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(33, GPIO3_1, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(34, GPIO3_2, GPIO, PWM, ____, ____, ____, ____, 0),
+ TH1520_PAD(35, GPIO3_3, GPIO, PWM, ____, ____, ____, ____, 0),
+ TH1520_PAD(36, HDMI_SCL, HDMI, PWM, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(37, HDMI_SDA, HDMI, PWM, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(38, HDMI_CEC, HDMI, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(39, GMAC0_TX_CLK, MAC0, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(40, GMAC0_RX_CLK, MAC0, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(41, GMAC0_TXEN, MAC0, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(42, GMAC0_TXD0, MAC0, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(43, GMAC0_TXD1, MAC0, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(44, GMAC0_TXD2, MAC0, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(45, GMAC0_TXD3, MAC0, I2C, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(46, GMAC0_RXDV, MAC0, I2C, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(47, GMAC0_RXD0, MAC0, I2C, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(48, GMAC0_RXD1, MAC0, I2C, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(49, GMAC0_RXD2, MAC0, SPI, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(50, GMAC0_RXD3, MAC0, SPI, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(51, GMAC0_MDC, MAC0, SPI, MAC1, GPIO, ____, ____, 0),
+ TH1520_PAD(52, GMAC0_MDIO, MAC0, SPI, MAC1, GPIO, ____, ____, 0),
+ TH1520_PAD(53, GMAC0_COL, MAC0, PWM, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(54, GMAC0_CRS, MAC0, PWM, ____, GPIO, ____, ____, 0),
+};
+
+static const struct th1520_pad_group th1520_group1 = {
+ .name = "th1520-group1",
+ .pins = th1520_group1_pins,
+ .npins = ARRAY_SIZE(th1520_group1_pins),
+};
+
+static const struct th1520_pad_group th1520_group2 = {
+ .name = "th1520-group2",
+ .pins = th1520_group2_pins,
+ .npins = ARRAY_SIZE(th1520_group2_pins),
+};
+
+static const struct th1520_pad_group th1520_group3 = {
+ .name = "th1520-group3",
+ .pins = th1520_group3_pins,
+ .npins = ARRAY_SIZE(th1520_group3_pins),
+};
+
+static int th1520_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+
+ return thp->desc.npins;
+}
+
+static const char *th1520_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int gsel)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+
+ return thp->desc.pins[gsel].name;
+}
+
+static int th1520_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int gsel,
+ const unsigned int **pins,
+ unsigned int *npins)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = &thp->desc.pins[gsel].number;
+ *npins = 1;
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void th1520_pin_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int pin)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ void __iomem *padcfg = th1520_padcfg(thp, pin);
+ void __iomem *muxcfg = th1520_muxcfg(thp, pin);
+ u32 pad;
+ u32 mux;
+
+ scoped_guard(raw_spinlock_irqsave, &thp->lock) {
+ pad = readl_relaxed(padcfg);
+ mux = readl_relaxed(muxcfg);
+ }
+
+ seq_printf(s, "[PADCFG_%03u:0x%x=0x%07x MUXCFG_%03u:0x%x=0x%08x]",
+ 1 + pin / 2, 0x000 + 4 * (pin / 2), pad,
+ 1 + pin / 8, 0x400 + 4 * (pin / 8), mux);
+}
+#else
+#define th1520_pin_dbg_show NULL
+#endif
+
+static void th1520_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned int nmaps)
+{
+ unsigned long *seen = NULL;
+ unsigned int i;
+
+ for (i = 0; i < nmaps; i++) {
+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN &&
+ map[i].data.configs.configs != seen) {
+ seen = map[i].data.configs.configs;
+ kfree(seen);
+ }
+ }
+
+ kfree(map);
+}
+
+static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **maps,
+ unsigned int *num_maps)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ struct device_node *child;
+ struct pinctrl_map *map;
+ unsigned long *configs;
+ unsigned int nconfigs;
+ unsigned int nmaps;
+ int ret;
+
+ nmaps = 0;
+ for_each_available_child_of_node(np, child) {
+ int npins = of_property_count_strings(child, "pins");
+
+ if (npins <= 0) {
+ of_node_put(child);
+ dev_err(thp->pctl->dev, "no pins selected for %pOFn.%pOFn\n",
+ np, child);
+ return -EINVAL;
+ }
+ nmaps += npins;
+ if (of_property_present(child, "function"))
+ nmaps += npins;
+ }
+
+ map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
+ if (!map)
+ return -ENOMEM;
+
+ nmaps = 0;
+ mutex_lock(&thp->mutex);
+ for_each_available_child_of_node(np, child) {
+ unsigned int rollback = nmaps;
+ enum th1520_muxtype muxtype;
+ struct property *prop;
+ const char *funcname;
+ const char **pgnames;
+ const char *pinname;
+ int npins;
+
+ ret = pinconf_generic_parse_dt_config(child, pctldev, &configs, &nconfigs);
+ if (ret) {
+ dev_err(thp->pctl->dev, "%pOFn.%pOFn: error parsing pin config\n",
+ np, child);
+ goto put_child;
+ }
+
+ if (!of_property_read_string(child, "function", &funcname)) {
+ muxtype = th1520_muxtype_get(funcname);
+ if (!muxtype) {
+ dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown function '%s'\n",
+ np, child, funcname);
+ ret = -EINVAL;
+ goto free_configs;
+ }
+
+ funcname = devm_kasprintf(thp->pctl->dev, GFP_KERNEL, "%pOFn.%pOFn",
+ np, child);
+ if (!funcname) {
+ ret = -ENOMEM;
+ goto free_configs;
+ }
+
+ npins = of_property_count_strings(child, "pins");
+ pgnames = devm_kcalloc(thp->pctl->dev, npins, sizeof(*pgnames), GFP_KERNEL);
+ if (!pgnames) {
+ ret = -ENOMEM;
+ goto free_configs;
+ }
+ } else {
+ funcname = NULL;
+ }
+
+ npins = 0;
+ of_property_for_each_string(child, "pins", prop, pinname) {
+ unsigned int i;
+
+ for (i = 0; i < thp->desc.npins; i++) {
+ if (!strcmp(pinname, thp->desc.pins[i].name))
+ break;
+ }
+ if (i == thp->desc.npins) {
+ nmaps = rollback;
+ dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown pin '%s'\n",
+ np, child, pinname);
+ goto free_configs;
+ }
+
+ if (nconfigs) {
+ map[nmaps].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ map[nmaps].data.configs.group_or_pin = thp->desc.pins[i].name;
+ map[nmaps].data.configs.configs = configs;
+ map[nmaps].data.configs.num_configs = nconfigs;
+ nmaps += 1;
+ }
+ if (funcname) {
+ pgnames[npins++] = thp->desc.pins[i].name;
+ map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
+ map[nmaps].data.mux.function = funcname;
+ map[nmaps].data.mux.group = thp->desc.pins[i].name;
+ nmaps += 1;
+ }
+ }
+
+ if (funcname) {
+ ret = pinmux_generic_add_function(pctldev, funcname, pgnames,
+ npins, (void *)muxtype);
+ if (ret < 0) {
+ dev_err(thp->pctl->dev, "error adding function %s\n", funcname);
+ goto put_child;
+ }
+ }
+ }
+
+ *maps = map;
+ *num_maps = nmaps;
+ mutex_unlock(&thp->mutex);
+ return 0;
+
+free_configs:
+ kfree(configs);
+put_child:
+ of_node_put(child);
+ th1520_pinctrl_dt_free_map(pctldev, map, nmaps);
+ mutex_unlock(&thp->mutex);
+ return ret;
+}
+
+static const struct pinctrl_ops th1520_pinctrl_ops = {
+ .get_groups_count = th1520_pinctrl_get_groups_count,
+ .get_group_name = th1520_pinctrl_get_group_name,
+ .get_group_pins = th1520_pinctrl_get_group_pins,
+ .pin_dbg_show = th1520_pin_dbg_show,
+ .dt_node_to_map = th1520_pinctrl_dt_node_to_map,
+ .dt_free_map = th1520_pinctrl_dt_free_map,
+};
+
+static const u8 th1520_drive_strength_in_ma[16] = {
+ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25,
+};
+
+static u16 th1520_drive_strength_from_ma(u32 arg)
+{
+ u16 ds;
+
+ for (ds = 0; ds < TH1520_PADCFG_DS; ds++) {
+ if (arg <= th1520_drive_strength_in_ma[ds])
+ return ds;
+ }
+ return TH1520_PADCFG_DS;
+}
+
+static int th1520_padcfg_rmw(struct th1520_pinctrl *thp, unsigned int pin,
+ u32 mask, u32 value)
+{
+ void __iomem *padcfg = th1520_padcfg(thp, pin);
+ unsigned int shift = th1520_padcfg_shift(pin);
+ u32 tmp;
+
+ mask <<= shift;
+ value <<= shift;
+
+ scoped_guard(raw_spinlock_irqsave, &thp->lock) {
+ tmp = readl_relaxed(padcfg);
+ tmp = (tmp & ~mask) | value;
+ writel_relaxed(tmp, padcfg);
+ }
+ return 0;
+}
+
+static int th1520_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ const struct pin_desc *desc = pin_desc_get(pctldev, pin);
+ bool enabled;
+ int param;
+ u32 value;
+ u32 arg;
+
+ if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG)
+ return -EOPNOTSUPP;
+
+ value = readl_relaxed(th1520_padcfg(thp, pin));
+ value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0);
+
+ param = pinconf_to_config_param(*config);
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ enabled = !(value & (TH1520_PADCFG_SPU | TH1520_PADCFG_PE));
+ arg = 0;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ enabled = (value & TH1520_PADCFG_BIAS) == TH1520_PADCFG_PE;
+ arg = enabled ? TH1520_PULL_DOWN_OHM : 0;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (value & TH1520_PADCFG_SPU) {
+ enabled = true;
+ arg = TH1520_PULL_STRONG_OHM;
+ } else if ((value & (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) ==
+ (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) {
+ enabled = true;
+ arg = TH1520_PULL_UP_OHM;
+ } else {
+ enabled = false;
+ arg = 0;
+ }
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ enabled = true;
+ arg = th1520_drive_strength_in_ma[value & TH1520_PADCFG_DS];
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ enabled = value & TH1520_PADCFG_IE;
+ arg = enabled ? 1 : 0;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ enabled = value & TH1520_PADCFG_ST;
+ arg = enabled ? 1 : 0;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ enabled = value & TH1520_PADCFG_SL;
+ arg = enabled ? 1 : 0;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+ return enabled ? 0 : -EINVAL;
+}
+
+static int th1520_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned int gsel, unsigned long *config)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int pin = thp->desc.pins[gsel].number;
+
+ return th1520_pinconf_get(pctldev, pin, config);
+}
+
+static int th1520_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ const struct pin_desc *desc = pin_desc_get(pctldev, pin);
+ unsigned int i;
+ u16 mask, value;
+
+ if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG)
+ return -EOPNOTSUPP;
+
+ mask = 0;
+ value = 0;
+ for (i = 0; i < num_configs; i++) {
+ int param = pinconf_to_config_param(configs[i]);
+ u32 arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ mask |= TH1520_PADCFG_BIAS;
+ value &= ~TH1520_PADCFG_BIAS;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (arg == 0)
+ return -EOPNOTSUPP;
+ mask |= TH1520_PADCFG_BIAS;
+ value &= ~TH1520_PADCFG_BIAS;
+ value |= TH1520_PADCFG_PE;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (arg == 0)
+ return -EOPNOTSUPP;
+ mask |= TH1520_PADCFG_BIAS;
+ value &= ~TH1520_PADCFG_BIAS;
+ if (arg == TH1520_PULL_STRONG_OHM)
+ value |= TH1520_PADCFG_SPU;
+ else
+ value |= TH1520_PADCFG_PE | TH1520_PADCFG_PS;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ mask |= TH1520_PADCFG_DS;
+ value &= ~TH1520_PADCFG_DS;
+ value |= th1520_drive_strength_from_ma(arg);
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ mask |= TH1520_PADCFG_IE;
+ if (arg)
+ value |= TH1520_PADCFG_IE;
+ else
+ value &= ~TH1520_PADCFG_IE;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ mask |= TH1520_PADCFG_ST;
+ if (arg)
+ value |= TH1520_PADCFG_ST;
+ else
+ value &= ~TH1520_PADCFG_ST;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ mask |= TH1520_PADCFG_SL;
+ if (arg)
+ value |= TH1520_PADCFG_SL;
+ else
+ value &= ~TH1520_PADCFG_SL;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+ }
+
+ return th1520_padcfg_rmw(thp, pin, mask, value);
+}
+
+static int th1520_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned int gsel,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int pin = thp->desc.pins[gsel].number;
+
+ return th1520_pinconf_set(pctldev, pin, configs, num_configs);
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void th1520_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int pin)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ u32 value = readl_relaxed(th1520_padcfg(thp, pin));
+
+ value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0);
+
+ seq_printf(s, " [0x%03x]", value);
+}
+#else
+#define th1520_pinconf_dbg_show NULL
+#endif
+
+static const struct pinconf_ops th1520_pinconf_ops = {
+ .pin_config_get = th1520_pinconf_get,
+ .pin_config_group_get = th1520_pinconf_group_get,
+ .pin_config_set = th1520_pinconf_set,
+ .pin_config_group_set = th1520_pinconf_group_set,
+ .pin_config_dbg_show = th1520_pinconf_dbg_show,
+ .is_generic = true,
+};
+
+static int th1520_pinmux_set(struct th1520_pinctrl *thp, unsigned int pin,
+ unsigned long muxdata, enum th1520_muxtype muxtype)
+{
+ void __iomem *muxcfg = th1520_muxcfg(thp, pin);
+ unsigned int shift = th1520_muxcfg_shift(pin);
+ u32 mask, value, tmp;
+
+ for (value = 0; muxdata; muxdata >>= 5, value++) {
+ if ((muxdata & GENMASK(4, 0)) == muxtype)
+ break;
+ }
+ if (!muxdata) {
+ dev_err(thp->pctl->dev, "invalid mux %s for pin %s\n",
+ th1520_muxtype_string[muxtype], pin_get_name(thp->pctl, pin));
+ return -EINVAL;
+ }
+
+ mask = GENMASK(3, 0) << shift;
+ value = value << shift;
+
+ scoped_guard(raw_spinlock_irqsave, &thp->lock) {
+ tmp = readl_relaxed(muxcfg);
+ tmp = (tmp & ~mask) | value;
+ writel_relaxed(tmp, muxcfg);
+ }
+ return 0;
+}
+
+static int th1520_pinmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int fsel, unsigned int gsel)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ const struct function_desc *func = pinmux_generic_get_function(pctldev, fsel);
+
+ return th1520_pinmux_set(thp, thp->desc.pins[gsel].number,
+ (uintptr_t)thp->desc.pins[gsel].drv_data & TH1520_PAD_MUXDATA,
+ (uintptr_t)func->data);
+}
+
+static int th1520_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ const struct pin_desc *desc = pin_desc_get(pctldev, offset);
+
+ return th1520_pinmux_set(thp, offset,
+ (uintptr_t)desc->drv_data & TH1520_PAD_MUXDATA,
+ TH1520_MUX_GPIO);
+}
+
+static int th1520_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset, bool input)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+
+ return th1520_padcfg_rmw(thp, offset, TH1520_PADCFG_IE,
+ input ? TH1520_PADCFG_IE : 0);
+}
+
+static const struct pinmux_ops th1520_pinmux_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = th1520_pinmux_set_mux,
+ .gpio_request_enable = th1520_gpio_request_enable,
+ .gpio_set_direction = th1520_gpio_set_direction,
+ .strict = true,
+};
+
+static int th1520_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct th1520_pad_group *group;
+ struct device_node *np = dev->of_node;
+ struct th1520_pinctrl *thp;
+ struct clk *clk;
+ u32 pin_group;
+ int ret;
+
+ thp = devm_kzalloc(dev, sizeof(*thp), GFP_KERNEL);
+ if (!thp)
+ return -ENOMEM;
+
+ thp->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(thp->base))
+ return PTR_ERR(thp->base);
+
+ clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "error getting clock\n");
+
+ ret = of_property_read_u32(np, "thead,pad-group", &pin_group);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to read the thead,pad-group property\n");
+
+ if (pin_group == 1)
+ group = &th1520_group1;
+ else if (pin_group == 2)
+ group = &th1520_group2;
+ else if (pin_group == 3)
+ group = &th1520_group3;
+ else
+ return dev_err_probe(dev, -EINVAL, "unit address did not match any pad group\n");
+
+ thp->desc.name = group->name;
+ thp->desc.pins = group->pins;
+ thp->desc.npins = group->npins;
+ thp->desc.pctlops = &th1520_pinctrl_ops;
+ thp->desc.pmxops = &th1520_pinmux_ops;
+ thp->desc.confops = &th1520_pinconf_ops;
+ thp->desc.owner = THIS_MODULE;
+ mutex_init(&thp->mutex);
+ raw_spin_lock_init(&thp->lock);
+
+ ret = devm_pinctrl_register_and_init(dev, &thp->desc, thp, &thp->pctl);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
+
+ return pinctrl_enable(thp->pctl);
+}
+
+static const struct of_device_id th1520_pinctrl_of_match[] = {
+ { .compatible = "thead,th1520-pinctrl"},
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, th1520_pinctrl_of_match);
+
+static struct platform_driver th1520_pinctrl_driver = {
+ .probe = th1520_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-th1520",
+ .of_match_table = th1520_pinctrl_of_match,
+ },
+};
+module_platform_driver(th1520_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for the T-Head TH1520 SoC");
+MODULE_AUTHOR("Emil Renner Berthing <emil.renner.berthing@canonical.com>");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
@ 2024-09-30 19:50 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add pinctrl driver for the T-Head TH1520 RISC-V SoC.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[dfustini: use thead,pad-group to identify the pin controller instance]
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
MAINTAINERS | 1 +
drivers/pinctrl/Kconfig | 13 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-th1520.c | 907 +++++++++++++++++++++++++++++++++++++++
4 files changed, 922 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index dd74c9aa2009..67634f0ea30e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19945,6 +19945,7 @@ F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
F: arch/riscv/boot/dts/thead/
F: drivers/clk/thead/clk-th1520-ap.c
+F: drivers/pinctrl/pinctrl-th1520.c
F: include/dt-bindings/clock/thead,th1520-clk-ap.h
RNBD BLOCK DRIVERS
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 354536de564b..5bf58e138ce3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -551,6 +551,19 @@ config PINCTRL_TPS6594
This driver can also be built as a module
called tps6594-pinctrl.
+config PINCTRL_TH1520
+ tristate "Pinctrl driver for the T-Head TH1520 SoC"
+ depends on ARCH_THEAD || COMPILE_TEST
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ select PINMUX
+ help
+ This is the driver for the pin controller blocks on the
+ T-Head TH1520 SoC.
+
+ This driver is needed for RISC-V development boards like
+ the BeagleV Ahead and the LicheePi 4A.
+
config PINCTRL_ZYNQ
bool "Pinctrl driver for Xilinx Zynq"
depends on ARCH_ZYNQ
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 97823f52b972..26180a616d13 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_TPS6594) += pinctrl-tps6594.o
+obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c
new file mode 100644
index 000000000000..1bb78b212fd5
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-th1520.c
@@ -0,0 +1,907 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl driver for the T-Head TH1520 SoC
+ *
+ * Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com>
+ */
+
+#include <linux/array_size.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "core.h"
+#include "pinmux.h"
+#include "pinconf.h"
+
+#define TH1520_PADCFG_IE BIT(9)
+#define TH1520_PADCFG_SL BIT(8)
+#define TH1520_PADCFG_ST BIT(7)
+#define TH1520_PADCFG_SPU BIT(6)
+#define TH1520_PADCFG_PS BIT(5)
+#define TH1520_PADCFG_PE BIT(4)
+#define TH1520_PADCFG_BIAS (TH1520_PADCFG_SPU | TH1520_PADCFG_PS | TH1520_PADCFG_PE)
+#define TH1520_PADCFG_DS GENMASK(3, 0)
+
+#define TH1520_PULL_DOWN_OHM 44000 /* typ. 44kOhm */
+#define TH1520_PULL_UP_OHM 48000 /* typ. 48kOhm */
+#define TH1520_PULL_STRONG_OHM 2100 /* typ. 2.1kOhm */
+
+#define TH1520_PAD_NO_PADCFG BIT(30)
+#define TH1520_PAD_MUXDATA GENMASK(29, 0)
+
+struct th1520_pad_group {
+ const char *name;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+};
+
+struct th1520_pinctrl {
+ struct pinctrl_desc desc;
+ struct mutex mutex; /* serialize adding functions */
+ raw_spinlock_t lock; /* serialize register access */
+ void __iomem *base;
+ struct pinctrl_dev *pctl;
+};
+
+static void __iomem *th1520_padcfg(struct th1520_pinctrl *thp,
+ unsigned int pin)
+{
+ return thp->base + 4 * (pin / 2);
+}
+
+static unsigned int th1520_padcfg_shift(unsigned int pin)
+{
+ return 16 * (pin & BIT(0));
+}
+
+static void __iomem *th1520_muxcfg(struct th1520_pinctrl *thp,
+ unsigned int pin)
+{
+ return thp->base + 0x400 + 4 * (pin / 8);
+}
+
+static unsigned int th1520_muxcfg_shift(unsigned int pin)
+{
+ return 4 * (pin & GENMASK(2, 0));
+}
+
+enum th1520_muxtype {
+ TH1520_MUX_____,
+ TH1520_MUX_GPIO,
+ TH1520_MUX_PWM,
+ TH1520_MUX_UART,
+ TH1520_MUX_IR,
+ TH1520_MUX_I2C,
+ TH1520_MUX_SPI,
+ TH1520_MUX_QSPI,
+ TH1520_MUX_SDIO,
+ TH1520_MUX_AUD,
+ TH1520_MUX_I2S,
+ TH1520_MUX_MAC0,
+ TH1520_MUX_MAC1,
+ TH1520_MUX_DPU0,
+ TH1520_MUX_DPU1,
+ TH1520_MUX_ISP,
+ TH1520_MUX_HDMI,
+ TH1520_MUX_BSEL,
+ TH1520_MUX_DBG,
+ TH1520_MUX_CLK,
+ TH1520_MUX_JTAG,
+ TH1520_MUX_ISO,
+ TH1520_MUX_FUSE,
+ TH1520_MUX_RST,
+};
+
+static const char *const th1520_muxtype_string[] = {
+ [TH1520_MUX_GPIO] = "gpio",
+ [TH1520_MUX_PWM] = "pwm",
+ [TH1520_MUX_UART] = "uart",
+ [TH1520_MUX_IR] = "ir",
+ [TH1520_MUX_I2C] = "i2c",
+ [TH1520_MUX_SPI] = "spi",
+ [TH1520_MUX_QSPI] = "qspi",
+ [TH1520_MUX_SDIO] = "sdio",
+ [TH1520_MUX_AUD] = "audio",
+ [TH1520_MUX_I2S] = "i2s",
+ [TH1520_MUX_MAC0] = "gmac0",
+ [TH1520_MUX_MAC1] = "gmac1",
+ [TH1520_MUX_DPU0] = "dpu0",
+ [TH1520_MUX_DPU1] = "dpu1",
+ [TH1520_MUX_ISP] = "isp",
+ [TH1520_MUX_HDMI] = "hdmi",
+ [TH1520_MUX_BSEL] = "bootsel",
+ [TH1520_MUX_DBG] = "debug",
+ [TH1520_MUX_CLK] = "clock",
+ [TH1520_MUX_JTAG] = "jtag",
+ [TH1520_MUX_ISO] = "iso7816",
+ [TH1520_MUX_FUSE] = "efuse",
+ [TH1520_MUX_RST] = "reset",
+};
+
+static enum th1520_muxtype th1520_muxtype_get(const char *str)
+{
+ enum th1520_muxtype mt;
+
+ for (mt = TH1520_MUX_GPIO; mt < ARRAY_SIZE(th1520_muxtype_string); mt++) {
+ if (!strcmp(str, th1520_muxtype_string[mt]))
+ return mt;
+ }
+ return TH1520_MUX_____;
+}
+
+#define TH1520_PAD(_nr, _name, m0, m1, m2, m3, m4, m5, _flags) \
+ { .number = _nr, .name = #_name, .drv_data = (void *)((_flags) | \
+ (TH1520_MUX_##m0 << 0) | (TH1520_MUX_##m1 << 5) | (TH1520_MUX_##m2 << 10) | \
+ (TH1520_MUX_##m3 << 15) | (TH1520_MUX_##m4 << 20) | (TH1520_MUX_##m5 << 25)) }
+
+static const struct pinctrl_pin_desc th1520_group1_pins[] = {
+ TH1520_PAD(0, OSC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(1, OSC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(2, SYS_RST_N, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(3, RTC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(4, RTC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ /* skip number 5 so we can calculate register offsets and shifts from the pin number */
+ TH1520_PAD(6, TEST_MODE, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(7, DEBUG_MODE, DBG, ____, ____, GPIO, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(8, POR_SEL, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
+ TH1520_PAD(9, I2C_AON_SCL, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(10, I2C_AON_SDA, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(11, CPU_JTG_TCLK, JTAG, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(12, CPU_JTG_TMS, JTAG, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(13, CPU_JTG_TDI, JTAG, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(14, CPU_JTG_TDO, JTAG, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(15, CPU_JTG_TRST, JTAG, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(16, AOGPIO_7, CLK, AUD, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(17, AOGPIO_8, UART, AUD, IR, GPIO, ____, ____, 0),
+ TH1520_PAD(18, AOGPIO_9, UART, AUD, IR, GPIO, ____, ____, 0),
+ TH1520_PAD(19, AOGPIO_10, CLK, AUD, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(20, AOGPIO_11, GPIO, AUD, ____, ____, ____, ____, 0),
+ TH1520_PAD(21, AOGPIO_12, GPIO, AUD, ____, ____, ____, ____, 0),
+ TH1520_PAD(22, AOGPIO_13, GPIO, AUD, ____, ____, ____, ____, 0),
+ TH1520_PAD(23, AOGPIO_14, GPIO, AUD, ____, ____, ____, ____, 0),
+ TH1520_PAD(24, AOGPIO_15, GPIO, AUD, ____, ____, ____, ____, 0),
+ TH1520_PAD(25, AUDIO_PA0, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(26, AUDIO_PA1, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(27, AUDIO_PA2, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(28, AUDIO_PA3, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(29, AUDIO_PA4, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(30, AUDIO_PA5, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(31, AUDIO_PA6, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(32, AUDIO_PA7, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(33, AUDIO_PA8, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(34, AUDIO_PA9, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(35, AUDIO_PA10, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(36, AUDIO_PA11, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(37, AUDIO_PA12, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(38, AUDIO_PA13, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(39, AUDIO_PA14, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(40, AUDIO_PA15, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(41, AUDIO_PA16, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(42, AUDIO_PA17, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(43, AUDIO_PA27, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(44, AUDIO_PA28, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(45, AUDIO_PA29, AUD, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(46, AUDIO_PA30, AUD, RST, ____, GPIO, ____, ____, 0),
+};
+
+static const struct pinctrl_pin_desc th1520_group2_pins[] = {
+ TH1520_PAD(0, QSPI1_SCLK, QSPI, ISO, ____, GPIO, FUSE, ____, 0),
+ TH1520_PAD(1, QSPI1_CSN0, QSPI, ____, I2C, GPIO, FUSE, ____, 0),
+ TH1520_PAD(2, QSPI1_D0_MOSI, QSPI, ISO, I2C, GPIO, FUSE, ____, 0),
+ TH1520_PAD(3, QSPI1_D1_MISO, QSPI, ISO, ____, GPIO, FUSE, ____, 0),
+ TH1520_PAD(4, QSPI1_D2_WP, QSPI, ISO, UART, GPIO, FUSE, ____, 0),
+ TH1520_PAD(5, QSPI1_D3_HOLD, QSPI, ISO, UART, GPIO, ____, ____, 0),
+ TH1520_PAD(6, I2C0_SCL, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(7, I2C0_SDA, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(8, I2C1_SCL, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(9, I2C1_SDA, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(10, UART1_TXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(11, UART1_RXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(12, UART4_TXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(13, UART4_RXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(14, UART4_CTSN, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(15, UART4_RTSN, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(16, UART3_TXD, DBG, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(17, UART3_RXD, DBG, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(18, GPIO0_18, GPIO, I2C, ____, ____, ____, ____, 0),
+ TH1520_PAD(19, GPIO0_19, GPIO, I2C, ____, ____, ____, ____, 0),
+ TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, ____, ____, 0),
+ TH1520_PAD(21, GPIO0_21, GPIO, UART, IR, ____, DPU0, DPU1, 0),
+ TH1520_PAD(22, GPIO0_22, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0),
+ TH1520_PAD(23, GPIO0_23, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0),
+ TH1520_PAD(24, GPIO0_24, GPIO, JTAG, QSPI, ____, DPU0, DPU1, 0),
+ TH1520_PAD(25, GPIO0_25, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(26, GPIO0_26, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(27, GPIO0_27, GPIO, ____, I2C, ____, DPU0, DPU1, 0),
+ TH1520_PAD(28, GPIO0_28, GPIO, ____, I2C, ____, DPU0, DPU1, 0),
+ TH1520_PAD(29, GPIO0_29, GPIO, ____, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(30, GPIO0_30, GPIO, ____, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(31, GPIO0_31, GPIO, ____, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(32, GPIO1_0, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(33, GPIO1_1, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(34, GPIO1_2, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(35, GPIO1_3, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(36, GPIO1_4, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(37, GPIO1_5, GPIO, ____, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(38, GPIO1_6, GPIO, ____, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(39, GPIO1_7, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(40, GPIO1_8, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(41, GPIO1_9, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(42, GPIO1_10, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(43, GPIO1_11, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(44, GPIO1_12, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(45, GPIO1_13, GPIO, UART, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(46, GPIO1_14, GPIO, UART, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(47, GPIO1_15, GPIO, UART, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(48, GPIO1_16, GPIO, UART, ____, ____, DPU0, DPU1, 0),
+ TH1520_PAD(49, CLK_OUT_0, BSEL, CLK, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(50, CLK_OUT_1, BSEL, CLK, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(51, CLK_OUT_2, BSEL, CLK, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(52, CLK_OUT_3, BSEL, CLK, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(53, GPIO1_21, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(54, GPIO1_22, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(55, GPIO1_23, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(56, GPIO1_24, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(57, GPIO1_25, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(58, GPIO1_26, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(59, GPIO1_27, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(60, GPIO1_28, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(61, GPIO1_29, GPIO, ____, ISP, ____, ____, ____, 0),
+ TH1520_PAD(62, GPIO1_30, GPIO, ____, ISP, ____, ____, ____, 0),
+};
+
+static const struct pinctrl_pin_desc th1520_group3_pins[] = {
+ TH1520_PAD(0, UART0_TXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(1, UART0_RXD, UART, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(2, QSPI0_SCLK, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(3, QSPI0_CSN0, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(4, QSPI0_CSN1, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(8, QSPI1_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0),
+ TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(11, I2C3_SCL, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(12, I2C3_SDA, I2C, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(13, GPIO2_13, GPIO, SPI, ____, ____, ____, ____, 0),
+ TH1520_PAD(14, SPI_SCLK, SPI, UART, IR, GPIO, ____, ____, 0),
+ TH1520_PAD(15, SPI_CSN, SPI, UART, IR, GPIO, ____, ____, 0),
+ TH1520_PAD(16, SPI_MOSI, SPI, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(17, SPI_MISO, SPI, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(18, GPIO2_18, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(19, GPIO2_19, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(20, GPIO2_20, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(21, GPIO2_21, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(22, GPIO2_22, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(23, GPIO2_23, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(24, GPIO2_24, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(25, GPIO2_25, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(26, SDIO0_WPRTN, SDIO, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(27, SDIO0_DETN, SDIO, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(28, SDIO1_WPRTN, SDIO, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(29, SDIO1_DETN, SDIO, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(30, GPIO2_30, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(31, GPIO2_31, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(32, GPIO3_0, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(33, GPIO3_1, GPIO, MAC1, ____, ____, ____, ____, 0),
+ TH1520_PAD(34, GPIO3_2, GPIO, PWM, ____, ____, ____, ____, 0),
+ TH1520_PAD(35, GPIO3_3, GPIO, PWM, ____, ____, ____, ____, 0),
+ TH1520_PAD(36, HDMI_SCL, HDMI, PWM, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(37, HDMI_SDA, HDMI, PWM, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(38, HDMI_CEC, HDMI, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(39, GMAC0_TX_CLK, MAC0, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(40, GMAC0_RX_CLK, MAC0, ____, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(41, GMAC0_TXEN, MAC0, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(42, GMAC0_TXD0, MAC0, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(43, GMAC0_TXD1, MAC0, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(44, GMAC0_TXD2, MAC0, UART, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(45, GMAC0_TXD3, MAC0, I2C, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(46, GMAC0_RXDV, MAC0, I2C, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(47, GMAC0_RXD0, MAC0, I2C, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(48, GMAC0_RXD1, MAC0, I2C, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(49, GMAC0_RXD2, MAC0, SPI, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(50, GMAC0_RXD3, MAC0, SPI, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(51, GMAC0_MDC, MAC0, SPI, MAC1, GPIO, ____, ____, 0),
+ TH1520_PAD(52, GMAC0_MDIO, MAC0, SPI, MAC1, GPIO, ____, ____, 0),
+ TH1520_PAD(53, GMAC0_COL, MAC0, PWM, ____, GPIO, ____, ____, 0),
+ TH1520_PAD(54, GMAC0_CRS, MAC0, PWM, ____, GPIO, ____, ____, 0),
+};
+
+static const struct th1520_pad_group th1520_group1 = {
+ .name = "th1520-group1",
+ .pins = th1520_group1_pins,
+ .npins = ARRAY_SIZE(th1520_group1_pins),
+};
+
+static const struct th1520_pad_group th1520_group2 = {
+ .name = "th1520-group2",
+ .pins = th1520_group2_pins,
+ .npins = ARRAY_SIZE(th1520_group2_pins),
+};
+
+static const struct th1520_pad_group th1520_group3 = {
+ .name = "th1520-group3",
+ .pins = th1520_group3_pins,
+ .npins = ARRAY_SIZE(th1520_group3_pins),
+};
+
+static int th1520_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+
+ return thp->desc.npins;
+}
+
+static const char *th1520_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int gsel)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+
+ return thp->desc.pins[gsel].name;
+}
+
+static int th1520_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int gsel,
+ const unsigned int **pins,
+ unsigned int *npins)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = &thp->desc.pins[gsel].number;
+ *npins = 1;
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void th1520_pin_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int pin)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ void __iomem *padcfg = th1520_padcfg(thp, pin);
+ void __iomem *muxcfg = th1520_muxcfg(thp, pin);
+ u32 pad;
+ u32 mux;
+
+ scoped_guard(raw_spinlock_irqsave, &thp->lock) {
+ pad = readl_relaxed(padcfg);
+ mux = readl_relaxed(muxcfg);
+ }
+
+ seq_printf(s, "[PADCFG_%03u:0x%x=0x%07x MUXCFG_%03u:0x%x=0x%08x]",
+ 1 + pin / 2, 0x000 + 4 * (pin / 2), pad,
+ 1 + pin / 8, 0x400 + 4 * (pin / 8), mux);
+}
+#else
+#define th1520_pin_dbg_show NULL
+#endif
+
+static void th1520_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned int nmaps)
+{
+ unsigned long *seen = NULL;
+ unsigned int i;
+
+ for (i = 0; i < nmaps; i++) {
+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN &&
+ map[i].data.configs.configs != seen) {
+ seen = map[i].data.configs.configs;
+ kfree(seen);
+ }
+ }
+
+ kfree(map);
+}
+
+static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **maps,
+ unsigned int *num_maps)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ struct device_node *child;
+ struct pinctrl_map *map;
+ unsigned long *configs;
+ unsigned int nconfigs;
+ unsigned int nmaps;
+ int ret;
+
+ nmaps = 0;
+ for_each_available_child_of_node(np, child) {
+ int npins = of_property_count_strings(child, "pins");
+
+ if (npins <= 0) {
+ of_node_put(child);
+ dev_err(thp->pctl->dev, "no pins selected for %pOFn.%pOFn\n",
+ np, child);
+ return -EINVAL;
+ }
+ nmaps += npins;
+ if (of_property_present(child, "function"))
+ nmaps += npins;
+ }
+
+ map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
+ if (!map)
+ return -ENOMEM;
+
+ nmaps = 0;
+ mutex_lock(&thp->mutex);
+ for_each_available_child_of_node(np, child) {
+ unsigned int rollback = nmaps;
+ enum th1520_muxtype muxtype;
+ struct property *prop;
+ const char *funcname;
+ const char **pgnames;
+ const char *pinname;
+ int npins;
+
+ ret = pinconf_generic_parse_dt_config(child, pctldev, &configs, &nconfigs);
+ if (ret) {
+ dev_err(thp->pctl->dev, "%pOFn.%pOFn: error parsing pin config\n",
+ np, child);
+ goto put_child;
+ }
+
+ if (!of_property_read_string(child, "function", &funcname)) {
+ muxtype = th1520_muxtype_get(funcname);
+ if (!muxtype) {
+ dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown function '%s'\n",
+ np, child, funcname);
+ ret = -EINVAL;
+ goto free_configs;
+ }
+
+ funcname = devm_kasprintf(thp->pctl->dev, GFP_KERNEL, "%pOFn.%pOFn",
+ np, child);
+ if (!funcname) {
+ ret = -ENOMEM;
+ goto free_configs;
+ }
+
+ npins = of_property_count_strings(child, "pins");
+ pgnames = devm_kcalloc(thp->pctl->dev, npins, sizeof(*pgnames), GFP_KERNEL);
+ if (!pgnames) {
+ ret = -ENOMEM;
+ goto free_configs;
+ }
+ } else {
+ funcname = NULL;
+ }
+
+ npins = 0;
+ of_property_for_each_string(child, "pins", prop, pinname) {
+ unsigned int i;
+
+ for (i = 0; i < thp->desc.npins; i++) {
+ if (!strcmp(pinname, thp->desc.pins[i].name))
+ break;
+ }
+ if (i == thp->desc.npins) {
+ nmaps = rollback;
+ dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown pin '%s'\n",
+ np, child, pinname);
+ goto free_configs;
+ }
+
+ if (nconfigs) {
+ map[nmaps].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ map[nmaps].data.configs.group_or_pin = thp->desc.pins[i].name;
+ map[nmaps].data.configs.configs = configs;
+ map[nmaps].data.configs.num_configs = nconfigs;
+ nmaps += 1;
+ }
+ if (funcname) {
+ pgnames[npins++] = thp->desc.pins[i].name;
+ map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
+ map[nmaps].data.mux.function = funcname;
+ map[nmaps].data.mux.group = thp->desc.pins[i].name;
+ nmaps += 1;
+ }
+ }
+
+ if (funcname) {
+ ret = pinmux_generic_add_function(pctldev, funcname, pgnames,
+ npins, (void *)muxtype);
+ if (ret < 0) {
+ dev_err(thp->pctl->dev, "error adding function %s\n", funcname);
+ goto put_child;
+ }
+ }
+ }
+
+ *maps = map;
+ *num_maps = nmaps;
+ mutex_unlock(&thp->mutex);
+ return 0;
+
+free_configs:
+ kfree(configs);
+put_child:
+ of_node_put(child);
+ th1520_pinctrl_dt_free_map(pctldev, map, nmaps);
+ mutex_unlock(&thp->mutex);
+ return ret;
+}
+
+static const struct pinctrl_ops th1520_pinctrl_ops = {
+ .get_groups_count = th1520_pinctrl_get_groups_count,
+ .get_group_name = th1520_pinctrl_get_group_name,
+ .get_group_pins = th1520_pinctrl_get_group_pins,
+ .pin_dbg_show = th1520_pin_dbg_show,
+ .dt_node_to_map = th1520_pinctrl_dt_node_to_map,
+ .dt_free_map = th1520_pinctrl_dt_free_map,
+};
+
+static const u8 th1520_drive_strength_in_ma[16] = {
+ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25,
+};
+
+static u16 th1520_drive_strength_from_ma(u32 arg)
+{
+ u16 ds;
+
+ for (ds = 0; ds < TH1520_PADCFG_DS; ds++) {
+ if (arg <= th1520_drive_strength_in_ma[ds])
+ return ds;
+ }
+ return TH1520_PADCFG_DS;
+}
+
+static int th1520_padcfg_rmw(struct th1520_pinctrl *thp, unsigned int pin,
+ u32 mask, u32 value)
+{
+ void __iomem *padcfg = th1520_padcfg(thp, pin);
+ unsigned int shift = th1520_padcfg_shift(pin);
+ u32 tmp;
+
+ mask <<= shift;
+ value <<= shift;
+
+ scoped_guard(raw_spinlock_irqsave, &thp->lock) {
+ tmp = readl_relaxed(padcfg);
+ tmp = (tmp & ~mask) | value;
+ writel_relaxed(tmp, padcfg);
+ }
+ return 0;
+}
+
+static int th1520_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ const struct pin_desc *desc = pin_desc_get(pctldev, pin);
+ bool enabled;
+ int param;
+ u32 value;
+ u32 arg;
+
+ if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG)
+ return -EOPNOTSUPP;
+
+ value = readl_relaxed(th1520_padcfg(thp, pin));
+ value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0);
+
+ param = pinconf_to_config_param(*config);
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ enabled = !(value & (TH1520_PADCFG_SPU | TH1520_PADCFG_PE));
+ arg = 0;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ enabled = (value & TH1520_PADCFG_BIAS) == TH1520_PADCFG_PE;
+ arg = enabled ? TH1520_PULL_DOWN_OHM : 0;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (value & TH1520_PADCFG_SPU) {
+ enabled = true;
+ arg = TH1520_PULL_STRONG_OHM;
+ } else if ((value & (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) ==
+ (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) {
+ enabled = true;
+ arg = TH1520_PULL_UP_OHM;
+ } else {
+ enabled = false;
+ arg = 0;
+ }
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ enabled = true;
+ arg = th1520_drive_strength_in_ma[value & TH1520_PADCFG_DS];
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ enabled = value & TH1520_PADCFG_IE;
+ arg = enabled ? 1 : 0;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ enabled = value & TH1520_PADCFG_ST;
+ arg = enabled ? 1 : 0;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ enabled = value & TH1520_PADCFG_SL;
+ arg = enabled ? 1 : 0;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+ return enabled ? 0 : -EINVAL;
+}
+
+static int th1520_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned int gsel, unsigned long *config)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int pin = thp->desc.pins[gsel].number;
+
+ return th1520_pinconf_get(pctldev, pin, config);
+}
+
+static int th1520_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ const struct pin_desc *desc = pin_desc_get(pctldev, pin);
+ unsigned int i;
+ u16 mask, value;
+
+ if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG)
+ return -EOPNOTSUPP;
+
+ mask = 0;
+ value = 0;
+ for (i = 0; i < num_configs; i++) {
+ int param = pinconf_to_config_param(configs[i]);
+ u32 arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ mask |= TH1520_PADCFG_BIAS;
+ value &= ~TH1520_PADCFG_BIAS;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (arg == 0)
+ return -EOPNOTSUPP;
+ mask |= TH1520_PADCFG_BIAS;
+ value &= ~TH1520_PADCFG_BIAS;
+ value |= TH1520_PADCFG_PE;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (arg == 0)
+ return -EOPNOTSUPP;
+ mask |= TH1520_PADCFG_BIAS;
+ value &= ~TH1520_PADCFG_BIAS;
+ if (arg == TH1520_PULL_STRONG_OHM)
+ value |= TH1520_PADCFG_SPU;
+ else
+ value |= TH1520_PADCFG_PE | TH1520_PADCFG_PS;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ mask |= TH1520_PADCFG_DS;
+ value &= ~TH1520_PADCFG_DS;
+ value |= th1520_drive_strength_from_ma(arg);
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ mask |= TH1520_PADCFG_IE;
+ if (arg)
+ value |= TH1520_PADCFG_IE;
+ else
+ value &= ~TH1520_PADCFG_IE;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ mask |= TH1520_PADCFG_ST;
+ if (arg)
+ value |= TH1520_PADCFG_ST;
+ else
+ value &= ~TH1520_PADCFG_ST;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ mask |= TH1520_PADCFG_SL;
+ if (arg)
+ value |= TH1520_PADCFG_SL;
+ else
+ value &= ~TH1520_PADCFG_SL;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+ }
+
+ return th1520_padcfg_rmw(thp, pin, mask, value);
+}
+
+static int th1520_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned int gsel,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int pin = thp->desc.pins[gsel].number;
+
+ return th1520_pinconf_set(pctldev, pin, configs, num_configs);
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void th1520_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int pin)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ u32 value = readl_relaxed(th1520_padcfg(thp, pin));
+
+ value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0);
+
+ seq_printf(s, " [0x%03x]", value);
+}
+#else
+#define th1520_pinconf_dbg_show NULL
+#endif
+
+static const struct pinconf_ops th1520_pinconf_ops = {
+ .pin_config_get = th1520_pinconf_get,
+ .pin_config_group_get = th1520_pinconf_group_get,
+ .pin_config_set = th1520_pinconf_set,
+ .pin_config_group_set = th1520_pinconf_group_set,
+ .pin_config_dbg_show = th1520_pinconf_dbg_show,
+ .is_generic = true,
+};
+
+static int th1520_pinmux_set(struct th1520_pinctrl *thp, unsigned int pin,
+ unsigned long muxdata, enum th1520_muxtype muxtype)
+{
+ void __iomem *muxcfg = th1520_muxcfg(thp, pin);
+ unsigned int shift = th1520_muxcfg_shift(pin);
+ u32 mask, value, tmp;
+
+ for (value = 0; muxdata; muxdata >>= 5, value++) {
+ if ((muxdata & GENMASK(4, 0)) == muxtype)
+ break;
+ }
+ if (!muxdata) {
+ dev_err(thp->pctl->dev, "invalid mux %s for pin %s\n",
+ th1520_muxtype_string[muxtype], pin_get_name(thp->pctl, pin));
+ return -EINVAL;
+ }
+
+ mask = GENMASK(3, 0) << shift;
+ value = value << shift;
+
+ scoped_guard(raw_spinlock_irqsave, &thp->lock) {
+ tmp = readl_relaxed(muxcfg);
+ tmp = (tmp & ~mask) | value;
+ writel_relaxed(tmp, muxcfg);
+ }
+ return 0;
+}
+
+static int th1520_pinmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int fsel, unsigned int gsel)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ const struct function_desc *func = pinmux_generic_get_function(pctldev, fsel);
+
+ return th1520_pinmux_set(thp, thp->desc.pins[gsel].number,
+ (uintptr_t)thp->desc.pins[gsel].drv_data & TH1520_PAD_MUXDATA,
+ (uintptr_t)func->data);
+}
+
+static int th1520_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+ const struct pin_desc *desc = pin_desc_get(pctldev, offset);
+
+ return th1520_pinmux_set(thp, offset,
+ (uintptr_t)desc->drv_data & TH1520_PAD_MUXDATA,
+ TH1520_MUX_GPIO);
+}
+
+static int th1520_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset, bool input)
+{
+ struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
+
+ return th1520_padcfg_rmw(thp, offset, TH1520_PADCFG_IE,
+ input ? TH1520_PADCFG_IE : 0);
+}
+
+static const struct pinmux_ops th1520_pinmux_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = th1520_pinmux_set_mux,
+ .gpio_request_enable = th1520_gpio_request_enable,
+ .gpio_set_direction = th1520_gpio_set_direction,
+ .strict = true,
+};
+
+static int th1520_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct th1520_pad_group *group;
+ struct device_node *np = dev->of_node;
+ struct th1520_pinctrl *thp;
+ struct clk *clk;
+ u32 pin_group;
+ int ret;
+
+ thp = devm_kzalloc(dev, sizeof(*thp), GFP_KERNEL);
+ if (!thp)
+ return -ENOMEM;
+
+ thp->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(thp->base))
+ return PTR_ERR(thp->base);
+
+ clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "error getting clock\n");
+
+ ret = of_property_read_u32(np, "thead,pad-group", &pin_group);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to read the thead,pad-group property\n");
+
+ if (pin_group == 1)
+ group = &th1520_group1;
+ else if (pin_group == 2)
+ group = &th1520_group2;
+ else if (pin_group == 3)
+ group = &th1520_group3;
+ else
+ return dev_err_probe(dev, -EINVAL, "unit address did not match any pad group\n");
+
+ thp->desc.name = group->name;
+ thp->desc.pins = group->pins;
+ thp->desc.npins = group->npins;
+ thp->desc.pctlops = &th1520_pinctrl_ops;
+ thp->desc.pmxops = &th1520_pinmux_ops;
+ thp->desc.confops = &th1520_pinconf_ops;
+ thp->desc.owner = THIS_MODULE;
+ mutex_init(&thp->mutex);
+ raw_spin_lock_init(&thp->lock);
+
+ ret = devm_pinctrl_register_and_init(dev, &thp->desc, thp, &thp->pctl);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
+
+ return pinctrl_enable(thp->pctl);
+}
+
+static const struct of_device_id th1520_pinctrl_of_match[] = {
+ { .compatible = "thead,th1520-pinctrl"},
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, th1520_pinctrl_of_match);
+
+static struct platform_driver th1520_pinctrl_driver = {
+ .probe = th1520_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-th1520",
+ .of_match_table = th1520_pinctrl_of_match,
+ },
+};
+module_platform_driver(th1520_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for the T-Head TH1520 SoC");
+MODULE_AUTHOR("Emil Renner Berthing <emil.renner.berthing@canonical.com>");
+MODULE_LICENSE("GPL");
--
2.34.1
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^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 3/8] riscv: dts: thead: Add TH1520 pin control nodes
2024-09-30 19:50 ` Drew Fustini
@ 2024-09-30 19:50 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++
arch/riscv/boot/dts/thead/th1520.dtsi | 27 ++++++++++++++++++++++
3 files changed, 35 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 497d961456f3..e88b4fce755e 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -45,6 +45,10 @@ &osc_32k {
clock-frequency = <32768>;
};
+&aonsys_clk {
+ clock-frequency = <73728000>;
+};
+
&dmac0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 78977bdbbe3d..bf1c639072b8 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -25,6 +25,10 @@ &osc_32k {
clock-frequency = <32768>;
};
+&aonsys_clk {
+ clock-frequency = <73728000>;
+};
+
&dmac0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 6992060e6a54..e4eda2a76595 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -216,6 +216,12 @@ osc_32k: 32k-oscillator {
#clock-cells = <0>;
};
+ aonsys_clk: aonsys-clk {
+ compatible = "fixed-clock";
+ clock-output-names = "aonsys_clk";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -354,6 +360,13 @@ portd: gpio-controller@0 {
};
};
+ padctrl1_apsys: pinctrl@ffe7f3c000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xe7f3c000 0x0 0x1000>;
+ clocks = <&clk CLK_PADCTRL1>;
+ thead,pad-group = <2>;
+ };
+
gpio0: gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
@@ -392,6 +405,13 @@ portb: gpio-controller@0 {
};
};
+ padctrl0_apsys: pinctrl@ffec007000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xec007000 0x0 0x1000>;
+ clocks = <&clk CLK_PADCTRL0>;
+ thead,pad-group = <3>;
+ };
+
uart2: serial@ffec010000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xec010000 0x0 0x4000>;
@@ -538,6 +558,13 @@ porte: gpio-controller@0 {
};
};
+ padctrl_aosys: pinctrl@fffff4a000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xfff4a000 0x0 0x2000>;
+ thead,pad-group = <1>;
+ clocks = <&aonsys_clk>;
+ };
+
ao_gpio1: gpio@fffff52000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff52000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 3/8] riscv: dts: thead: Add TH1520 pin control nodes
@ 2024-09-30 19:50 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++
arch/riscv/boot/dts/thead/th1520.dtsi | 27 ++++++++++++++++++++++
3 files changed, 35 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 497d961456f3..e88b4fce755e 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -45,6 +45,10 @@ &osc_32k {
clock-frequency = <32768>;
};
+&aonsys_clk {
+ clock-frequency = <73728000>;
+};
+
&dmac0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 78977bdbbe3d..bf1c639072b8 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -25,6 +25,10 @@ &osc_32k {
clock-frequency = <32768>;
};
+&aonsys_clk {
+ clock-frequency = <73728000>;
+};
+
&dmac0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 6992060e6a54..e4eda2a76595 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -216,6 +216,12 @@ osc_32k: 32k-oscillator {
#clock-cells = <0>;
};
+ aonsys_clk: aonsys-clk {
+ compatible = "fixed-clock";
+ clock-output-names = "aonsys_clk";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -354,6 +360,13 @@ portd: gpio-controller@0 {
};
};
+ padctrl1_apsys: pinctrl@ffe7f3c000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xe7f3c000 0x0 0x1000>;
+ clocks = <&clk CLK_PADCTRL1>;
+ thead,pad-group = <2>;
+ };
+
gpio0: gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
@@ -392,6 +405,13 @@ portb: gpio-controller@0 {
};
};
+ padctrl0_apsys: pinctrl@ffec007000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xec007000 0x0 0x1000>;
+ clocks = <&clk CLK_PADCTRL0>;
+ thead,pad-group = <3>;
+ };
+
uart2: serial@ffec010000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xec010000 0x0 0x4000>;
@@ -538,6 +558,13 @@ porte: gpio-controller@0 {
};
};
+ padctrl_aosys: pinctrl@fffff4a000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xfff4a000 0x0 0x2000>;
+ thead,pad-group = <1>;
+ clocks = <&aonsys_clk>;
+ };
+
ao_gpio1: gpio@fffff52000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff52000 0x0 0x1000>;
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 4/8] riscv: dts: thead: Add TH1520 GPIO ranges
2024-09-30 19:50 ` Drew Fustini
@ 2024-09-30 19:50 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add gpio-ranges properties to the TH1520 device tree, so user space can
change basic pinconf settings for GPIOs and are not allowed to use pads
already used by other functions.
Adjust number of GPIOs available for the different controllers.
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index e4eda2a76595..7dcc250ee1d1 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -334,6 +334,7 @@ portc: gpio-controller@0 {
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
+ gpio-ranges = <&padctrl0_apsys 0 0 32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -352,7 +353,8 @@ portd: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- ngpios = <32>;
+ ngpios = <23>;
+ gpio-ranges = <&padctrl0_apsys 0 32 23>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -379,6 +381,7 @@ porta: gpio-controller@0 {
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
+ gpio-ranges = <&padctrl1_apsys 0 0 32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -397,7 +400,8 @@ portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- ngpios = <32>;
+ ngpios = <31>;
+ gpio-ranges = <&padctrl1_apsys 0 32 31>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -550,7 +554,8 @@ porte: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- ngpios = <32>;
+ ngpios = <16>;
+ gpio-ranges = <&padctrl_aosys 0 9 16>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -575,7 +580,8 @@ portf: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- ngpios = <32>;
+ ngpios = <23>;
+ gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 4/8] riscv: dts: thead: Add TH1520 GPIO ranges
@ 2024-09-30 19:50 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add gpio-ranges properties to the TH1520 device tree, so user space can
change basic pinconf settings for GPIOs and are not allowed to use pads
already used by other functions.
Adjust number of GPIOs available for the different controllers.
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index e4eda2a76595..7dcc250ee1d1 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -334,6 +334,7 @@ portc: gpio-controller@0 {
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
+ gpio-ranges = <&padctrl0_apsys 0 0 32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -352,7 +353,8 @@ portd: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- ngpios = <32>;
+ ngpios = <23>;
+ gpio-ranges = <&padctrl0_apsys 0 32 23>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -379,6 +381,7 @@ porta: gpio-controller@0 {
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
+ gpio-ranges = <&padctrl1_apsys 0 0 32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -397,7 +400,8 @@ portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- ngpios = <32>;
+ ngpios = <31>;
+ gpio-ranges = <&padctrl1_apsys 0 32 31>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -550,7 +554,8 @@ porte: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- ngpios = <32>;
+ ngpios = <16>;
+ gpio-ranges = <&padctrl_aosys 0 9 16>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -575,7 +580,8 @@ portf: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- ngpios = <32>;
+ ngpios = <23>;
+ gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 5/8] riscv: dts: thead: Adjust TH1520 GPIO labels
2024-09-30 19:50 ` Drew Fustini
@ 2024-09-30 19:50 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Adjust labels for the TH1520 GPIO controllers such that GPIOs can be
referenced by the names used by the documentation. Eg.
GPIO0_X -> <&gpio0 X Y>
GPIO1_X -> <&gpio1 X Y>
GPIO2_X -> <&gpio2 X Y>
GPIO3_X -> <&gpio3 X Y>
GPIO4_X -> <&gpio4 X Y>
AOGPIO_X -> <&aogpio X Y>
Remove labels for the parent GPIO devices that shouldn't need to be
referenced.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 2 ++
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 2 ++
arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++-----------
3 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index e88b4fce755e..69f82e7afd0b 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -17,6 +17,8 @@ aliases {
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &aogpio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
index 7738d2895c5a..58ad381fc1c3 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
@@ -14,6 +14,8 @@ aliases {
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &aogpio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 7dcc250ee1d1..b958f249930e 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -322,14 +322,14 @@ uart3: serial@ffe7f04000 {
status = "disabled";
};
- gpio2: gpio@ffe7f34000 {
+ gpio@ffe7f34000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f34000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO2>;
- portc: gpio-controller@0 {
+ gpio2: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -342,14 +342,14 @@ portc: gpio-controller@0 {
};
};
- gpio3: gpio@ffe7f38000 {
+ gpio@ffe7f38000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f38000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO3>;
- portd: gpio-controller@0 {
+ gpio3: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -369,14 +369,14 @@ padctrl1_apsys: pinctrl@ffe7f3c000 {
thead,pad-group = <2>;
};
- gpio0: gpio@ffec005000 {
+ gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO0>;
- porta: gpio-controller@0 {
+ gpio0: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -389,14 +389,14 @@ porta: gpio-controller@0 {
};
};
- gpio1: gpio@ffec006000 {
+ gpio@ffec006000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec006000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO1>;
- portb: gpio-controller@0 {
+ gpio1: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -544,13 +544,13 @@ timer7: timer@ffffc3303c {
status = "disabled";
};
- ao_gpio0: gpio@fffff41000 {
+ gpio@fffff41000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff41000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- porte: gpio-controller@0 {
+ aogpio: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -570,13 +570,13 @@ padctrl_aosys: pinctrl@fffff4a000 {
clocks = <&aonsys_clk>;
};
- ao_gpio1: gpio@fffff52000 {
+ gpio@fffff52000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff52000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- portf: gpio-controller@0 {
+ gpio4: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 5/8] riscv: dts: thead: Adjust TH1520 GPIO labels
@ 2024-09-30 19:50 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Adjust labels for the TH1520 GPIO controllers such that GPIOs can be
referenced by the names used by the documentation. Eg.
GPIO0_X -> <&gpio0 X Y>
GPIO1_X -> <&gpio1 X Y>
GPIO2_X -> <&gpio2 X Y>
GPIO3_X -> <&gpio3 X Y>
GPIO4_X -> <&gpio4 X Y>
AOGPIO_X -> <&aogpio X Y>
Remove labels for the parent GPIO devices that shouldn't need to be
referenced.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 2 ++
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 2 ++
arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++-----------
3 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index e88b4fce755e..69f82e7afd0b 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -17,6 +17,8 @@ aliases {
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &aogpio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
index 7738d2895c5a..58ad381fc1c3 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
@@ -14,6 +14,8 @@ aliases {
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &aogpio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 7dcc250ee1d1..b958f249930e 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -322,14 +322,14 @@ uart3: serial@ffe7f04000 {
status = "disabled";
};
- gpio2: gpio@ffe7f34000 {
+ gpio@ffe7f34000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f34000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO2>;
- portc: gpio-controller@0 {
+ gpio2: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -342,14 +342,14 @@ portc: gpio-controller@0 {
};
};
- gpio3: gpio@ffe7f38000 {
+ gpio@ffe7f38000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f38000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO3>;
- portd: gpio-controller@0 {
+ gpio3: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -369,14 +369,14 @@ padctrl1_apsys: pinctrl@ffe7f3c000 {
thead,pad-group = <2>;
};
- gpio0: gpio@ffec005000 {
+ gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO0>;
- porta: gpio-controller@0 {
+ gpio0: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -389,14 +389,14 @@ porta: gpio-controller@0 {
};
};
- gpio1: gpio@ffec006000 {
+ gpio@ffec006000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec006000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GPIO1>;
- portb: gpio-controller@0 {
+ gpio1: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -544,13 +544,13 @@ timer7: timer@ffffc3303c {
status = "disabled";
};
- ao_gpio0: gpio@fffff41000 {
+ gpio@fffff41000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff41000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- porte: gpio-controller@0 {
+ aogpio: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -570,13 +570,13 @@ padctrl_aosys: pinctrl@fffff4a000 {
clocks = <&aonsys_clk>;
};
- ao_gpio1: gpio@fffff52000 {
+ gpio@fffff52000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff52000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- portf: gpio-controller@0 {
+ gpio4: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names
2024-09-30 19:50 ` Drew Fustini
@ 2024-09-30 19:50 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add names for the GPIO00-GPIO14 lines of the SO-DIMM module.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index bf1c639072b8..ca84bc2039ef 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -29,6 +29,12 @@ &aonsys_clk {
clock-frequency = <73728000>;
};
+&aogpio {
+ gpio-line-names = "", "", "",
+ "GPIO00",
+ "GPIO04";
+};
+
&dmac0 {
status = "okay";
};
@@ -48,3 +54,36 @@ &sdio0 {
max-frequency = <198000000>;
status = "okay";
};
+
+&gpio0 {
+ gpio-line-names = "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "",
+ "GPIO07",
+ "GPIO08",
+ "",
+ "GPIO01",
+ "GPIO02";
+};
+
+&gpio1 {
+ gpio-line-names = "", "", "",
+ "GPIO11",
+ "GPIO12",
+ "GPIO13",
+ "GPIO14",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "",
+ "GPIO06";
+};
+
+&gpio2 {
+ gpio-line-names = "GPIO03",
+ "GPIO05";
+};
+
+&gpio3 {
+ gpio-line-names = "", "",
+ "GPIO09",
+ "GPIO10";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names
@ 2024-09-30 19:50 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add names for the GPIO00-GPIO14 lines of the SO-DIMM module.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index bf1c639072b8..ca84bc2039ef 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -29,6 +29,12 @@ &aonsys_clk {
clock-frequency = <73728000>;
};
+&aogpio {
+ gpio-line-names = "", "", "",
+ "GPIO00",
+ "GPIO04";
+};
+
&dmac0 {
status = "okay";
};
@@ -48,3 +54,36 @@ &sdio0 {
max-frequency = <198000000>;
status = "okay";
};
+
+&gpio0 {
+ gpio-line-names = "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "",
+ "GPIO07",
+ "GPIO08",
+ "",
+ "GPIO01",
+ "GPIO02";
+};
+
+&gpio1 {
+ gpio-line-names = "", "", "",
+ "GPIO11",
+ "GPIO12",
+ "GPIO13",
+ "GPIO14",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "",
+ "GPIO06";
+};
+
+&gpio2 {
+ gpio-line-names = "GPIO03",
+ "GPIO05";
+};
+
+&gpio3 {
+ gpio-line-names = "", "",
+ "GPIO09",
+ "GPIO10";
+};
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0
2024-09-30 19:50 ` Drew Fustini
@ 2024-09-30 19:50 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add pinctrl settings for UART0 used as the default debug console on
both the Lichee Pi 4A and BeagleV Ahead boards.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 26 ++++++++++++++++++++++
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 26 ++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 69f82e7afd0b..6c0b768e8d17 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -71,7 +71,33 @@ &sdio0 {
status = "okay";
};
+&padctrl0_apsys {
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pins = "UART0_TXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <3>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pins = "UART0_RXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <1>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+};
+
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
index 58ad381fc1c3..f60b1879192d 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
@@ -30,7 +30,33 @@ chosen {
};
};
+&padctrl0_apsys {
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pins = "UART0_TXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <3>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pins = "UART0_RXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <1>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+};
+
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
status = "okay";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0
@ 2024-09-30 19:50 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add pinctrl settings for UART0 used as the default debug console on
both the Lichee Pi 4A and BeagleV Ahead boards.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 26 ++++++++++++++++++++++
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 26 ++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 69f82e7afd0b..6c0b768e8d17 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -71,7 +71,33 @@ &sdio0 {
status = "okay";
};
+&padctrl0_apsys {
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pins = "UART0_TXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <3>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pins = "UART0_RXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <1>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+};
+
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
index 58ad381fc1c3..f60b1879192d 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
@@ -30,7 +30,33 @@ chosen {
};
};
+&padctrl0_apsys {
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pins = "UART0_TXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <3>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pins = "UART0_RXD";
+ function = "uart";
+ bias-disable;
+ drive-strength = <1>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+};
+
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
status = "okay";
};
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs
2024-09-30 19:50 ` Drew Fustini
@ 2024-09-30 19:50 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add nodes for the 5 user controllable LEDs on the BeagleV Ahead board.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 55 ++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 6c0b768e8d17..5a5888f4eda6 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -7,6 +7,8 @@
/dts-v1/;
#include "th1520.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "BeagleV Ahead";
@@ -35,7 +37,42 @@ chosen {
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x1 0x00000000>;
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+ compatible = "gpio-leds";
+
+ led-1 {
+ gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "led1";
+ };
+
+ led-2 {
+ gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "led2";
+ };
+
+ led-3 {
+ gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "led3";
+ };
+
+ led-4 {
+ gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "led4";
+ };
+ led-5 {
+ gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "led5";
+ };
};
};
@@ -71,6 +108,24 @@ &sdio0 {
status = "okay";
};
+&padctrl_aosys {
+ led_pins: led-0 {
+ led-pins {
+ pins = "AUDIO_PA8", /* GPIO4_8 */
+ "AUDIO_PA9", /* GPIO4_9 */
+ "AUDIO_PA10", /* GPIO4_10 */
+ "AUDIO_PA11", /* GPIO4_11 */
+ "AUDIO_PA12"; /* GPIO4_12 */
+ function = "gpio";
+ bias-disable;
+ drive-strength = <3>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+};
+
&padctrl0_apsys {
uart0_pins: uart0-0 {
tx-pins {
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v3 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs
@ 2024-09-30 19:50 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-09-30 19:50 UTC (permalink / raw)
To: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel, Drew Fustini
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add nodes for the 5 user controllable LEDs on the BeagleV Ahead board.
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 55 ++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 6c0b768e8d17..5a5888f4eda6 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -7,6 +7,8 @@
/dts-v1/;
#include "th1520.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "BeagleV Ahead";
@@ -35,7 +37,42 @@ chosen {
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x1 0x00000000>;
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+ compatible = "gpio-leds";
+
+ led-1 {
+ gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "led1";
+ };
+
+ led-2 {
+ gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "led2";
+ };
+
+ led-3 {
+ gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "led3";
+ };
+
+ led-4 {
+ gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "led4";
+ };
+ led-5 {
+ gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "led5";
+ };
};
};
@@ -71,6 +108,24 @@ &sdio0 {
status = "okay";
};
+&padctrl_aosys {
+ led_pins: led-0 {
+ led-pins {
+ pins = "AUDIO_PA8", /* GPIO4_8 */
+ "AUDIO_PA9", /* GPIO4_9 */
+ "AUDIO_PA10", /* GPIO4_10 */
+ "AUDIO_PA11", /* GPIO4_11 */
+ "AUDIO_PA12"; /* GPIO4_12 */
+ function = "gpio";
+ bias-disable;
+ drive-strength = <3>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+};
+
&padctrl0_apsys {
uart0_pins: uart0-0 {
tx-pins {
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
2024-09-30 19:50 ` Drew Fustini
@ 2024-10-01 12:13 ` Linus Walleij
-1 siblings, 0 replies; 41+ messages in thread
From: Linus Walleij @ 2024-10-01 12:13 UTC (permalink / raw)
To: Drew Fustini
Cc: Drew Fustini, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Emil Renner Berthing, Thomas Bonnefille, linux-riscv, linux-gpio,
devicetree, linux-kernel
On Mon, Sep 30, 2024 at 9:51 PM Drew Fustini <dfustini@tenstorrent.com> wrote:
> This adds a pin control driver created by Emil for the T-Head TH1520
> RISC-V SoC used on the Lichee Pi 4A and BeagleV Ahead boards and updates
> the device trees to make use of it.
Thanks Drew, v3 looks good. I've merged it to an immutable branch:
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-thead-th1520
Then I merged that into my "devel" branch for v6.13.
You can merge the DTS/DTSI files through the SoC tree, FWIW:
Acked-by: Linus Walleij <linus.walleij@linaro.org>
I think I'll make a stab at using guarded mutexes etc and see what
you think about it!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
@ 2024-10-01 12:13 ` Linus Walleij
0 siblings, 0 replies; 41+ messages in thread
From: Linus Walleij @ 2024-10-01 12:13 UTC (permalink / raw)
To: Drew Fustini
Cc: Drew Fustini, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Emil Renner Berthing, Thomas Bonnefille, linux-riscv, linux-gpio,
devicetree, linux-kernel
On Mon, Sep 30, 2024 at 9:51 PM Drew Fustini <dfustini@tenstorrent.com> wrote:
> This adds a pin control driver created by Emil for the T-Head TH1520
> RISC-V SoC used on the Lichee Pi 4A and BeagleV Ahead boards and updates
> the device trees to make use of it.
Thanks Drew, v3 looks good. I've merged it to an immutable branch:
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-thead-th1520
Then I merged that into my "devel" branch for v6.13.
You can merge the DTS/DTSI files through the SoC tree, FWIW:
Acked-by: Linus Walleij <linus.walleij@linaro.org>
I think I'll make a stab at using guarded mutexes etc and see what
you think about it!
Yours,
Linus Walleij
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
2024-09-30 19:50 ` Drew Fustini
(?)
@ 2024-10-02 15:54 ` Dan Carpenter
2024-10-05 19:30 ` Drew Fustini
-1 siblings, 1 reply; 41+ messages in thread
From: Dan Carpenter @ 2024-10-02 15:54 UTC (permalink / raw)
To: oe-kbuild, Drew Fustini; +Cc: lkp, oe-kbuild-all
Hi Drew,
kernel test robot noticed the following build warnings:
url: https://github.com/intel-lab-lkp/linux/commits/Drew-Fustini/dt-bindings-pinctrl-Add-thead-th1520-pinctrl-bindings/20241001-035421
base: 9852d85ec9d492ebef56dc5f229416c925758edc
patch link: https://lore.kernel.org/r/20240930-th1520-pinctrl-v3-2-32cea2bdbecb%40tenstorrent.com
patch subject: [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
config: s390-randconfig-r072-20241002 (https://download.01.org/0day-ci/archive/20241002/202410022336.xyWlV0Tf-lkp@intel.com/config)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202410022336.xyWlV0Tf-lkp@intel.com/
smatch warnings:
drivers/pinctrl/pinctrl-th1520.c:502 th1520_pinctrl_dt_node_to_map() warn: missing error code 'ret'
vim +/ret +502 drivers/pinctrl/pinctrl-th1520.c
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 414 static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 415 struct device_node *np,
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 416 struct pinctrl_map **maps,
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 417 unsigned int *num_maps)
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 418 {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 419 struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 420 struct device_node *child;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 421 struct pinctrl_map *map;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 422 unsigned long *configs;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 423 unsigned int nconfigs;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 424 unsigned int nmaps;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 425 int ret;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 426
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 427 nmaps = 0;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 428 for_each_available_child_of_node(np, child) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 429 int npins = of_property_count_strings(child, "pins");
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 430
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 431 if (npins <= 0) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 432 of_node_put(child);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 433 dev_err(thp->pctl->dev, "no pins selected for %pOFn.%pOFn\n",
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 434 np, child);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 435 return -EINVAL;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 436 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 437 nmaps += npins;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 438 if (of_property_present(child, "function"))
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 439 nmaps += npins;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 440 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 441
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 442 map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 443 if (!map)
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 444 return -ENOMEM;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 445
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 446 nmaps = 0;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 447 mutex_lock(&thp->mutex);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 448 for_each_available_child_of_node(np, child) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 449 unsigned int rollback = nmaps;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 450 enum th1520_muxtype muxtype;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 451 struct property *prop;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 452 const char *funcname;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 453 const char **pgnames;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 454 const char *pinname;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 455 int npins;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 456
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 457 ret = pinconf_generic_parse_dt_config(child, pctldev, &configs, &nconfigs);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 458 if (ret) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 459 dev_err(thp->pctl->dev, "%pOFn.%pOFn: error parsing pin config\n",
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 460 np, child);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 461 goto put_child;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 462 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 463
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 464 if (!of_property_read_string(child, "function", &funcname)) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 465 muxtype = th1520_muxtype_get(funcname);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 466 if (!muxtype) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 467 dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown function '%s'\n",
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 468 np, child, funcname);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 469 ret = -EINVAL;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 470 goto free_configs;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 471 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 472
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 473 funcname = devm_kasprintf(thp->pctl->dev, GFP_KERNEL, "%pOFn.%pOFn",
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 474 np, child);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 475 if (!funcname) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 476 ret = -ENOMEM;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 477 goto free_configs;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 478 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 479
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 480 npins = of_property_count_strings(child, "pins");
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 481 pgnames = devm_kcalloc(thp->pctl->dev, npins, sizeof(*pgnames), GFP_KERNEL);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 482 if (!pgnames) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 483 ret = -ENOMEM;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 484 goto free_configs;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 485 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 486 } else {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 487 funcname = NULL;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 488 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 489
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 490 npins = 0;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 491 of_property_for_each_string(child, "pins", prop, pinname) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 492 unsigned int i;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 493
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 494 for (i = 0; i < thp->desc.npins; i++) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 495 if (!strcmp(pinname, thp->desc.pins[i].name))
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 496 break;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 497 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 498 if (i == thp->desc.npins) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 499 nmaps = rollback;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 500 dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown pin '%s'\n",
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 501 np, child, pinname);
ret = -EINVAL?
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 @502 goto free_configs;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 503 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 504
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 505 if (nconfigs) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 506 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_PIN;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 507 map[nmaps].data.configs.group_or_pin = thp->desc.pins[i].name;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 508 map[nmaps].data.configs.configs = configs;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 509 map[nmaps].data.configs.num_configs = nconfigs;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 510 nmaps += 1;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 511 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 512 if (funcname) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 513 pgnames[npins++] = thp->desc.pins[i].name;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 514 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 515 map[nmaps].data.mux.function = funcname;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 516 map[nmaps].data.mux.group = thp->desc.pins[i].name;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 517 nmaps += 1;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 518 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 519 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 520
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 521 if (funcname) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 522 ret = pinmux_generic_add_function(pctldev, funcname, pgnames,
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 523 npins, (void *)muxtype);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 524 if (ret < 0) {
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 525 dev_err(thp->pctl->dev, "error adding function %s\n", funcname);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 526 goto put_child;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 527 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 528 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 529 }
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 530
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 531 *maps = map;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 532 *num_maps = nmaps;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 533 mutex_unlock(&thp->mutex);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 534 return 0;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 535
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 536 free_configs:
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 537 kfree(configs);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 538 put_child:
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 539 of_node_put(child);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 540 th1520_pinctrl_dt_free_map(pctldev, map, nmaps);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 541 mutex_unlock(&thp->mutex);
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 542 return ret;
e7e62c9ab90ce8 Emil Renner Berthing 2024-09-30 543 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
2024-10-01 12:13 ` Linus Walleij
@ 2024-10-02 18:34 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-10-02 18:34 UTC (permalink / raw)
To: Linus Walleij
Cc: Drew Fustini, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Emil Renner Berthing, Thomas Bonnefille, linux-riscv, linux-gpio,
devicetree, linux-kernel
On Tue, Oct 01, 2024 at 02:13:20PM +0200, Linus Walleij wrote:
> On Mon, Sep 30, 2024 at 9:51 PM Drew Fustini <dfustini@tenstorrent.com> wrote:
>
> > This adds a pin control driver created by Emil for the T-Head TH1520
> > RISC-V SoC used on the Lichee Pi 4A and BeagleV Ahead boards and updates
> > the device trees to make use of it.
>
> Thanks Drew, v3 looks good. I've merged it to an immutable branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-thead-th1520
>
> Then I merged that into my "devel" branch for v6.13.
Thanks for taking this. Will that also end up in linux-next eventually?
I'm working on a TH1520 Ethernet driver which depends on the pinctrl
driver. Andrew Lunn replied to me that all the dependencies need to be
in linux-next [1].
> You can merge the DTS/DTSI files through the SoC tree, FWIW:
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Thanks, I'll take the dts through my thead tree [2].
> I think I'll make a stab at using guarded mutexes etc and see what
> you think about it!
Do you mean using scoped_guard() for thp->mutex in
th1520_pinctrl_dt_node_to_map()?
thanks,
drew
[1] https://lore.kernel.org/linux-riscv/99af411c-ff40-4396-a6e2-5aac179ba1be@lunn.ch/T/#t
[2] https://github.com/pdp7/linux/tree/thead-dt-for-next
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
@ 2024-10-02 18:34 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-10-02 18:34 UTC (permalink / raw)
To: Linus Walleij
Cc: Drew Fustini, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Emil Renner Berthing, Thomas Bonnefille, linux-riscv, linux-gpio,
devicetree, linux-kernel
On Tue, Oct 01, 2024 at 02:13:20PM +0200, Linus Walleij wrote:
> On Mon, Sep 30, 2024 at 9:51 PM Drew Fustini <dfustini@tenstorrent.com> wrote:
>
> > This adds a pin control driver created by Emil for the T-Head TH1520
> > RISC-V SoC used on the Lichee Pi 4A and BeagleV Ahead boards and updates
> > the device trees to make use of it.
>
> Thanks Drew, v3 looks good. I've merged it to an immutable branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-thead-th1520
>
> Then I merged that into my "devel" branch for v6.13.
Thanks for taking this. Will that also end up in linux-next eventually?
I'm working on a TH1520 Ethernet driver which depends on the pinctrl
driver. Andrew Lunn replied to me that all the dependencies need to be
in linux-next [1].
> You can merge the DTS/DTSI files through the SoC tree, FWIW:
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Thanks, I'll take the dts through my thead tree [2].
> I think I'll make a stab at using guarded mutexes etc and see what
> you think about it!
Do you mean using scoped_guard() for thp->mutex in
th1520_pinctrl_dt_node_to_map()?
thanks,
drew
[1] https://lore.kernel.org/linux-riscv/99af411c-ff40-4396-a6e2-5aac179ba1be@lunn.ch/T/#t
[2] https://github.com/pdp7/linux/tree/thead-dt-for-next
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
2024-09-30 19:50 ` Drew Fustini
@ 2024-10-02 19:36 ` Kees Bakker
-1 siblings, 0 replies; 41+ messages in thread
From: Kees Bakker @ 2024-10-02 19:36 UTC (permalink / raw)
To: Drew Fustini, Drew Fustini, Guo Ren, Fu Wei, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing,
Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel
Op 30-09-2024 om 21:50 schreef Drew Fustini:
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add pinctrl driver for the T-Head TH1520 RISC-V SoC.
>
> Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> [dfustini: use thead,pad-group to identify the pin controller instance]
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
> MAINTAINERS | 1 +
> drivers/pinctrl/Kconfig | 13 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/pinctrl-th1520.c | 907 +++++++++++++++++++++++++++++++++++++++
> 4 files changed, 922 insertions(+)
>
> [...]
> +static int th1520_pinmux_set_mux(struct pinctrl_dev *pctldev,
> + unsigned int fsel, unsigned int gsel)
> +{
> + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
> + const struct function_desc *func = pinmux_generic_get_function(pctldev, fsel);
func can be NULL after calling pinmux_generic_get_function
Please add something to avoid NULL pointer dereferencing in the next
statement.
All other callers of pinmux_generic_get_function have something like this:
if (!func)
return -EINVAL;
> +
> + return th1520_pinmux_set(thp, thp->desc.pins[gsel].number,
> + (uintptr_t)thp->desc.pins[gsel].drv_data & TH1520_PAD_MUXDATA,
> + (uintptr_t)func->data);
> +}
> +
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
@ 2024-10-02 19:36 ` Kees Bakker
0 siblings, 0 replies; 41+ messages in thread
From: Kees Bakker @ 2024-10-02 19:36 UTC (permalink / raw)
To: Drew Fustini, Drew Fustini, Guo Ren, Fu Wei, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing,
Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel
Op 30-09-2024 om 21:50 schreef Drew Fustini:
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add pinctrl driver for the T-Head TH1520 RISC-V SoC.
>
> Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> [dfustini: use thead,pad-group to identify the pin controller instance]
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
> MAINTAINERS | 1 +
> drivers/pinctrl/Kconfig | 13 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/pinctrl-th1520.c | 907 +++++++++++++++++++++++++++++++++++++++
> 4 files changed, 922 insertions(+)
>
> [...]
> +static int th1520_pinmux_set_mux(struct pinctrl_dev *pctldev,
> + unsigned int fsel, unsigned int gsel)
> +{
> + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
> + const struct function_desc *func = pinmux_generic_get_function(pctldev, fsel);
func can be NULL after calling pinmux_generic_get_function
Please add something to avoid NULL pointer dereferencing in the next
statement.
All other callers of pinmux_generic_get_function have something like this:
if (!func)
return -EINVAL;
> +
> + return th1520_pinmux_set(thp, thp->desc.pins[gsel].number,
> + (uintptr_t)thp->desc.pins[gsel].drv_data & TH1520_PAD_MUXDATA,
> + (uintptr_t)func->data);
> +}
> +
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
2024-10-02 18:34 ` Drew Fustini
@ 2024-10-02 20:46 ` Linus Walleij
-1 siblings, 0 replies; 41+ messages in thread
From: Linus Walleij @ 2024-10-02 20:46 UTC (permalink / raw)
To: Drew Fustini
Cc: Drew Fustini, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Emil Renner Berthing, Thomas Bonnefille, linux-riscv, linux-gpio,
devicetree, linux-kernel
On Wed, Oct 2, 2024 at 8:35 PM Drew Fustini <dfustini@tenstorrent.com> wrote:
> > Then I merged that into my "devel" branch for v6.13.
>
> Thanks for taking this. Will that also end up in linux-next eventually?
Yes next -next.
> I'm working on a TH1520 Ethernet driver which depends on the pinctrl
> driver. Andrew Lunn replied to me that all the dependencies need to be
> in linux-next [1].
Well compile-time dependencies for sure, run-time dependencies
we are usually a bit lax with as long as we know they will
get there eventually.
> > I think I'll make a stab at using guarded mutexes etc and see what
> > you think about it!
>
> Do you mean using scoped_guard() for thp->mutex in
> th1520_pinctrl_dt_node_to_map()?
For all mutex and spinlocks in the driver.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
@ 2024-10-02 20:46 ` Linus Walleij
0 siblings, 0 replies; 41+ messages in thread
From: Linus Walleij @ 2024-10-02 20:46 UTC (permalink / raw)
To: Drew Fustini
Cc: Drew Fustini, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Emil Renner Berthing, Thomas Bonnefille, linux-riscv, linux-gpio,
devicetree, linux-kernel
On Wed, Oct 2, 2024 at 8:35 PM Drew Fustini <dfustini@tenstorrent.com> wrote:
> > Then I merged that into my "devel" branch for v6.13.
>
> Thanks for taking this. Will that also end up in linux-next eventually?
Yes next -next.
> I'm working on a TH1520 Ethernet driver which depends on the pinctrl
> driver. Andrew Lunn replied to me that all the dependencies need to be
> in linux-next [1].
Well compile-time dependencies for sure, run-time dependencies
we are usually a bit lax with as long as we know they will
get there eventually.
> > I think I'll make a stab at using guarded mutexes etc and see what
> > you think about it!
>
> Do you mean using scoped_guard() for thp->mutex in
> th1520_pinctrl_dt_node_to_map()?
For all mutex and spinlocks in the driver.
Yours,
Linus Walleij
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
2024-10-02 20:46 ` Linus Walleij
@ 2024-10-03 0:02 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-10-03 0:02 UTC (permalink / raw)
To: Linus Walleij
Cc: Drew Fustini, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Emil Renner Berthing, Thomas Bonnefille, linux-riscv, linux-gpio,
devicetree, linux-kernel
On Wed, Oct 02, 2024 at 10:46:41PM +0200, Linus Walleij wrote:
> On Wed, Oct 2, 2024 at 8:35 PM Drew Fustini <dfustini@tenstorrent.com> wrote:
>
> > > Then I merged that into my "devel" branch for v6.13.
> >
> > Thanks for taking this. Will that also end up in linux-next eventually?
>
> Yes next -next.
>
> > I'm working on a TH1520 Ethernet driver which depends on the pinctrl
> > driver. Andrew Lunn replied to me that all the dependencies need to be
> > in linux-next [1].
>
> Well compile-time dependencies for sure, run-time dependencies
> we are usually a bit lax with as long as we know they will
> get there eventually.
>
> > > I think I'll make a stab at using guarded mutexes etc and see what
> > > you think about it!
> >
> > Do you mean using scoped_guard() for thp->mutex in
> > th1520_pinctrl_dt_node_to_map()?
>
> For all mutex and spinlocks in the driver.
The thp->lock spinlock is already using scoped_guard() everywhere.
I will post a patch that adds guard() for the thp->mutex like this:
diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c
index 1bb78b212fd5..b7c2d998e9e7 100644
--- a/drivers/pinctrl/pinctrl-th1520.c
+++ b/drivers/pinctrl/pinctrl-th1520.c
@@ -444,8 +444,8 @@ static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
return -ENOMEM;
nmaps = 0;
- mutex_lock(&thp->mutex);
- for_each_available_child_of_node(np, child) {
+ guard(mutex)(&thp->mutex);
+ for_each_available_child_of_node_scoped(np, child) {
unsigned int rollback = nmaps;
enum th1520_muxtype muxtype;
struct property *prop;
@@ -530,7 +530,6 @@ static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
*maps = map;
*num_maps = nmaps;
- mutex_unlock(&thp->mutex);
return 0;
free_configs:
@@ -538,7 +537,6 @@ static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
put_child:
of_node_put(child);
th1520_pinctrl_dt_free_map(pctldev, map, nmaps);
- mutex_unlock(&thp->mutex);
return ret;
}
--
Thanks,
Drew
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
@ 2024-10-03 0:02 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-10-03 0:02 UTC (permalink / raw)
To: Linus Walleij
Cc: Drew Fustini, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Emil Renner Berthing, Thomas Bonnefille, linux-riscv, linux-gpio,
devicetree, linux-kernel
On Wed, Oct 02, 2024 at 10:46:41PM +0200, Linus Walleij wrote:
> On Wed, Oct 2, 2024 at 8:35 PM Drew Fustini <dfustini@tenstorrent.com> wrote:
>
> > > Then I merged that into my "devel" branch for v6.13.
> >
> > Thanks for taking this. Will that also end up in linux-next eventually?
>
> Yes next -next.
>
> > I'm working on a TH1520 Ethernet driver which depends on the pinctrl
> > driver. Andrew Lunn replied to me that all the dependencies need to be
> > in linux-next [1].
>
> Well compile-time dependencies for sure, run-time dependencies
> we are usually a bit lax with as long as we know they will
> get there eventually.
>
> > > I think I'll make a stab at using guarded mutexes etc and see what
> > > you think about it!
> >
> > Do you mean using scoped_guard() for thp->mutex in
> > th1520_pinctrl_dt_node_to_map()?
>
> For all mutex and spinlocks in the driver.
The thp->lock spinlock is already using scoped_guard() everywhere.
I will post a patch that adds guard() for the thp->mutex like this:
diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c
index 1bb78b212fd5..b7c2d998e9e7 100644
--- a/drivers/pinctrl/pinctrl-th1520.c
+++ b/drivers/pinctrl/pinctrl-th1520.c
@@ -444,8 +444,8 @@ static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
return -ENOMEM;
nmaps = 0;
- mutex_lock(&thp->mutex);
- for_each_available_child_of_node(np, child) {
+ guard(mutex)(&thp->mutex);
+ for_each_available_child_of_node_scoped(np, child) {
unsigned int rollback = nmaps;
enum th1520_muxtype muxtype;
struct property *prop;
@@ -530,7 +530,6 @@ static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
*maps = map;
*num_maps = nmaps;
- mutex_unlock(&thp->mutex);
return 0;
free_configs:
@@ -538,7 +537,6 @@ static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
put_child:
of_node_put(child);
th1520_pinctrl_dt_free_map(pctldev, map, nmaps);
- mutex_unlock(&thp->mutex);
return ret;
}
--
Thanks,
Drew
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
2024-10-02 19:36 ` Kees Bakker
@ 2024-10-03 2:43 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-10-03 2:43 UTC (permalink / raw)
To: Kees Bakker
Cc: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille, linux-riscv,
linux-gpio, devicetree, linux-kernel
On Wed, Oct 02, 2024 at 09:36:59PM +0200, Kees Bakker wrote:
> Op 30-09-2024 om 21:50 schreef Drew Fustini:
> > From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >
> > Add pinctrl driver for the T-Head TH1520 RISC-V SoC.
> >
> > Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > [dfustini: use thead,pad-group to identify the pin controller instance]
> > Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> > ---
> > MAINTAINERS | 1 +
> > drivers/pinctrl/Kconfig | 13 +
> > drivers/pinctrl/Makefile | 1 +
> > drivers/pinctrl/pinctrl-th1520.c | 907 +++++++++++++++++++++++++++++++++++++++
> > 4 files changed, 922 insertions(+)
> >
> > [...]
> > +static int th1520_pinmux_set_mux(struct pinctrl_dev *pctldev,
> > + unsigned int fsel, unsigned int gsel)
> > +{
> > + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
> > + const struct function_desc *func = pinmux_generic_get_function(pctldev, fsel);
> func can be NULL after calling pinmux_generic_get_function
> Please add something to avoid NULL pointer dereferencing in the next
> statement.
> All other callers of pinmux_generic_get_function have something like this:
> if (!func)
> return -EINVAL;
Thanks for catching this. I see that another person has posted a patch
as a result so I'll respond over in that thread [1].
Drew
[1] https://lore.kernel.org/lkml/20241003023307.2138695-1-clf700383@gmail.com/
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
@ 2024-10-03 2:43 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-10-03 2:43 UTC (permalink / raw)
To: Kees Bakker
Cc: Drew Fustini, Guo Ren, Fu Wei, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Emil Renner Berthing, Thomas Bonnefille, linux-riscv,
linux-gpio, devicetree, linux-kernel
On Wed, Oct 02, 2024 at 09:36:59PM +0200, Kees Bakker wrote:
> Op 30-09-2024 om 21:50 schreef Drew Fustini:
> > From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >
> > Add pinctrl driver for the T-Head TH1520 RISC-V SoC.
> >
> > Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > [dfustini: use thead,pad-group to identify the pin controller instance]
> > Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> > ---
> > MAINTAINERS | 1 +
> > drivers/pinctrl/Kconfig | 13 +
> > drivers/pinctrl/Makefile | 1 +
> > drivers/pinctrl/pinctrl-th1520.c | 907 +++++++++++++++++++++++++++++++++++++++
> > 4 files changed, 922 insertions(+)
> >
> > [...]
> > +static int th1520_pinmux_set_mux(struct pinctrl_dev *pctldev,
> > + unsigned int fsel, unsigned int gsel)
> > +{
> > + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
> > + const struct function_desc *func = pinmux_generic_get_function(pctldev, fsel);
> func can be NULL after calling pinmux_generic_get_function
> Please add something to avoid NULL pointer dereferencing in the next
> statement.
> All other callers of pinmux_generic_get_function have something like this:
> if (!func)
> return -EINVAL;
Thanks for catching this. I see that another person has posted a patch
as a result so I'll respond over in that thread [1].
Drew
[1] https://lore.kernel.org/lkml/20241003023307.2138695-1-clf700383@gmail.com/
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
2024-10-02 15:54 ` Dan Carpenter
@ 2024-10-05 19:30 ` Drew Fustini
2024-10-07 5:30 ` Dan Carpenter
0 siblings, 1 reply; 41+ messages in thread
From: Drew Fustini @ 2024-10-05 19:30 UTC (permalink / raw)
To: Dan Carpenter; +Cc: oe-kbuild, lkp, oe-kbuild-all
On Wed, Oct 02, 2024 at 06:54:48PM +0300, Dan Carpenter wrote:
> Hi Drew,
>
> kernel test robot noticed the following build warnings:
>
> url: https://github.com/intel-lab-lkp/linux/commits/Drew-Fustini/dt-bindings-pinctrl-Add-thead-th1520-pinctrl-bindings/20241001-035421
> base: 9852d85ec9d492ebef56dc5f229416c925758edc
> patch link: https://lore.kernel.org/r/20240930-th1520-pinctrl-v3-2-32cea2bdbecb%40tenstorrent.com
> patch subject: [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
> config: s390-randconfig-r072-20241002 (https://download.01.org/0day-ci/archive/20241002/202410022336.xyWlV0Tf-lkp@intel.com/config)
> compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
> | Closes: https://lore.kernel.org/r/202410022336.xyWlV0Tf-lkp@intel.com/
I put these tags in the patch I'm about to send but I get this
checkpatch warning:
-----------------------------------------------------------
WARNING: Reported-by: should be immediately followed by Closes: with a URL to the report
#9:
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
total: 0 errors, 1 warnings, 7 lines checked
NOTE: For some of the reported defects, checkpatch may be able to
mechanically convert to the typical style using --fix or --fix-inplace.
Commit 8d7cdbc31c9f ("pinctrl: th1520: Fix return value for unknown pin error") has style problems, please review.
NOTE: If any of the errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.
-----------------------------------------------------------
If I remove the first Reported-by, then checkpatch no longer complains.
Am I missing something?
Thanks,
Drew
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
2024-10-05 19:30 ` Drew Fustini
@ 2024-10-07 5:30 ` Dan Carpenter
0 siblings, 0 replies; 41+ messages in thread
From: Dan Carpenter @ 2024-10-07 5:30 UTC (permalink / raw)
To: Drew Fustini; +Cc: oe-kbuild, lkp, oe-kbuild-all
On Sat, Oct 05, 2024 at 12:30:16PM -0700, Drew Fustini wrote:
> On Wed, Oct 02, 2024 at 06:54:48PM +0300, Dan Carpenter wrote:
> > Hi Drew,
> >
> > kernel test robot noticed the following build warnings:
> >
> > url: https://github.com/intel-lab-lkp/linux/commits/Drew-Fustini/dt-bindings-pinctrl-Add-thead-th1520-pinctrl-bindings/20241001-035421
> > base: 9852d85ec9d492ebef56dc5f229416c925758edc
> > patch link: https://lore.kernel.org/r/20240930-th1520-pinctrl-v3-2-32cea2bdbecb%40tenstorrent.com
> > patch subject: [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC
> > config: s390-randconfig-r072-20241002 (https://download.01.org/0day-ci/archive/20241002/202410022336.xyWlV0Tf-lkp@intel.com/config)
> > compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
> >
> > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > the same patch/commit), kindly add following tags
> > | Reported-by: kernel test robot <lkp@intel.com>
> > | Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
> > | Closes: https://lore.kernel.org/r/202410022336.xyWlV0Tf-lkp@intel.com/
>
> I put these tags in the patch I'm about to send but I get this
> checkpatch warning:
>
> -----------------------------------------------------------
> WARNING: Reported-by: should be immediately followed by Closes: with a URL to the report
> #9:
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
>
> total: 0 errors, 1 warnings, 7 lines checked
>
> NOTE: For some of the reported defects, checkpatch may be able to
> mechanically convert to the typical style using --fix or --fix-inplace.
>
> Commit 8d7cdbc31c9f ("pinctrl: th1520: Fix return value for unknown pin error") has style problems, please review.
>
> NOTE: If any of the errors are false positives, please report
> them to the maintainer, see CHECKPATCH in MAINTAINERS.
> -----------------------------------------------------------
>
> If I remove the first Reported-by, then checkpatch no longer complains.
You can always ignore checkpatch. It's just a script, not an emperor.
regards,
dan carpenter
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
2024-09-30 19:50 ` Drew Fustini
@ 2024-10-11 17:22 ` Drew Fustini
-1 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-10-11 17:22 UTC (permalink / raw)
To: Drew Fustini
Cc: Guo Ren, Fu Wei, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Emil Renner Berthing, Thomas Bonnefille, linux-riscv, linux-gpio,
devicetree, linux-kernel
On Mon, Sep 30, 2024 at 12:50:50PM -0700, Drew Fustini wrote:
> This adds a pin control driver created by Emil for the T-Head TH1520
> RISC-V SoC used on the Lichee Pi 4A and BeagleV Ahead boards and updates
> the device trees to make use of it.
>
> Changes in v3:
> - Add Rb from Rob for the binding
> - Rebase on 6.12-rc1 which enables AP_SUBSYS clock controller in dts
> - Update dts to use AP_SUBSYS clock controller instead of fixed clocks
> - Remove unneeded defines from the driver for dt unit addresses
> - Link to v2: https://lore.kernel.org/linux-riscv/20240914-th1520-pinctrl-v2-0-3ba67dde882c@tenstorrent.com/
>
> [...]
I've applied the dts patches to my thead-dt-for-next [1]
[3/8] riscv: dts: thead: Add TH1520 pin control nodes
commit: ad36d24e4fac83a6cf916fbf7eb458ed5179758b
[4/8] riscv: dts: thead: Add TH1520 GPIO ranges
commit: 5c0a6b845d1670c7a10d8016cb352c21b0133935
[5/8] riscv: dts: thead: Adjust TH1520 GPIO labels
commit: 2a3aaf5fd062e9a820c420b02795acf6e031c855
[6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names
commit: 753c9640121235b3ea26137f3a2dcbb301fa8556
[7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0
commit: 5aa0a71414f1e4fcacd64146d40e78ecdfc26374
[8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs
commit: ddc5ab7259a525670fbea6e9bda5334022aae050
Thanks,
Drew
[1] https://github.com/pdp7/linux/commits/thead-dt-for-next/
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers
@ 2024-10-11 17:22 ` Drew Fustini
0 siblings, 0 replies; 41+ messages in thread
From: Drew Fustini @ 2024-10-11 17:22 UTC (permalink / raw)
To: Drew Fustini
Cc: Guo Ren, Fu Wei, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Emil Renner Berthing, Thomas Bonnefille, linux-riscv, linux-gpio,
devicetree, linux-kernel
On Mon, Sep 30, 2024 at 12:50:50PM -0700, Drew Fustini wrote:
> This adds a pin control driver created by Emil for the T-Head TH1520
> RISC-V SoC used on the Lichee Pi 4A and BeagleV Ahead boards and updates
> the device trees to make use of it.
>
> Changes in v3:
> - Add Rb from Rob for the binding
> - Rebase on 6.12-rc1 which enables AP_SUBSYS clock controller in dts
> - Update dts to use AP_SUBSYS clock controller instead of fixed clocks
> - Remove unneeded defines from the driver for dt unit addresses
> - Link to v2: https://lore.kernel.org/linux-riscv/20240914-th1520-pinctrl-v2-0-3ba67dde882c@tenstorrent.com/
>
> [...]
I've applied the dts patches to my thead-dt-for-next [1]
[3/8] riscv: dts: thead: Add TH1520 pin control nodes
commit: ad36d24e4fac83a6cf916fbf7eb458ed5179758b
[4/8] riscv: dts: thead: Add TH1520 GPIO ranges
commit: 5c0a6b845d1670c7a10d8016cb352c21b0133935
[5/8] riscv: dts: thead: Adjust TH1520 GPIO labels
commit: 2a3aaf5fd062e9a820c420b02795acf6e031c855
[6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names
commit: 753c9640121235b3ea26137f3a2dcbb301fa8556
[7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0
commit: 5aa0a71414f1e4fcacd64146d40e78ecdfc26374
[8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs
commit: ddc5ab7259a525670fbea6e9bda5334022aae050
Thanks,
Drew
[1] https://github.com/pdp7/linux/commits/thead-dt-for-next/
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names
2024-09-30 19:50 ` Drew Fustini
@ 2024-10-12 13:46 ` Emil Renner Berthing
-1 siblings, 0 replies; 41+ messages in thread
From: Emil Renner Berthing @ 2024-10-12 13:46 UTC (permalink / raw)
To: Drew Fustini, Drew Fustini, Guo Ren, Fu Wei, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing,
Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel
Drew Fustini wrote:
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add names for the GPIO00-GPIO14 lines of the SO-DIMM module.
>
> Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
> .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 39 ++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> index bf1c639072b8..ca84bc2039ef 100644
> --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> @@ -29,6 +29,12 @@ &aonsys_clk {
> clock-frequency = <73728000>;
> };
>
> +&aogpio {
> + gpio-line-names = "", "", "",
> + "GPIO00",
> + "GPIO04";
> +};
> +
> &dmac0 {
> status = "okay";
> };
> @@ -48,3 +54,36 @@ &sdio0 {
> max-frequency = <198000000>;
> status = "okay";
> };
> +
> +&gpio0 {
> + gpio-line-names = "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "",
> + "GPIO07",
> + "GPIO08",
> + "",
> + "GPIO01",
> + "GPIO02";
> +};
> +
> +&gpio1 {
> + gpio-line-names = "", "", "",
> + "GPIO11",
> + "GPIO12",
> + "GPIO13",
> + "GPIO14",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "",
> + "GPIO06";
> +};
> +
> +&gpio2 {
> + gpio-line-names = "GPIO03",
> + "GPIO05";
> +};
> +
> +&gpio3 {
> + gpio-line-names = "", "",
> + "GPIO09",
> + "GPIO10";
> +};
Hi Drew,
I just noticed you've moved these entries compared to my original patches, so
they're no longer sorted alphabetically. Why?
Please see https://docs.kernel.org/devicetree/bindings/dts-coding-style.html
under "Order of Nodes".
/Emil
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names
@ 2024-10-12 13:46 ` Emil Renner Berthing
0 siblings, 0 replies; 41+ messages in thread
From: Emil Renner Berthing @ 2024-10-12 13:46 UTC (permalink / raw)
To: Drew Fustini, Drew Fustini, Guo Ren, Fu Wei, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing,
Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel
Drew Fustini wrote:
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add names for the GPIO00-GPIO14 lines of the SO-DIMM module.
>
> Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
> .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 39 ++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> index bf1c639072b8..ca84bc2039ef 100644
> --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> @@ -29,6 +29,12 @@ &aonsys_clk {
> clock-frequency = <73728000>;
> };
>
> +&aogpio {
> + gpio-line-names = "", "", "",
> + "GPIO00",
> + "GPIO04";
> +};
> +
> &dmac0 {
> status = "okay";
> };
> @@ -48,3 +54,36 @@ &sdio0 {
> max-frequency = <198000000>;
> status = "okay";
> };
> +
> +&gpio0 {
> + gpio-line-names = "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "",
> + "GPIO07",
> + "GPIO08",
> + "",
> + "GPIO01",
> + "GPIO02";
> +};
> +
> +&gpio1 {
> + gpio-line-names = "", "", "",
> + "GPIO11",
> + "GPIO12",
> + "GPIO13",
> + "GPIO14",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "",
> + "GPIO06";
> +};
> +
> +&gpio2 {
> + gpio-line-names = "GPIO03",
> + "GPIO05";
> +};
> +
> +&gpio3 {
> + gpio-line-names = "", "",
> + "GPIO09",
> + "GPIO10";
> +};
Hi Drew,
I just noticed you've moved these entries compared to my original patches, so
they're no longer sorted alphabetically. Why?
Please see https://docs.kernel.org/devicetree/bindings/dts-coding-style.html
under "Order of Nodes".
/Emil
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0
2024-09-30 19:50 ` Drew Fustini
@ 2024-10-12 13:48 ` Emil Renner Berthing
-1 siblings, 0 replies; 41+ messages in thread
From: Emil Renner Berthing @ 2024-10-12 13:48 UTC (permalink / raw)
To: Drew Fustini, Drew Fustini, Guo Ren, Fu Wei, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing,
Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel
Drew Fustini wrote:
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add pinctrl settings for UART0 used as the default debug console on
> both the Lichee Pi 4A and BeagleV Ahead boards.
>
> Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
> arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 26 ++++++++++++++++++++++
> arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 26 ++++++++++++++++++++++
> 2 files changed, 52 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> index 69f82e7afd0b..6c0b768e8d17 100644
> --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> @@ -71,7 +71,33 @@ &sdio0 {
> status = "okay";
> };
>
> +&padctrl0_apsys {
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pins = "UART0_TXD";
> + function = "uart";
> + bias-disable;
> + drive-strength = <3>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pins = "UART0_RXD";
> + function = "uart";
> + bias-disable;
> + drive-strength = <1>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> &uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> index 58ad381fc1c3..f60b1879192d 100644
> --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> @@ -30,7 +30,33 @@ chosen {
> };
> };
>
> +&padctrl0_apsys {
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pins = "UART0_TXD";
> + function = "uart";
> + bias-disable;
> + drive-strength = <3>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pins = "UART0_RXD";
> + function = "uart";
> + bias-disable;
> + drive-strength = <1>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> &uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
For these two files you also broke the ordering.
/Emil
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0
@ 2024-10-12 13:48 ` Emil Renner Berthing
0 siblings, 0 replies; 41+ messages in thread
From: Emil Renner Berthing @ 2024-10-12 13:48 UTC (permalink / raw)
To: Drew Fustini, Drew Fustini, Guo Ren, Fu Wei, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing,
Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel
Drew Fustini wrote:
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add pinctrl settings for UART0 used as the default debug console on
> both the Lichee Pi 4A and BeagleV Ahead boards.
>
> Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
> arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 26 ++++++++++++++++++++++
> arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 26 ++++++++++++++++++++++
> 2 files changed, 52 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> index 69f82e7afd0b..6c0b768e8d17 100644
> --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> @@ -71,7 +71,33 @@ &sdio0 {
> status = "okay";
> };
>
> +&padctrl0_apsys {
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pins = "UART0_TXD";
> + function = "uart";
> + bias-disable;
> + drive-strength = <3>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pins = "UART0_RXD";
> + function = "uart";
> + bias-disable;
> + drive-strength = <1>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> &uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> index 58ad381fc1c3..f60b1879192d 100644
> --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> @@ -30,7 +30,33 @@ chosen {
> };
> };
>
> +&padctrl0_apsys {
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pins = "UART0_TXD";
> + function = "uart";
> + bias-disable;
> + drive-strength = <3>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pins = "UART0_RXD";
> + function = "uart";
> + bias-disable;
> + drive-strength = <1>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> &uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
For these two files you also broke the ordering.
/Emil
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs
2024-09-30 19:50 ` Drew Fustini
@ 2024-10-12 14:41 ` Emil Renner Berthing
-1 siblings, 0 replies; 41+ messages in thread
From: Emil Renner Berthing @ 2024-10-12 14:41 UTC (permalink / raw)
To: Drew Fustini, Drew Fustini, Guo Ren, Fu Wei, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing,
Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel
Drew Fustini wrote:
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add nodes for the 5 user controllable LEDs on the BeagleV Ahead board.
>
> Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
> arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 55 ++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> index 6c0b768e8d17..5a5888f4eda6 100644
> --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> @@ -7,6 +7,8 @@
> /dts-v1/;
>
> #include "th1520.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
>
> / {
> model = "BeagleV Ahead";
> @@ -35,7 +37,42 @@ chosen {
> memory@0 {
> device_type = "memory";
> reg = <0x0 0x00000000 0x1 0x00000000>;
> + };
> +
> + leds {
> + pinctrl-names = "default";
> + pinctrl-0 = <&led_pins>;
> + compatible = "gpio-leds";
> +
> + led-1 {
> + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
Here you're also missing important changes from the tree I told you to use.
These should be GPIO_ACTIVE_HIGH otherwise the LEDs will be on when they should
be off.
> + color = <LED_COLOR_ID_BLUE>;
> + label = "led1";
> + };
> +
> + led-2 {
> + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
> + color = <LED_COLOR_ID_BLUE>;
> + label = "led2";
> + };
> +
> + led-3 {
> + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
> + color = <LED_COLOR_ID_BLUE>;
> + label = "led3";
> + };
> +
> + led-4 {
> + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
> + color = <LED_COLOR_ID_BLUE>;
> + label = "led4";
> + };
>
> + led-5 {
> + gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
> + color = <LED_COLOR_ID_BLUE>;
> + label = "led5";
> + };
> };
> };
>
> @@ -71,6 +108,24 @@ &sdio0 {
> status = "okay";
> };
>
> +&padctrl_aosys {
> + led_pins: led-0 {
> + led-pins {
> + pins = "AUDIO_PA8", /* GPIO4_8 */
> + "AUDIO_PA9", /* GPIO4_9 */
> + "AUDIO_PA10", /* GPIO4_10 */
> + "AUDIO_PA11", /* GPIO4_11 */
> + "AUDIO_PA12"; /* GPIO4_12 */
> + function = "gpio";
You've also added this line which results in an error like this:
pinctrl-th1520 fffff4a000.pinctrl: pin AUDIO_PA8 already requested
by leds; cannot claim for fffff52000.gpio:536
Did you run this on your BeagleV Ahead?
/Emil
> + bias-disable;
> + drive-strength = <3>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> &padctrl0_apsys {
> uart0_pins: uart0-0 {
> tx-pins {
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs
@ 2024-10-12 14:41 ` Emil Renner Berthing
0 siblings, 0 replies; 41+ messages in thread
From: Emil Renner Berthing @ 2024-10-12 14:41 UTC (permalink / raw)
To: Drew Fustini, Drew Fustini, Guo Ren, Fu Wei, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Emil Renner Berthing,
Thomas Bonnefille
Cc: linux-riscv, linux-gpio, devicetree, linux-kernel
Drew Fustini wrote:
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add nodes for the 5 user controllable LEDs on the BeagleV Ahead board.
>
> Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
> arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 55 ++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> index 6c0b768e8d17..5a5888f4eda6 100644
> --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> @@ -7,6 +7,8 @@
> /dts-v1/;
>
> #include "th1520.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
>
> / {
> model = "BeagleV Ahead";
> @@ -35,7 +37,42 @@ chosen {
> memory@0 {
> device_type = "memory";
> reg = <0x0 0x00000000 0x1 0x00000000>;
> + };
> +
> + leds {
> + pinctrl-names = "default";
> + pinctrl-0 = <&led_pins>;
> + compatible = "gpio-leds";
> +
> + led-1 {
> + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
Here you're also missing important changes from the tree I told you to use.
These should be GPIO_ACTIVE_HIGH otherwise the LEDs will be on when they should
be off.
> + color = <LED_COLOR_ID_BLUE>;
> + label = "led1";
> + };
> +
> + led-2 {
> + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
> + color = <LED_COLOR_ID_BLUE>;
> + label = "led2";
> + };
> +
> + led-3 {
> + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
> + color = <LED_COLOR_ID_BLUE>;
> + label = "led3";
> + };
> +
> + led-4 {
> + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
> + color = <LED_COLOR_ID_BLUE>;
> + label = "led4";
> + };
>
> + led-5 {
> + gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
> + color = <LED_COLOR_ID_BLUE>;
> + label = "led5";
> + };
> };
> };
>
> @@ -71,6 +108,24 @@ &sdio0 {
> status = "okay";
> };
>
> +&padctrl_aosys {
> + led_pins: led-0 {
> + led-pins {
> + pins = "AUDIO_PA8", /* GPIO4_8 */
> + "AUDIO_PA9", /* GPIO4_9 */
> + "AUDIO_PA10", /* GPIO4_10 */
> + "AUDIO_PA11", /* GPIO4_11 */
> + "AUDIO_PA12"; /* GPIO4_12 */
> + function = "gpio";
You've also added this line which results in an error like this:
pinctrl-th1520 fffff4a000.pinctrl: pin AUDIO_PA8 already requested
by leds; cannot claim for fffff52000.gpio:536
Did you run this on your BeagleV Ahead?
/Emil
> + bias-disable;
> + drive-strength = <3>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> &padctrl0_apsys {
> uart0_pins: uart0-0 {
> tx-pins {
>
> --
> 2.34.1
>
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^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2024-10-12 14:52 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-09-30 19:50 [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers Drew Fustini
2024-09-30 19:50 ` Drew Fustini
2024-09-30 19:50 ` [PATCH v3 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings Drew Fustini
2024-09-30 19:50 ` Drew Fustini
2024-09-30 19:50 ` [PATCH v3 2/8] pinctrl: Add driver for the T-Head TH1520 SoC Drew Fustini
2024-09-30 19:50 ` Drew Fustini
2024-10-02 15:54 ` Dan Carpenter
2024-10-05 19:30 ` Drew Fustini
2024-10-07 5:30 ` Dan Carpenter
2024-10-02 19:36 ` Kees Bakker
2024-10-02 19:36 ` Kees Bakker
2024-10-03 2:43 ` Drew Fustini
2024-10-03 2:43 ` Drew Fustini
2024-09-30 19:50 ` [PATCH v3 3/8] riscv: dts: thead: Add TH1520 pin control nodes Drew Fustini
2024-09-30 19:50 ` Drew Fustini
2024-09-30 19:50 ` [PATCH v3 4/8] riscv: dts: thead: Add TH1520 GPIO ranges Drew Fustini
2024-09-30 19:50 ` Drew Fustini
2024-09-30 19:50 ` [PATCH v3 5/8] riscv: dts: thead: Adjust TH1520 GPIO labels Drew Fustini
2024-09-30 19:50 ` Drew Fustini
2024-09-30 19:50 ` [PATCH v3 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names Drew Fustini
2024-09-30 19:50 ` Drew Fustini
2024-10-12 13:46 ` Emil Renner Berthing
2024-10-12 13:46 ` Emil Renner Berthing
2024-09-30 19:50 ` [PATCH v3 7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0 Drew Fustini
2024-09-30 19:50 ` Drew Fustini
2024-10-12 13:48 ` Emil Renner Berthing
2024-10-12 13:48 ` Emil Renner Berthing
2024-09-30 19:50 ` [PATCH v3 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs Drew Fustini
2024-09-30 19:50 ` Drew Fustini
2024-10-12 14:41 ` Emil Renner Berthing
2024-10-12 14:41 ` Emil Renner Berthing
2024-10-01 12:13 ` [PATCH v3 0/8] pinctrl: Add T-Head TH1520 SoC pin controllers Linus Walleij
2024-10-01 12:13 ` Linus Walleij
2024-10-02 18:34 ` Drew Fustini
2024-10-02 18:34 ` Drew Fustini
2024-10-02 20:46 ` Linus Walleij
2024-10-02 20:46 ` Linus Walleij
2024-10-03 0:02 ` Drew Fustini
2024-10-03 0:02 ` Drew Fustini
2024-10-11 17:22 ` Drew Fustini
2024-10-11 17:22 ` Drew Fustini
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