* [PATCH v2 0/2] add S32G2/S32G3 uSDHC pinmux
@ 2024-08-30 11:33 Ciprian Costea
2024-08-30 11:33 ` [PATCH v2 1/2] arm64: dts: s32g: Add " Ciprian Costea
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Ciprian Costea @ 2024-08-30 11:33 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux Team, Ciprian Marian Costea
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
This patchset adds 100mhz & 200mhz pinmux support for uSDHC.
Hence, UHS modes would be supported on NXP boards which enable
usage of VCCQ voltage supply @1.8V by default, with no additional
hardware (board) changes required, such as S32G399A-RDB3.
Changes in V2:
- Added patch for disablement of UHS modes for NXP boards
where VCCQ voltage supply is set to 3.3V by default.
- Fixed S32G2, S32G3 dtb checks warnings related to uSDHC
pinmux renaming.
Ciprian Marian Costea (2):
arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux
arm64: dts: s32g2: Disable support for SD/eMMC UHS mode
arch/arm64/boot/dts/freescale/s32g2.dtsi | 153 ++++++++++++++++++
.../arm64/boot/dts/freescale/s32g274a-evb.dts | 5 +
.../boot/dts/freescale/s32g274a-rdb2.dts | 13 ++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 153 ++++++++++++++++++
.../boot/dts/freescale/s32g399a-rdb3.dts | 4 +
5 files changed, 328 insertions(+)
--
2.45.2
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 1/2] arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux 2024-08-30 11:33 [PATCH v2 0/2] add S32G2/S32G3 uSDHC pinmux Ciprian Costea @ 2024-08-30 11:33 ` Ciprian Costea 2024-09-06 15:53 ` Matthias Brugger 2024-09-17 17:44 ` Krzysztof Kozlowski 2024-08-30 11:33 ` [PATCH v2 2/2] arm64: dts: s32g2: Disable support for SD/eMMC UHS mode Ciprian Costea 2024-10-08 9:25 ` [PATCH v2 0/2] add S32G2/S32G3 uSDHC pinmux Shawn Guo 2 siblings, 2 replies; 8+ messages in thread From: Ciprian Costea @ 2024-08-30 11:33 UTC (permalink / raw) To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree, linux-kernel, NXP S32 Linux Team, Ciprian Marian Costea, Radu Pirea From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Adding 100mhz & 200mhz pinmux support for uSDHC helps to enable higher speed modes for SD (SDR50, DDR50, SDR104) and eMMC (such as HS200, HS400/HS400ES). Signed-off-by: Radu Pirea <radu-nicolae.pirea@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 153 ++++++++++++++++++ .../arm64/boot/dts/freescale/s32g274a-evb.dts | 4 + .../boot/dts/freescale/s32g274a-rdb2.dts | 4 + arch/arm64/boot/dts/freescale/s32g3.dtsi | 153 ++++++++++++++++++ .../boot/dts/freescale/s32g399a-rdb3.dts | 4 + 5 files changed, 318 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index fa054bfe7d5c..7be430b78c83 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -162,6 +162,159 @@ jtag-grp4 { slew-rate = <166>; }; }; + + pinctrl_usdhc0: usdhc0grp-pins { + usdhc0-grp0 { + pinmux = <0x2e1>, + <0x381>; + output-enable; + bias-pull-down; + slew-rate = <150>; + }; + + usdhc0-grp1 { + pinmux = <0x2f1>, + <0x301>, + <0x311>, + <0x321>, + <0x331>, + <0x341>, + <0x351>, + <0x361>, + <0x371>; + output-enable; + input-enable; + bias-pull-up; + slew-rate = <150>; + }; + + usdhc0-grp2 { + pinmux = <0x391>; + output-enable; + slew-rate = <150>; + }; + + usdhc0-grp3 { + pinmux = <0x3a0>; + input-enable; + slew-rate = <150>; + }; + + usdhc0-grp4 { + pinmux = <0x2032>, + <0x2042>, + <0x2052>, + <0x2062>, + <0x2072>, + <0x2082>, + <0x2092>, + <0x20a2>, + <0x20b2>, + <0x20c2>; + }; + }; + + pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { + usdhc0-100mhz-grp0 { + pinmux = <0x2e1>, + <0x381>; + output-enable; + bias-pull-down; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp1 { + pinmux = <0x2f1>, + <0x301>, + <0x311>, + <0x321>, + <0x331>, + <0x341>, + <0x351>, + <0x361>, + <0x371>; + output-enable; + input-enable; + bias-pull-up; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp2 { + pinmux = <0x391>; + output-enable; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp3 { + pinmux = <0x3a0>; + input-enable; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp4 { + pinmux = <0x2032>, + <0x2042>, + <0x2052>, + <0x2062>, + <0x2072>, + <0x2082>, + <0x2092>, + <0x20a2>, + <0x20b2>, + <0x20c2>; + }; + }; + + pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { + usdhc0-200mhz-grp0 { + pinmux = <0x2e1>, + <0x381>; + output-enable; + bias-pull-down; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp1 { + pinmux = <0x2f1>, + <0x301>, + <0x311>, + <0x321>, + <0x331>, + <0x341>, + <0x351>, + <0x361>, + <0x371>; + output-enable; + input-enable; + bias-pull-up; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp2 { + pinmux = <0x391>; + output-enable; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp3 { + pinmux = <0x3a0>; + input-enable; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp4 { + pinmux = <0x2032>, + <0x2042>, + <0x2052>, + <0x2062>, + <0x2072>, + <0x2082>, + <0x2092>, + <0x20a2>, + <0x20b2>, + <0x20c2>; + }; + }; }; uart0: serial@401c8000 { diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts index dbe498798bd9..7ab917f547ef 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts @@ -34,6 +34,10 @@ &uart0 { }; &usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; disable-wp; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index ab1e5caaeae7..8739f63771bc 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -40,6 +40,10 @@ &uart1 { }; &usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; disable-wp; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index b4226a9143c8..6c572ffe37ca 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -219,6 +219,159 @@ jtag-grp4 { slew-rate = <166>; }; }; + + pinctrl_usdhc0: usdhc0grp-pins { + usdhc0-grp0 { + pinmux = <0x2e1>, + <0x381>; + output-enable; + bias-pull-down; + slew-rate = <150>; + }; + + usdhc0-grp1 { + pinmux = <0x2f1>, + <0x301>, + <0x311>, + <0x321>, + <0x331>, + <0x341>, + <0x351>, + <0x361>, + <0x371>; + output-enable; + input-enable; + bias-pull-up; + slew-rate = <150>; + }; + + usdhc0-grp2 { + pinmux = <0x391>; + output-enable; + slew-rate = <150>; + }; + + usdhc0-grp3 { + pinmux = <0x3a0>; + input-enable; + slew-rate = <150>; + }; + + usdhc0-grp4 { + pinmux = <0x2032>, + <0x2042>, + <0x2052>, + <0x2062>, + <0x2072>, + <0x2082>, + <0x2092>, + <0x20a2>, + <0x20b2>, + <0x20c2>; + }; + }; + + pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { + usdhc0-100mhz-grp0 { + pinmux = <0x2e1>, + <0x381>; + output-enable; + bias-pull-down; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp1 { + pinmux = <0x2f1>, + <0x301>, + <0x311>, + <0x321>, + <0x331>, + <0x341>, + <0x351>, + <0x361>, + <0x371>; + output-enable; + input-enable; + bias-pull-up; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp2 { + pinmux = <0x391>; + output-enable; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp3 { + pinmux = <0x3a0>; + input-enable; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp4 { + pinmux = <0x2032>, + <0x2042>, + <0x2052>, + <0x2062>, + <0x2072>, + <0x2082>, + <0x2092>, + <0x20a2>, + <0x20b2>, + <0x20c2>; + }; + }; + + pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { + usdhc0-200mhz-grp0 { + pinmux = <0x2e1>, + <0x381>; + output-enable; + bias-pull-down; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp1 { + pinmux = <0x2f1>, + <0x301>, + <0x311>, + <0x321>, + <0x331>, + <0x341>, + <0x351>, + <0x361>, + <0x371>; + output-enable; + input-enable; + bias-pull-up; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp2 { + pinmux = <0x391>; + output-enable; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp3 { + pinmux = <0x3a0>; + input-enable; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp4 { + pinmux = <0x2032>, + <0x2042>, + <0x2052>, + <0x2062>, + <0x2072>, + <0x2082>, + <0x2092>, + <0x20a2>, + <0x20b2>, + <0x20c2>; + }; + }; }; uart0: serial@401c8000 { diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts index 176e5af191c8..828e353455b5 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -40,6 +40,10 @@ &uart1 { }; &usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; bus-width = <8>; disable-wp; status = "okay"; -- 2.45.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux 2024-08-30 11:33 ` [PATCH v2 1/2] arm64: dts: s32g: Add " Ciprian Costea @ 2024-09-06 15:53 ` Matthias Brugger 2024-09-17 17:44 ` Krzysztof Kozlowski 1 sibling, 0 replies; 8+ messages in thread From: Matthias Brugger @ 2024-09-06 15:53 UTC (permalink / raw) To: Ciprian Costea, Chester Lin, Ghennadi Procopciuc, Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree, linux-kernel, NXP S32 Linux Team, Radu Pirea On 30/08/2024 13:33, Ciprian Costea wrote: > From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > > Adding 100mhz & 200mhz pinmux support for uSDHC helps to enable > higher speed modes for SD (SDR50, DDR50, SDR104) and > eMMC (such as HS200, HS400/HS400ES). > > Signed-off-by: Radu Pirea <radu-nicolae.pirea@nxp.com> > Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > arch/arm64/boot/dts/freescale/s32g2.dtsi | 153 ++++++++++++++++++ > .../arm64/boot/dts/freescale/s32g274a-evb.dts | 4 + > .../boot/dts/freescale/s32g274a-rdb2.dts | 4 + > arch/arm64/boot/dts/freescale/s32g3.dtsi | 153 ++++++++++++++++++ > .../boot/dts/freescale/s32g399a-rdb3.dts | 4 + > 5 files changed, 318 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > index fa054bfe7d5c..7be430b78c83 100644 > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > @@ -162,6 +162,159 @@ jtag-grp4 { > slew-rate = <166>; > }; > }; > + > + pinctrl_usdhc0: usdhc0grp-pins { > + usdhc0-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <150>; > + }; > + > + usdhc0-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <150>; > + }; > + > + usdhc0-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > + > + pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { > + usdhc0-100mhz-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > + > + pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { > + usdhc0-200mhz-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > }; > > uart0: serial@401c8000 { > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > index dbe498798bd9..7ab917f547ef 100644 > --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > @@ -34,6 +34,10 @@ &uart0 { > }; > > &usdhc0 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc0>; > + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; > disable-wp; > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > index ab1e5caaeae7..8739f63771bc 100644 > --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > @@ -40,6 +40,10 @@ &uart1 { > }; > > &usdhc0 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc0>; > + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; > disable-wp; > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi > index b4226a9143c8..6c572ffe37ca 100644 > --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi > @@ -219,6 +219,159 @@ jtag-grp4 { > slew-rate = <166>; > }; > }; > + > + pinctrl_usdhc0: usdhc0grp-pins { > + usdhc0-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <150>; > + }; > + > + usdhc0-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <150>; > + }; > + > + usdhc0-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > + > + pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { > + usdhc0-100mhz-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > + > + pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { > + usdhc0-200mhz-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > }; > > uart0: serial@401c8000 { > diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts > index 176e5af191c8..828e353455b5 100644 > --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts > +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts > @@ -40,6 +40,10 @@ &uart1 { > }; > > &usdhc0 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc0>; > + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; > bus-width = <8>; > disable-wp; > status = "okay"; ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux 2024-08-30 11:33 ` [PATCH v2 1/2] arm64: dts: s32g: Add " Ciprian Costea 2024-09-06 15:53 ` Matthias Brugger @ 2024-09-17 17:44 ` Krzysztof Kozlowski 2024-09-18 9:58 ` Ciprian Marian Costea 1 sibling, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2024-09-17 17:44 UTC (permalink / raw) To: Ciprian Costea, Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree, linux-kernel, NXP S32 Linux Team, Radu Pirea On 30/08/2024 13:33, Ciprian Costea wrote: > From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > > Adding 100mhz & 200mhz pinmux support for uSDHC helps to enable > higher speed modes for SD (SDR50, DDR50, SDR104) and > eMMC (such as HS200, HS400/HS400ES). > > Signed-off-by: Radu Pirea <radu-nicolae.pirea@nxp.com> > Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > --- > arch/arm64/boot/dts/freescale/s32g2.dtsi | 153 ++++++++++++++++++ > .../arm64/boot/dts/freescale/s32g274a-evb.dts | 4 + > .../boot/dts/freescale/s32g274a-rdb2.dts | 4 + > arch/arm64/boot/dts/freescale/s32g3.dtsi | 153 ++++++++++++++++++ > .../boot/dts/freescale/s32g399a-rdb3.dts | 4 + > 5 files changed, 318 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > index fa054bfe7d5c..7be430b78c83 100644 > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > @@ -162,6 +162,159 @@ jtag-grp4 { > slew-rate = <166>; > }; > }; > + > + pinctrl_usdhc0: usdhc0grp-pins { > + usdhc0-grp0 { Are you sure that this passes dtbs_check W=1? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux 2024-09-17 17:44 ` Krzysztof Kozlowski @ 2024-09-18 9:58 ` Ciprian Marian Costea 0 siblings, 0 replies; 8+ messages in thread From: Ciprian Marian Costea @ 2024-09-18 9:58 UTC (permalink / raw) To: Krzysztof Kozlowski, Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree, linux-kernel, NXP S32 Linux Team, Radu Pirea On 9/17/2024 8:44 PM, Krzysztof Kozlowski wrote: > On 30/08/2024 13:33, Ciprian Costea wrote: >> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> >> >> Adding 100mhz & 200mhz pinmux support for uSDHC helps to enable >> higher speed modes for SD (SDR50, DDR50, SDR104) and >> eMMC (such as HS200, HS400/HS400ES). >> >> Signed-off-by: Radu Pirea <radu-nicolae.pirea@nxp.com> >> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> >> --- >> arch/arm64/boot/dts/freescale/s32g2.dtsi | 153 ++++++++++++++++++ >> .../arm64/boot/dts/freescale/s32g274a-evb.dts | 4 + >> .../boot/dts/freescale/s32g274a-rdb2.dts | 4 + >> arch/arm64/boot/dts/freescale/s32g3.dtsi | 153 ++++++++++++++++++ >> .../boot/dts/freescale/s32g399a-rdb3.dts | 4 + >> 5 files changed, 318 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi >> index fa054bfe7d5c..7be430b78c83 100644 >> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi >> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi >> @@ -162,6 +162,159 @@ jtag-grp4 { >> slew-rate = <166>; >> }; >> }; >> + >> + pinctrl_usdhc0: usdhc0grp-pins { >> + usdhc0-grp0 { > > Are you sure that this passes dtbs_check W=1? > > Best regards, > Krzysztof > Hello Krzysztof, I've checked as follows: $ make ARCH=arm64 CHECK_DTBS=y W=1 freescale/s32g274a-evb.dtb freescale/s32g274a-rdb2.dtb freescale/s32g399a-rdb3.dtb DTC [C] arch/arm64/boot/dts/freescale/s32g274a-evb.dtb DTC [C] arch/arm64/boot/dts/freescale/s32g274a-rdb2.dtb DTC [C] arch/arm64/boot/dts/freescale/s32g399a-rdb3.dtb Best Regards, Ciprian ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] arm64: dts: s32g2: Disable support for SD/eMMC UHS mode 2024-08-30 11:33 [PATCH v2 0/2] add S32G2/S32G3 uSDHC pinmux Ciprian Costea 2024-08-30 11:33 ` [PATCH v2 1/2] arm64: dts: s32g: Add " Ciprian Costea @ 2024-08-30 11:33 ` Ciprian Costea 2024-09-06 15:53 ` Matthias Brugger 2024-10-08 9:25 ` [PATCH v2 0/2] add S32G2/S32G3 uSDHC pinmux Shawn Guo 2 siblings, 1 reply; 8+ messages in thread From: Ciprian Costea @ 2024-08-30 11:33 UTC (permalink / raw) To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree, linux-kernel, NXP S32 Linux Team, Ciprian Marian Costea From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Disable SD/eMMC UHS modes for NXP boards which do not set VCCQ voltage supply to 1.8V by default, such as S32G274A-EVB and S32G274A-RDB2. Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> --- arch/arm64/boot/dts/freescale/s32g274a-evb.dts | 1 + arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts index 7ab917f547ef..b9a119eea2b7 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts @@ -39,5 +39,6 @@ &usdhc0 { pinctrl-1 = <&pinctrl_usdhc0_100mhz>; pinctrl-2 = <&pinctrl_usdhc0_200mhz>; disable-wp; + no-1-8-v; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index 8739f63771bc..aaa61a8ad0da 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -45,5 +45,14 @@ &usdhc0 { pinctrl-1 = <&pinctrl_usdhc0_100mhz>; pinctrl-2 = <&pinctrl_usdhc0_200mhz>; disable-wp; + /* Remove no-1-8-v to enable higher speed modes for SD card. + * However, this is not enough to enable HS400 or HS200 modes for eMMC. + * In this case, the position of the resistor R797 must be changed + * from A to B before removing the property. + * If the property is removed without changing the resistor position, + * HS*00 may be enabled, but the interface might be unstable because of + * the wrong VCCQ voltage applied to the eMMC. + */ + no-1-8-v; status = "okay"; }; -- 2.45.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: s32g2: Disable support for SD/eMMC UHS mode 2024-08-30 11:33 ` [PATCH v2 2/2] arm64: dts: s32g2: Disable support for SD/eMMC UHS mode Ciprian Costea @ 2024-09-06 15:53 ` Matthias Brugger 0 siblings, 0 replies; 8+ messages in thread From: Matthias Brugger @ 2024-09-06 15:53 UTC (permalink / raw) To: Ciprian Costea, Chester Lin, Ghennadi Procopciuc, Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree, linux-kernel, NXP S32 Linux Team On 30/08/2024 13:33, Ciprian Costea wrote: > From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > > Disable SD/eMMC UHS modes for NXP boards which do not set VCCQ voltage > supply to 1.8V by default, such as S32G274A-EVB and S32G274A-RDB2. > > Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > arch/arm64/boot/dts/freescale/s32g274a-evb.dts | 1 + > arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 9 +++++++++ > 2 files changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > index 7ab917f547ef..b9a119eea2b7 100644 > --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > @@ -39,5 +39,6 @@ &usdhc0 { > pinctrl-1 = <&pinctrl_usdhc0_100mhz>; > pinctrl-2 = <&pinctrl_usdhc0_200mhz>; > disable-wp; > + no-1-8-v; > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > index 8739f63771bc..aaa61a8ad0da 100644 > --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > @@ -45,5 +45,14 @@ &usdhc0 { > pinctrl-1 = <&pinctrl_usdhc0_100mhz>; > pinctrl-2 = <&pinctrl_usdhc0_200mhz>; > disable-wp; > + /* Remove no-1-8-v to enable higher speed modes for SD card. > + * However, this is not enough to enable HS400 or HS200 modes for eMMC. > + * In this case, the position of the resistor R797 must be changed > + * from A to B before removing the property. > + * If the property is removed without changing the resistor position, > + * HS*00 may be enabled, but the interface might be unstable because of > + * the wrong VCCQ voltage applied to the eMMC. > + */ > + no-1-8-v; > status = "okay"; > }; ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/2] add S32G2/S32G3 uSDHC pinmux 2024-08-30 11:33 [PATCH v2 0/2] add S32G2/S32G3 uSDHC pinmux Ciprian Costea 2024-08-30 11:33 ` [PATCH v2 1/2] arm64: dts: s32g: Add " Ciprian Costea 2024-08-30 11:33 ` [PATCH v2 2/2] arm64: dts: s32g2: Disable support for SD/eMMC UHS mode Ciprian Costea @ 2024-10-08 9:25 ` Shawn Guo 2 siblings, 0 replies; 8+ messages in thread From: Shawn Guo @ 2024-10-08 9:25 UTC (permalink / raw) To: Ciprian Costea Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree, linux-kernel, NXP S32 Linux Team On Fri, Aug 30, 2024 at 02:33:45PM +0300, Ciprian Costea wrote: > From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > > This patchset adds 100mhz & 200mhz pinmux support for uSDHC. > Hence, UHS modes would be supported on NXP boards which enable > usage of VCCQ voltage supply @1.8V by default, with no additional > hardware (board) changes required, such as S32G399A-RDB3. > > Changes in V2: > - Added patch for disablement of UHS modes for NXP boards > where VCCQ voltage supply is set to 3.3V by default. > - Fixed S32G2, S32G3 dtb checks warnings related to uSDHC > pinmux renaming. > > Ciprian Marian Costea (2): > arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux > arm64: dts: s32g2: Disable support for SD/eMMC UHS mode Applied both, thanks! ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-10-08 9:25 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-08-30 11:33 [PATCH v2 0/2] add S32G2/S32G3 uSDHC pinmux Ciprian Costea 2024-08-30 11:33 ` [PATCH v2 1/2] arm64: dts: s32g: Add " Ciprian Costea 2024-09-06 15:53 ` Matthias Brugger 2024-09-17 17:44 ` Krzysztof Kozlowski 2024-09-18 9:58 ` Ciprian Marian Costea 2024-08-30 11:33 ` [PATCH v2 2/2] arm64: dts: s32g2: Disable support for SD/eMMC UHS mode Ciprian Costea 2024-09-06 15:53 ` Matthias Brugger 2024-10-08 9:25 ` [PATCH v2 0/2] add S32G2/S32G3 uSDHC pinmux Shawn Guo
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