From: Charlie Jenkins <charlie@rivosinc.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Catalin Marinas <catalin.marinas@arm.com>,
linux-kernel@vger.kernel.org, Anup Patel <anup@brainfault.org>,
Conor Dooley <conor@kernel.org>,
kasan-dev@googlegroups.com, Atish Patra <atishp@atishpatra.org>,
Evgenii Stepanov <eugenis@google.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
"Kirill A . Shutemov" <kirill.shutemov@linux.intel.com>
Subject: Re: [PATCH v4 06/10] riscv: Allow ptrace control of the tagged address ABI
Date: Wed, 16 Oct 2024 17:58:00 -0700 [thread overview]
Message-ID: <ZxBhGJ0-hir0gFor@ghost> (raw)
In-Reply-To: <2e25597c-6278-4bc6-a0c2-3826841c2ac0@sifive.com>
On Wed, Oct 16, 2024 at 12:50:32PM -0500, Samuel Holland wrote:
> Hi Charlie,
>
> On 2024-09-12 9:51 PM, Charlie Jenkins wrote:
> > On Wed, Aug 28, 2024 at 06:01:28PM -0700, Samuel Holland wrote:
> >> This allows a tracer to control the ABI of the tracee, as on arm64.
> >>
> >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> >> ---
> >
> > Since this code is identical to the arm64 port, could it be extracted
> > out into the generic ptrace.c and ifdef on either CONFIG_RISCV_ISA_SUPM
> > or CONFIG_ARM64_TAGGED_ADDR_ABI by adding some generic flag like
> > CONFIG_HAVE_ARCH_TAGGED_ADDR_ABI?
>
> Yes, it could be factored out, though I don't know if it is worth the overhead
> for these two trivial functions. I don't see any other code like this outside of
> arch/.
In my ideal world there is just a generic header somewhere so the only
"overhead" is creating the generic header. But I will defer to you on
whether it is worthwhile.
- Charlie
>
> Regards,
> Samuel
>
> >>
> >> (no changes since v1)
> >>
> >> arch/riscv/kernel/ptrace.c | 42 ++++++++++++++++++++++++++++++++++++++
> >> include/uapi/linux/elf.h | 1 +
> >> 2 files changed, 43 insertions(+)
> >>
> >> diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
> >> index 92731ff8c79a..ea67e9fb7a58 100644
> >> --- a/arch/riscv/kernel/ptrace.c
> >> +++ b/arch/riscv/kernel/ptrace.c
> >> @@ -28,6 +28,9 @@ enum riscv_regset {
> >> #ifdef CONFIG_RISCV_ISA_V
> >> REGSET_V,
> >> #endif
> >> +#ifdef CONFIG_RISCV_ISA_SUPM
> >> + REGSET_TAGGED_ADDR_CTRL,
> >> +#endif
> >> };
> >>
> >> static int riscv_gpr_get(struct task_struct *target,
> >> @@ -152,6 +155,35 @@ static int riscv_vr_set(struct task_struct *target,
> >> }
> >> #endif
> >>
> >> +#ifdef CONFIG_RISCV_ISA_SUPM
> >> +static int tagged_addr_ctrl_get(struct task_struct *target,
> >> + const struct user_regset *regset,
> >> + struct membuf to)
> >> +{
> >> + long ctrl = get_tagged_addr_ctrl(target);
> >> +
> >> + if (IS_ERR_VALUE(ctrl))
> >> + return ctrl;
> >> +
> >> + return membuf_write(&to, &ctrl, sizeof(ctrl));
> >> +}
> >> +
> >> +static int tagged_addr_ctrl_set(struct task_struct *target,
> >> + const struct user_regset *regset,
> >> + unsigned int pos, unsigned int count,
> >> + const void *kbuf, const void __user *ubuf)
> >> +{
> >> + int ret;
> >> + long ctrl;
> >> +
> >> + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + return set_tagged_addr_ctrl(target, ctrl);
> >> +}
> >> +#endif
> >> +
> >> static const struct user_regset riscv_user_regset[] = {
> >> [REGSET_X] = {
> >> .core_note_type = NT_PRSTATUS,
> >> @@ -182,6 +214,16 @@ static const struct user_regset riscv_user_regset[] = {
> >> .set = riscv_vr_set,
> >> },
> >> #endif
> >> +#ifdef CONFIG_RISCV_ISA_SUPM
> >> + [REGSET_TAGGED_ADDR_CTRL] = {
> >> + .core_note_type = NT_RISCV_TAGGED_ADDR_CTRL,
> >> + .n = 1,
> >> + .size = sizeof(long),
> >> + .align = sizeof(long),
> >> + .regset_get = tagged_addr_ctrl_get,
> >> + .set = tagged_addr_ctrl_set,
> >> + },
> >> +#endif
> >> };
> >>
> >> static const struct user_regset_view riscv_user_native_view = {
> >> diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
> >> index b54b313bcf07..9a32532d7264 100644
> >> --- a/include/uapi/linux/elf.h
> >> +++ b/include/uapi/linux/elf.h
> >> @@ -448,6 +448,7 @@ typedef struct elf64_shdr {
> >> #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */
> >> #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
> >> #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
> >> +#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */
> >> #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
> >> #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */
> >> #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */
> >> --
> >> 2.45.1
> >>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Catalin Marinas <catalin.marinas@arm.com>,
linux-kernel@vger.kernel.org, Anup Patel <anup@brainfault.org>,
Conor Dooley <conor@kernel.org>,
kasan-dev@googlegroups.com, Atish Patra <atishp@atishpatra.org>,
Evgenii Stepanov <eugenis@google.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
"Kirill A . Shutemov" <kirill.shutemov@linux.intel.com>
Subject: Re: [PATCH v4 06/10] riscv: Allow ptrace control of the tagged address ABI
Date: Wed, 16 Oct 2024 17:58:00 -0700 [thread overview]
Message-ID: <ZxBhGJ0-hir0gFor@ghost> (raw)
In-Reply-To: <2e25597c-6278-4bc6-a0c2-3826841c2ac0@sifive.com>
On Wed, Oct 16, 2024 at 12:50:32PM -0500, Samuel Holland wrote:
> Hi Charlie,
>
> On 2024-09-12 9:51 PM, Charlie Jenkins wrote:
> > On Wed, Aug 28, 2024 at 06:01:28PM -0700, Samuel Holland wrote:
> >> This allows a tracer to control the ABI of the tracee, as on arm64.
> >>
> >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> >> ---
> >
> > Since this code is identical to the arm64 port, could it be extracted
> > out into the generic ptrace.c and ifdef on either CONFIG_RISCV_ISA_SUPM
> > or CONFIG_ARM64_TAGGED_ADDR_ABI by adding some generic flag like
> > CONFIG_HAVE_ARCH_TAGGED_ADDR_ABI?
>
> Yes, it could be factored out, though I don't know if it is worth the overhead
> for these two trivial functions. I don't see any other code like this outside of
> arch/.
In my ideal world there is just a generic header somewhere so the only
"overhead" is creating the generic header. But I will defer to you on
whether it is worthwhile.
- Charlie
>
> Regards,
> Samuel
>
> >>
> >> (no changes since v1)
> >>
> >> arch/riscv/kernel/ptrace.c | 42 ++++++++++++++++++++++++++++++++++++++
> >> include/uapi/linux/elf.h | 1 +
> >> 2 files changed, 43 insertions(+)
> >>
> >> diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
> >> index 92731ff8c79a..ea67e9fb7a58 100644
> >> --- a/arch/riscv/kernel/ptrace.c
> >> +++ b/arch/riscv/kernel/ptrace.c
> >> @@ -28,6 +28,9 @@ enum riscv_regset {
> >> #ifdef CONFIG_RISCV_ISA_V
> >> REGSET_V,
> >> #endif
> >> +#ifdef CONFIG_RISCV_ISA_SUPM
> >> + REGSET_TAGGED_ADDR_CTRL,
> >> +#endif
> >> };
> >>
> >> static int riscv_gpr_get(struct task_struct *target,
> >> @@ -152,6 +155,35 @@ static int riscv_vr_set(struct task_struct *target,
> >> }
> >> #endif
> >>
> >> +#ifdef CONFIG_RISCV_ISA_SUPM
> >> +static int tagged_addr_ctrl_get(struct task_struct *target,
> >> + const struct user_regset *regset,
> >> + struct membuf to)
> >> +{
> >> + long ctrl = get_tagged_addr_ctrl(target);
> >> +
> >> + if (IS_ERR_VALUE(ctrl))
> >> + return ctrl;
> >> +
> >> + return membuf_write(&to, &ctrl, sizeof(ctrl));
> >> +}
> >> +
> >> +static int tagged_addr_ctrl_set(struct task_struct *target,
> >> + const struct user_regset *regset,
> >> + unsigned int pos, unsigned int count,
> >> + const void *kbuf, const void __user *ubuf)
> >> +{
> >> + int ret;
> >> + long ctrl;
> >> +
> >> + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + return set_tagged_addr_ctrl(target, ctrl);
> >> +}
> >> +#endif
> >> +
> >> static const struct user_regset riscv_user_regset[] = {
> >> [REGSET_X] = {
> >> .core_note_type = NT_PRSTATUS,
> >> @@ -182,6 +214,16 @@ static const struct user_regset riscv_user_regset[] = {
> >> .set = riscv_vr_set,
> >> },
> >> #endif
> >> +#ifdef CONFIG_RISCV_ISA_SUPM
> >> + [REGSET_TAGGED_ADDR_CTRL] = {
> >> + .core_note_type = NT_RISCV_TAGGED_ADDR_CTRL,
> >> + .n = 1,
> >> + .size = sizeof(long),
> >> + .align = sizeof(long),
> >> + .regset_get = tagged_addr_ctrl_get,
> >> + .set = tagged_addr_ctrl_set,
> >> + },
> >> +#endif
> >> };
> >>
> >> static const struct user_regset_view riscv_user_native_view = {
> >> diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
> >> index b54b313bcf07..9a32532d7264 100644
> >> --- a/include/uapi/linux/elf.h
> >> +++ b/include/uapi/linux/elf.h
> >> @@ -448,6 +448,7 @@ typedef struct elf64_shdr {
> >> #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */
> >> #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
> >> #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
> >> +#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */
> >> #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
> >> #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */
> >> #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */
> >> --
> >> 2.45.1
> >>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
next prev parent reply other threads:[~2024-10-17 2:31 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-29 1:01 [PATCH v4 00/10] riscv: Userspace pointer masking and tagged address ABI Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-08-29 1:01 ` [PATCH v4 01/10] dt-bindings: riscv: Add pointer masking ISA extensions Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-09-13 1:08 ` Charlie Jenkins
2024-09-13 1:08 ` Charlie Jenkins
2024-08-29 1:01 ` [PATCH v4 02/10] riscv: Add ISA extension parsing for pointer masking Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-09-13 1:09 ` Charlie Jenkins
2024-09-13 1:09 ` Charlie Jenkins
2024-08-29 1:01 ` [PATCH v4 03/10] riscv: Add CSR definitions " Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-09-13 1:16 ` Charlie Jenkins
2024-09-13 1:16 ` Charlie Jenkins
2024-08-29 1:01 ` [PATCH v4 04/10] riscv: Add support for userspace " Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-09-13 1:52 ` Charlie Jenkins
2024-09-13 1:52 ` Charlie Jenkins
2024-08-29 1:01 ` [PATCH v4 05/10] riscv: Add support for the tagged address ABI Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-09-13 2:45 ` Charlie Jenkins
2024-09-13 2:45 ` Charlie Jenkins
2024-09-14 2:57 ` Samuel Holland
2024-09-14 2:57 ` Samuel Holland
2024-09-14 3:16 ` Charlie Jenkins
2024-09-14 3:16 ` Charlie Jenkins
2024-08-29 1:01 ` [PATCH v4 06/10] riscv: Allow ptrace control of " Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-09-13 2:51 ` Charlie Jenkins
2024-09-13 2:51 ` Charlie Jenkins
2024-10-16 17:50 ` Samuel Holland
2024-10-16 17:50 ` Samuel Holland
2024-10-17 0:58 ` Charlie Jenkins [this message]
2024-10-17 0:58 ` Charlie Jenkins
2024-08-29 1:01 ` [PATCH v4 07/10] selftests: riscv: Add a pointer masking test Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-09-13 2:54 ` Charlie Jenkins
2024-09-13 2:54 ` Charlie Jenkins
2024-08-29 1:01 ` [PATCH v4 08/10] riscv: hwprobe: Export the Supm ISA extension Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-08-29 1:01 ` [PATCH v4 09/10] RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-09-04 12:17 ` Anup Patel
2024-09-04 12:17 ` Anup Patel
2024-09-04 14:31 ` Samuel Holland
2024-09-04 14:31 ` Samuel Holland
2024-09-04 14:31 ` Samuel Holland
2024-09-04 14:45 ` Anup Patel
2024-09-04 14:45 ` Anup Patel
2024-09-04 14:45 ` Anup Patel
2024-09-04 14:57 ` Samuel Holland
2024-09-04 14:57 ` Samuel Holland
2024-09-04 14:57 ` Samuel Holland
2024-09-04 15:20 ` Anup Patel
2024-09-04 15:20 ` Anup Patel
2024-09-04 15:20 ` Anup Patel
2024-09-04 15:55 ` Samuel Holland
2024-09-04 15:55 ` Samuel Holland
2024-09-04 15:55 ` Samuel Holland
2024-09-05 5:18 ` Anup Patel
2024-09-05 5:18 ` Anup Patel
2024-09-05 5:18 ` Anup Patel
2024-09-14 2:52 ` Samuel Holland
2024-09-14 2:52 ` Samuel Holland
2024-09-14 2:52 ` Samuel Holland
2024-08-29 1:01 ` [PATCH v4 10/10] KVM: riscv: selftests: Add Smnpm and Ssnpm to get-reg-list test Samuel Holland
2024-08-29 1:01 ` Samuel Holland
2024-09-04 12:22 ` Anup Patel
2024-09-04 12:22 ` Anup Patel
2024-09-04 12:32 ` [PATCH v4 00/10] riscv: Userspace pointer masking and tagged address ABI Anup Patel
2024-09-04 12:32 ` Anup Patel
2024-09-13 18:08 ` Charlie Jenkins
2024-09-13 18:08 ` Charlie Jenkins
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