From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Anton Johansson" <anjo@rev.ng>,
"Jason Wang" <jasowang@redhat.com>,
qemu-arm@nongnu.org,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Thomas Huth" <thuth@redhat.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Gustavo Romero" <gustavo.romero@linaro.org>
Subject: Re: [PATCH 04/20] hw/net/xilinx_ethlite: Update QOM style
Date: Wed, 13 Nov 2024 16:12:09 +0100 [thread overview]
Message-ID: <ZzTByV5P4oDBAZVO@zapote> (raw)
In-Reply-To: <20241112181044.92193-5-philmd@linaro.org>
On Tue, Nov 12, 2024 at 07:10:28PM +0100, Philippe Mathieu-Daudé wrote:
> Use XlnxXpsEthLite typedef, OBJECT_DECLARE_SIMPLE_TYPE macro;
> convert type_init() to DEFINE_TYPES().
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
> ---
> hw/net/xilinx_ethlite.c | 48 +++++++++++++++++++----------------------
> 1 file changed, 22 insertions(+), 26 deletions(-)
>
> diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
> index 2b52597f03..0f59811c78 100644
> --- a/hw/net/xilinx_ethlite.c
> +++ b/hw/net/xilinx_ethlite.c
> @@ -53,10 +53,9 @@
> #define CTRL_S 0x1
>
> #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
> -DECLARE_INSTANCE_CHECKER(struct xlx_ethlite, XILINX_ETHLITE,
> - TYPE_XILINX_ETHLITE)
> +OBJECT_DECLARE_SIMPLE_TYPE(XlnxXpsEthLite, XILINX_ETHLITE)
>
> -struct xlx_ethlite
> +struct XlnxXpsEthLite
> {
> SysBusDevice parent_obj;
>
> @@ -73,7 +72,7 @@ struct xlx_ethlite
> uint32_t regs[R_MAX];
> };
>
> -static inline void eth_pulse_irq(struct xlx_ethlite *s)
> +static inline void eth_pulse_irq(XlnxXpsEthLite *s)
> {
> /* Only the first gie reg is active. */
> if (s->regs[R_TX_GIE0] & GIE_GIE) {
> @@ -84,7 +83,7 @@ static inline void eth_pulse_irq(struct xlx_ethlite *s)
> static uint64_t
> eth_read(void *opaque, hwaddr addr, unsigned int size)
> {
> - struct xlx_ethlite *s = opaque;
> + XlnxXpsEthLite *s = opaque;
> uint32_t r = 0;
>
> addr >>= 2;
> @@ -112,7 +111,7 @@ static void
> eth_write(void *opaque, hwaddr addr,
> uint64_t val64, unsigned int size)
> {
> - struct xlx_ethlite *s = opaque;
> + XlnxXpsEthLite *s = opaque;
> unsigned int base = 0;
> uint32_t value = val64;
>
> @@ -176,7 +175,7 @@ static const MemoryRegionOps eth_ops = {
>
> static bool eth_can_rx(NetClientState *nc)
> {
> - struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
> + XlnxXpsEthLite *s = qemu_get_nic_opaque(nc);
> unsigned int rxbase = s->rxbuf * (0x800 / 4);
>
> return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
> @@ -184,7 +183,7 @@ static bool eth_can_rx(NetClientState *nc)
>
> static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
> {
> - struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
> + XlnxXpsEthLite *s = qemu_get_nic_opaque(nc);
> unsigned int rxbase = s->rxbuf * (0x800 / 4);
>
> /* DA filter. */
> @@ -214,7 +213,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
>
> static void xilinx_ethlite_reset(DeviceState *dev)
> {
> - struct xlx_ethlite *s = XILINX_ETHLITE(dev);
> + XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
>
> s->rxbuf = 0;
> }
> @@ -228,7 +227,7 @@ static NetClientInfo net_xilinx_ethlite_info = {
>
> static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
> {
> - struct xlx_ethlite *s = XILINX_ETHLITE(dev);
> + XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
>
> qemu_macaddr_default_if_unset(&s->conf.macaddr);
> s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
> @@ -239,7 +238,7 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
>
> static void xilinx_ethlite_init(Object *obj)
> {
> - struct xlx_ethlite *s = XILINX_ETHLITE(obj);
> + XlnxXpsEthLite *s = XILINX_ETHLITE(obj);
>
> sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
>
> @@ -249,9 +248,9 @@ static void xilinx_ethlite_init(Object *obj)
> }
>
> static Property xilinx_ethlite_properties[] = {
> - DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
> - DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
> - DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
> + DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1),
> + DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1),
> + DEFINE_NIC_PROPERTIES(XlnxXpsEthLite, conf),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -264,17 +263,14 @@ static void xilinx_ethlite_class_init(ObjectClass *klass, void *data)
> device_class_set_props(dc, xilinx_ethlite_properties);
> }
>
> -static const TypeInfo xilinx_ethlite_info = {
> - .name = TYPE_XILINX_ETHLITE,
> - .parent = TYPE_SYS_BUS_DEVICE,
> - .instance_size = sizeof(struct xlx_ethlite),
> - .instance_init = xilinx_ethlite_init,
> - .class_init = xilinx_ethlite_class_init,
> +static const TypeInfo xilinx_ethlite_types[] = {
> + {
> + .name = TYPE_XILINX_ETHLITE,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(XlnxXpsEthLite),
> + .instance_init = xilinx_ethlite_init,
> + .class_init = xilinx_ethlite_class_init,
> + },
> };
>
> -static void xilinx_ethlite_register_types(void)
> -{
> - type_register_static(&xilinx_ethlite_info);
> -}
> -
> -type_init(xilinx_ethlite_register_types)
> +DEFINE_TYPES(xilinx_ethlite_types)
> --
> 2.45.2
>
next prev parent reply other threads:[~2024-11-13 15:12 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-12 18:10 [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 01/20] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 02/20] hw/net/xilinx_ethlite: Convert some debug logs to trace events Philippe Mathieu-Daudé
2024-11-13 15:11 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 03/20] hw/net/xilinx_ethlite: Remove unuseful debug logs Philippe Mathieu-Daudé
2024-11-13 15:11 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 04/20] hw/net/xilinx_ethlite: Update QOM style Philippe Mathieu-Daudé
2024-11-13 15:12 ` Edgar E. Iglesias [this message]
2024-11-12 18:10 ` [PATCH 05/20] hw/net/xilinx_ethlite: Correct maximum RX buffer size Philippe Mathieu-Daudé
2024-11-13 15:15 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 06/20] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented) Philippe Mathieu-Daudé
2024-11-13 15:16 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 07/20] hw/net/xilinx_ethlite: Rename rxbuf -> port_index Philippe Mathieu-Daudé
2024-11-13 15:20 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 08/20] hw/net/xilinx_ethlite: Add addr_to_port_index() helper Philippe Mathieu-Daudé
2024-11-13 15:23 ` Edgar E. Iglesias
2024-11-14 19:04 ` Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 09/20] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-13 15:26 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 10/20] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-13 15:26 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 11/20] hw/net/xilinx_ethlite: Access RX_CTRL register for each port Philippe Mathieu-Daudé
2024-11-13 15:27 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 12/20] hw/net/xilinx_ethlite: Access TX_GIE " Philippe Mathieu-Daudé
2024-11-13 15:28 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 13/20] hw/net/xilinx_ethlite: Access TX_LEN " Philippe Mathieu-Daudé
2024-11-13 15:28 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 14/20] hw/net/xilinx_ethlite: Access TX_CTRL " Philippe Mathieu-Daudé
2024-11-13 15:28 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 15/20] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO Philippe Mathieu-Daudé
2024-11-13 15:29 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 16/20] hw/net/xilinx_ethlite: Map TX_LEN " Philippe Mathieu-Daudé
2024-11-13 15:30 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 17/20] hw/net/xilinx_ethlite: Map TX_GIE " Philippe Mathieu-Daudé
2024-11-13 15:34 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 18/20] hw/net/xilinx_ethlite: Map TX_CTRL " Philippe Mathieu-Daudé
2024-11-13 15:34 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 19/20] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region Philippe Mathieu-Daudé
2024-11-13 15:35 ` Edgar E. Iglesias
2024-11-13 18:21 ` Paolo Bonzini
2024-11-13 19:37 ` Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 20/20] hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container' Philippe Mathieu-Daudé
2024-11-13 15:35 ` Edgar E. Iglesias
2024-11-13 15:36 ` [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Edgar E. Iglesias
2024-11-14 18:55 ` Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZzTByV5P4oDBAZVO@zapote \
--to=edgar.iglesias@gmail.com \
--cc=alistair@alistair23.me \
--cc=anjo@rev.ng \
--cc=gustavo.romero@linaro.org \
--cc=jasowang@redhat.com \
--cc=marcandre.lureau@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=thuth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.