Re: [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

On Tue, Nov 12, 2024 at 07:10:24PM +0100, Philippe Mathieu-Daudé wrote:
> This is the result of a long discussion with Edgar (started few
> years ago!) and Paolo:
> https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f6814b5@redhat.com/
> After clarification from Richard on MMIO/RAM accesses, I figured
> strengthening the model regions would make things obvious,
> eventually allowing to remove the tswap() calls for good.
> 
> This costly series mostly plays around with MemoryRegions.
> 
> The model has a mix of RAM/MMIO in its address range. Currently
> they are implemented as a MMIO array of u32. Since the core
> memory layer swaps accesses for MMIO, the device implementation
> has to swap them back.
> In order to avoid that, we'll map the RAM regions as RAM MRs.
> First we move each MMIO register to new MMIO regions (RX and TX).
> Then what is left are the RAM buffers; we convert them to RAM MRs,
> removing the need for tswap() at all.
> 
> Once reviewed, I'll respin my "hw/microblaze: Allow running
> cross-endian vCPUs" series based on this.


Thanks Phil,

This looks good to me. Have you tested this with the Images I provied
a while back or some other way?

Cheers,
Edgar




> 
> Please review,
> 
> Phil.
> 
> Philippe Mathieu-Daudé (20):
>   hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit
>   hw/net/xilinx_ethlite: Convert some debug logs to trace events
>   hw/net/xilinx_ethlite: Remove unuseful debug logs
>   hw/net/xilinx_ethlite: Update QOM style
>   hw/net/xilinx_ethlite: Correct maximum RX buffer size
>   hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented)
>   hw/net/xilinx_ethlite: Rename rxbuf -> port_index
>   hw/net/xilinx_ethlite: Add addr_to_port_index() helper
>   hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper
>   hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper
>   hw/net/xilinx_ethlite: Access RX_CTRL register for each port
>   hw/net/xilinx_ethlite: Access TX_GIE register for each port
>   hw/net/xilinx_ethlite: Access TX_LEN register for each port
>   hw/net/xilinx_ethlite: Access TX_CTRL register for each port
>   hw/net/xilinx_ethlite: Map RX_CTRL as MMIO
>   hw/net/xilinx_ethlite: Map TX_LEN as MMIO
>   hw/net/xilinx_ethlite: Map TX_GIE as MMIO
>   hw/net/xilinx_ethlite: Map TX_CTRL as MMIO
>   hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region
>   hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container'
> 
>  hw/char/xilinx_uartlite.c |   4 +
>  hw/intc/xilinx_intc.c     |   4 +
>  hw/net/xilinx_ethlite.c   | 357 ++++++++++++++++++++++++--------------
>  hw/timer/xilinx_timer.c   |   4 +
>  hw/net/trace-events       |   4 +
>  5 files changed, 246 insertions(+), 127 deletions(-)
> 
> -- 
> 2.45.2
>