From: Vineet Gupta <Vineet.Gupta1@synopsys.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
"linux-snps-arc@lists.infradead.org"
<linux-snps-arc@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Alexey Brodkin <Alexey.Brodkin@synopsys.com>,
Jason Baron <jbaron@akamai.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
"linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>
Subject: Re: [PATCH] ARC: ARCv2: jump label: implement jump label patching
Date: Thu, 20 Jun 2019 11:48:17 -0700 [thread overview]
Message-ID: <a0a1aa81-d46e-71db-ff7b-207bc468068d@synopsys.com> (raw)
In-Reply-To: <20190620070120.GU3402@hirez.programming.kicks-ass.net>
On 6/20/19 12:01 AM, Peter Zijlstra wrote:
>
> In particular we do not need the alignment.
>
> So what the x86 code does is:
>
> - overwrite the first byte of the instruction with a single byte trap
> instruction
>
> - machine wide IPI which synchronizes I$
>
> At this point, any CPU that encounters this instruction will trap; and
> the trap handler will emulate the 'new' instruction -- typically a jump.
>
> - overwrite the tail of the instruction (if there is a tail)
>
> - machine wide IPI which syncrhonizes I$
>
> At this point, nobody will execute the tail, because we'll still trap on
> that first single byte instruction, but if they were to read the
> instruction stream, the tail must be there.
>
> - overwrite the first byte of the instruction to now have a complete
> instruction.
>
> - machine wide IPI which syncrhonizes I$
>
> At this point, any CPU will encounter the new instruction as a whole,
> irrespective of alignment.
>
>
> So the benefit of this scheme is that is works irrespective of the
> instruction fetch window size and don't need the 'funny' alignment
> stuff.
>
> Now, I've no idea if something like this is feasible on ARC; for it to
> work you need that 2 byte trap instruction -- since all instructions are
> 2 byte aligned, you can always poke that without issue.
We do have a 2 byte TRAP_S u6 which is used for all/any trap'ing: syscalls,
software breakpoint, kprobes etc. But using it like x86 seems a bit excessive for
ARC. Given that x86 doesn't implement flush_icache_range() it must have I$
snooping D$ and also this machine wide IPI sync I$ must be totally under the hood
all hardware affair - unlike ARC which needs on_each_cpu( I$ line range).
Using TRAP_S would actually requires 2 passes (and 2 rounds of IPI) for code
patching - the last one to undo the TRAP_S itself.
I do worry about the occasional alignment induced extra NOP_S instruction (2 byte)
but there doesn't seem to be an easy solution. Heck if we could use the NOP_S /
B_S in first place. While not a clean solution by any standards, could anything be
done to reduce the code path of DO_ONCE() so that unlikely code is not too far off.
WARNING: multiple messages have this Message-ID (diff)
From: Vineet.Gupta1@synopsys.com (Vineet Gupta)
To: linux-snps-arc@lists.infradead.org
Subject: [PATCH] ARC: ARCv2: jump label: implement jump label patching
Date: Thu, 20 Jun 2019 11:48:17 -0700 [thread overview]
Message-ID: <a0a1aa81-d46e-71db-ff7b-207bc468068d@synopsys.com> (raw)
In-Reply-To: <20190620070120.GU3402@hirez.programming.kicks-ass.net>
On 6/20/19 12:01 AM, Peter Zijlstra wrote:
>
> In particular we do not need the alignment.
>
> So what the x86 code does is:
>
> - overwrite the first byte of the instruction with a single byte trap
> instruction
>
> - machine wide IPI which synchronizes I$
>
> At this point, any CPU that encounters this instruction will trap; and
> the trap handler will emulate the 'new' instruction -- typically a jump.
>
> - overwrite the tail of the instruction (if there is a tail)
>
> - machine wide IPI which syncrhonizes I$
>
> At this point, nobody will execute the tail, because we'll still trap on
> that first single byte instruction, but if they were to read the
> instruction stream, the tail must be there.
>
> - overwrite the first byte of the instruction to now have a complete
> instruction.
>
> - machine wide IPI which syncrhonizes I$
>
> At this point, any CPU will encounter the new instruction as a whole,
> irrespective of alignment.
>
>
> So the benefit of this scheme is that is works irrespective of the
> instruction fetch window size and don't need the 'funny' alignment
> stuff.
>
> Now, I've no idea if something like this is feasible on ARC; for it to
> work you need that 2 byte trap instruction -- since all instructions are
> 2 byte aligned, you can always poke that without issue.
We do have a 2 byte TRAP_S u6 which is used for all/any trap'ing: syscalls,
software breakpoint, kprobes etc. But using it like x86 seems a bit excessive for
ARC. Given that x86 doesn't implement flush_icache_range() it must have I$
snooping D$ and also this machine wide IPI sync I$ must be totally under the hood
all hardware affair - unlike ARC which needs on_each_cpu( I$ line range).
Using TRAP_S would actually requires 2 passes (and 2 rounds of IPI) for code
patching - the last one to undo the TRAP_S itself.
I do worry about the occasional alignment induced extra NOP_S instruction (2 byte)
but there doesn't seem to be an easy solution. Heck if we could use the NOP_S /
B_S in first place. While not a clean solution by any standards, could anything be
done to reduce the code path of DO_ONCE() so that unlikely code is not too far off.
next prev parent reply other threads:[~2019-06-20 18:48 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-14 16:40 [PATCH] ARC: ARCv2: jump label: implement jump label patching Eugeniy Paltsev
2019-06-14 16:40 ` Eugeniy Paltsev
2019-06-18 16:16 ` Vineet Gupta
2019-06-18 16:16 ` Vineet Gupta
2019-06-19 8:12 ` Peter Zijlstra
2019-06-19 8:12 ` Peter Zijlstra
2019-06-19 23:55 ` Vineet Gupta
2019-06-19 23:55 ` Vineet Gupta
2019-06-20 7:01 ` Peter Zijlstra
2019-06-20 7:01 ` Peter Zijlstra
2019-06-20 18:34 ` Eugeniy Paltsev
2019-06-20 18:34 ` Eugeniy Paltsev
2019-06-20 21:30 ` Peter Zijlstra
2019-06-20 21:30 ` Peter Zijlstra
2019-06-20 21:30 ` Peter Zijlstra
2019-06-20 18:48 ` Vineet Gupta [this message]
2019-06-20 18:48 ` Vineet Gupta
2019-06-20 21:22 ` Peter Zijlstra
2019-06-20 21:22 ` Peter Zijlstra
2019-06-21 12:09 ` Peter Zijlstra
2019-06-21 12:09 ` Peter Zijlstra
2019-06-21 12:09 ` Peter Zijlstra
2019-06-21 12:12 ` Peter Zijlstra
2019-06-21 12:12 ` Peter Zijlstra
2019-06-21 12:12 ` Peter Zijlstra
2019-06-21 18:37 ` Nadav Amit
2019-06-21 18:37 ` Nadav Amit
2019-06-20 7:15 ` Peter Zijlstra
2019-06-20 7:15 ` Peter Zijlstra
2019-06-20 7:15 ` Peter Zijlstra
2019-06-20 7:21 ` Peter Zijlstra
2019-06-20 7:21 ` Peter Zijlstra
2019-06-20 7:52 ` Peter Zijlstra
2019-06-20 7:52 ` Peter Zijlstra
2019-06-20 7:52 ` Peter Zijlstra
2019-06-20 20:49 ` Vineet Gupta
2019-06-20 20:49 ` Vineet Gupta
2019-06-21 15:39 ` Alexey Brodkin
2019-06-21 15:39 ` Alexey Brodkin
2019-06-20 18:34 ` Eugeniy Paltsev
2019-06-20 18:34 ` Eugeniy Paltsev
2019-06-20 21:12 ` Peter Zijlstra
2019-06-20 21:12 ` Peter Zijlstra
2019-06-28 22:59 ` Vineet Gupta
2019-06-28 22:59 ` Vineet Gupta
2019-07-03 16:15 ` Vineet Gupta
2019-07-03 16:15 ` Vineet Gupta
2019-07-17 15:09 ` Eugeniy Paltsev
2019-07-17 15:09 ` Eugeniy Paltsev
2019-07-17 17:45 ` Vineet Gupta
2019-07-17 17:45 ` Vineet Gupta
2019-07-17 18:54 ` Eugeniy Paltsev
2019-07-17 18:54 ` Eugeniy Paltsev
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