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From: Stefan Roese <sr@denx.de>
To: "Pali Rohár" <pali@kernel.org>
Cc: "Marek Behún" <marek.behun@nic.cz>, u-boot@lists.denx.de
Subject: Re: [PATCH 6/8] pci: pci_mvebu: Do not automatically enable bus mastering on PCI Bridge
Date: Tue, 2 Nov 2021 11:50:18 +0100	[thread overview]
Message-ID: <a8cf4cd3-da16-9200-e7e8-aff8e46a79aa@denx.de> (raw)
In-Reply-To: <20211022142215.26484-7-pali@kernel.org>

On 22.10.21 16:22, Pali Rohár wrote:
> Now that PCI Bridge is working, U-Boot's CONFIG_PCI_PNP code automatically
> enables memory access and bus mastering when it is needed. So do not
> prematurely enable memory access and bus mastering.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Reviewed-by: Marek Behún <marek.behun@nic.cz>

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

> ---
>   drivers/pci/pci_mvebu.c | 8 --------
>   1 file changed, 8 deletions(-)
> 
> diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
> index 40b8a57bbe1e..e43fa12d3819 100644
> --- a/drivers/pci/pci_mvebu.c
> +++ b/drivers/pci/pci_mvebu.c
> @@ -451,14 +451,6 @@ static int mvebu_pcie_probe(struct udevice *dev)
>   	/* Setup windows and configure host bridge */
>   	mvebu_pcie_setup_wins(pcie);
>   
> -	/* Master + slave enable. */
> -	reg = readl(pcie->base + PCIE_CMD_OFF);
> -	reg |= PCI_COMMAND_MEMORY;
> -	reg |= PCI_COMMAND_IO;
> -	reg |= PCI_COMMAND_MASTER;
> -	reg |= BIT(10);		/* disable interrupts */
> -	writel(reg, pcie->base + PCIE_CMD_OFF);
> -
>   	/* PCI memory space */
>   	pci_set_region(hose->regions + 0, pcie->mem.start,
>   		       pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
> 


Viele Grüße,
Stefan

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de

  reply	other threads:[~2021-11-02 10:50 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-22 14:22 [PATCH 0/8] pci: pci_mvebu: Fix access to config space and PCIe Root Port Pali Rohár
2021-10-22 14:22 ` [PATCH 1/8] pci: pci_mvebu: Fix write_config() with PCI_SIZE_8 or PCI_SIZE_16 Pali Rohár
2021-11-02 10:44   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 2/8] pci: pci_mvebu: Fix read_config() " Pali Rohár
2021-11-02 10:45   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 3/8] pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port) Pali Rohár
2021-11-02 10:47   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 4/8] pci: pci_mvebu: Remove unused functions Pali Rohár
2021-11-02 10:47   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 5/8] pci: pci_mvebu: Fix place of link up detection Pali Rohár
2021-11-02 10:50   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 6/8] pci: pci_mvebu: Do not automatically enable bus mastering on PCI Bridge Pali Rohár
2021-11-02 10:50   ` Stefan Roese [this message]
2021-10-22 14:22 ` [PATCH 7/8] pci: pci_mvebu: Setup PCI controller to Root Complex mode Pali Rohár
2021-11-02 10:50   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 8/8] pci: pci_mvebu: Fix comment about driver class name Pali Rohár
2021-11-02 10:50   ` Stefan Roese
2021-11-03  7:46 ` [PATCH 0/8] pci: pci_mvebu: Fix access to config space and PCIe Root Port Stefan Roese

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