Re: [PATCH bpf-next 3/8] bpf, riscv64: Support load-acquire and store-release instructions

[Peilin Ye <yepeilin@google.com>]

On Tue, May 06, 2025 at 10:20:04PM +0800, Pu Lehui wrote:
> On 2025/4/30 8:50, Peilin Ye wrote:
> > @@ -1259,7 +1318,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> >   {
> >   	bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 ||
> >   		    BPF_CLASS(insn->code) == BPF_JMP;
> > -	int s, e, rvoff, ret, i = insn - ctx->prog->insnsi;
> > +	int s, e, rvoff, ret = 0, i = insn - ctx->prog->insnsi;
> >   	struct bpf_prog_aux *aux = ctx->prog->aux;
> >   	u8 rd = -1, rs = -1, code = insn->code;
> >   	s16 off = insn->off;
> > @@ -1962,10 +2021,14 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> >   	case BPF_STX | BPF_MEM | BPF_DW:
> >   		emit_store_64(rd, off, rs, ctx);
> >   		break;
> > +	case BPF_STX | BPF_ATOMIC | BPF_B:
> > +	case BPF_STX | BPF_ATOMIC | BPF_H:
> >   	case BPF_STX | BPF_ATOMIC | BPF_W:
> >   	case BPF_STX | BPF_ATOMIC | BPF_DW:
> > -		emit_atomic(rd, rs, off, imm,
> > -			    BPF_SIZE(code) == BPF_DW, ctx);
> > +		if (bpf_atomic_is_load_store(insn))
> > +			ret = emit_atomic_ld_st(rd, rs, off, imm, code, ctx);
> > +		else
> > +			ret = emit_atomic_rmw(rd, rs, off, imm, code, ctx);
> >   		break;
> >   	case BPF_STX | BPF_PROBE_MEM32 | BPF_B:
> > @@ -2050,7 +2113,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> >   		return -EINVAL;
> >   	}
> > -	return 0;
> > +	return ret;
> 
> `ret` may be a value greater than zero, which will potentially cause
> build_body to skip the next instruction. Let's `return 0` here, and `return
> ret` if the above fails.

Sure, I'll change this in v2.

Thanks,
Peilin Ye