From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: "Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Jassi Brar" <jassisinghbrar@gmail.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Len Brown" <lenb@kernel.org>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Rahul Pathak" <rpathak@ventanamicro.com>,
"Leyfoon Tan" <leyfoon.tan@starfivetech.com>,
"Atish Patra" <atish.patra@linux.dev>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Anup Patel" <anup@brainfault.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 18/23] ACPI: RISC-V: Add support to update gsi range
Date: Mon, 12 May 2025 10:31:05 +0300 [thread overview]
Message-ID: <aCGjuc9AmZaKBGg5@smile.fi.intel.com> (raw)
In-Reply-To: <20250511133939.801777-19-apatel@ventanamicro.com>
On Sun, May 11, 2025 at 07:09:34PM +0530, Anup Patel wrote:
> From: Sunil V L <sunilvl@ventanamicro.com>
>
> Some RISC-V interrupt controllers like RPMI based system MSI interrupt
> controllers do not have MADT entry defined. These interrupt controllers
> exist only in the namespace. ACPI spec defines _GSB method to get the
> GSI base of the interrupt controller, However, there is no such standard
> method to get the GSI range. To support such interrupt controllers, set
> the GSI range of such interrupt controllers to non-overlapping range and
> provide API for interrupt controller driver to update it with proper
> value.
...
> +static inline int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs)
> +{
> + return -1;
Why not using the defined error code?
> +}
...
> +int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs)
> +{
> + struct riscv_ext_intc_list *ext_intc_element;
> +
> + list_for_each_entry(ext_intc_element, &ext_intc_list, list) {
> + if (gsi_base == ext_intc_element->gsi_base &&
> + (ext_intc_element->flag & RISCV_ACPI_INTC_FLAG_PENDING)) {
> + ext_intc_element->nr_irqs = nr_irqs;
> + ext_intc_element->flag &= ~RISCV_ACPI_INTC_FLAG_PENDING;
> + return 0;
> + }
> + }
> + return -1;
Ditto.
> +}
...
> + /* If nr_irqs is zero, indicate it in flag and set to max range possible */
> + if (!nr_irqs) {
Make conditional positive.
> + ext_intc_element->flag |= RISCV_ACPI_INTC_FLAG_PENDING;
> + ext_intc_element->nr_irqs = U32_MAX - ext_intc_element->gsi_base;
One space too many.
> + } else {
> + ext_intc_element->nr_irqs = nr_irqs;
> + }
--
With Best Regards,
Andy Shevchenko
WARNING: multiple messages have this Message-ID (diff)
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: "Jassi Brar" <jassisinghbrar@gmail.com>,
"Atish Patra" <atish.patra@linux.dev>,
"Michael Turquette" <mturquette@baylibre.com>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
"Rob Herring" <robh@kernel.org>,
"Anup Patel" <anup@brainfault.org>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
devicetree@vger.kernel.org, "Conor Dooley" <conor+dt@kernel.org>,
"Leyfoon Tan" <leyfoon.tan@starfivetech.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Stephen Boyd" <sboyd@kernel.org>,
linux-kernel@vger.kernel.org,
"Samuel Holland" <samuel.holland@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Rahul Pathak" <rpathak@ventanamicro.com>,
"Len Brown" <lenb@kernel.org>
Subject: Re: [PATCH v3 18/23] ACPI: RISC-V: Add support to update gsi range
Date: Mon, 12 May 2025 10:31:05 +0300 [thread overview]
Message-ID: <aCGjuc9AmZaKBGg5@smile.fi.intel.com> (raw)
In-Reply-To: <20250511133939.801777-19-apatel@ventanamicro.com>
On Sun, May 11, 2025 at 07:09:34PM +0530, Anup Patel wrote:
> From: Sunil V L <sunilvl@ventanamicro.com>
>
> Some RISC-V interrupt controllers like RPMI based system MSI interrupt
> controllers do not have MADT entry defined. These interrupt controllers
> exist only in the namespace. ACPI spec defines _GSB method to get the
> GSI base of the interrupt controller, However, there is no such standard
> method to get the GSI range. To support such interrupt controllers, set
> the GSI range of such interrupt controllers to non-overlapping range and
> provide API for interrupt controller driver to update it with proper
> value.
...
> +static inline int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs)
> +{
> + return -1;
Why not using the defined error code?
> +}
...
> +int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs)
> +{
> + struct riscv_ext_intc_list *ext_intc_element;
> +
> + list_for_each_entry(ext_intc_element, &ext_intc_list, list) {
> + if (gsi_base == ext_intc_element->gsi_base &&
> + (ext_intc_element->flag & RISCV_ACPI_INTC_FLAG_PENDING)) {
> + ext_intc_element->nr_irqs = nr_irqs;
> + ext_intc_element->flag &= ~RISCV_ACPI_INTC_FLAG_PENDING;
> + return 0;
> + }
> + }
> + return -1;
Ditto.
> +}
...
> + /* If nr_irqs is zero, indicate it in flag and set to max range possible */
> + if (!nr_irqs) {
Make conditional positive.
> + ext_intc_element->flag |= RISCV_ACPI_INTC_FLAG_PENDING;
> + ext_intc_element->nr_irqs = U32_MAX - ext_intc_element->gsi_base;
One space too many.
> + } else {
> + ext_intc_element->nr_irqs = nr_irqs;
> + }
--
With Best Regards,
Andy Shevchenko
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next prev parent reply other threads:[~2025-05-12 7:31 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-11 13:39 [PATCH v3 00/23] Linux SBI MPXY and RPMI drivers Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 01/23] riscv: Add new error codes defined by SBI v3.0 Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 02/23] dt-bindings: mailbox: Add bindings for RPMI shared memory transport Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-19 17:26 ` Rob Herring
2025-05-19 17:26 ` Rob Herring
2025-05-21 6:12 ` Anup Patel
2025-05-21 6:12 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 03/23] dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 04/23] RISC-V: Add defines for the SBI message proxy extension Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 05/23] mailbox: Add common header for RPMI messages sent via mailbox Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 06/23] mailbox: Allow controller specific mapping using fwnode Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 07/23] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-12 18:54 ` Thomas Gleixner
2025-05-12 18:54 ` Thomas Gleixner
2025-05-21 6:08 ` Anup Patel
2025-05-21 6:08 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 08/23] dt-bindings: clock: Add RPMI clock service message proxy bindings Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 09/23] dt-bindings: clock: Add RPMI clock service controller bindings Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 10/23] clk: Add clock driver for the RISC-V RPMI clock service group Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-12 7:07 ` Andy Shevchenko
2025-05-12 7:07 ` Andy Shevchenko
2025-05-12 9:58 ` Rahul Pathak
2025-05-12 9:58 ` Rahul Pathak
2025-05-12 14:15 ` Andy Shevchenko
2025-05-12 14:15 ` Andy Shevchenko
2025-05-22 13:14 ` Rahul Pathak
2025-05-22 13:14 ` Rahul Pathak
2025-05-23 16:35 ` Andy Shevchenko
2025-05-23 16:35 ` Andy Shevchenko
2025-05-11 13:39 ` [PATCH v3 11/23] dt-bindings: Add RPMI system MSI message proxy bindings Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 12/23] dt-bindings: Add RPMI system MSI interrupt controller bindings Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 13/23] irqchip: Add driver for the RPMI system MSI service group Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-12 6:50 ` Andy Shevchenko
2025-05-12 6:50 ` Andy Shevchenko
2025-05-21 11:37 ` Anup Patel
2025-05-21 11:37 ` Anup Patel
2025-05-21 14:11 ` Andy Shevchenko
2025-05-21 14:11 ` Andy Shevchenko
2025-05-23 11:38 ` Anup Patel
2025-05-23 11:38 ` Anup Patel
2025-05-12 18:58 ` Thomas Gleixner
2025-05-12 18:58 ` Thomas Gleixner
2025-05-21 11:37 ` Anup Patel
2025-05-21 11:37 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 14/23] ACPI: property: Refactor acpi_fwnode_get_reference_args() Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-12 8:43 ` Andy Shevchenko
2025-05-12 8:43 ` Andy Shevchenko
2025-05-11 13:39 ` [PATCH v3 15/23] ACPI: property: Add support for cells property Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-12 7:16 ` Andy Shevchenko
2025-05-12 7:16 ` Andy Shevchenko
2025-05-12 8:30 ` Sunil V L
2025-05-12 8:30 ` Sunil V L
2025-05-11 13:39 ` [PATCH v3 16/23] ACPI: scan: Update honor list for RPMI System MSI Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 17/23] ACPI: RISC-V: Create interrupt controller list in sorted order Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 18/23] ACPI: RISC-V: Add support to update gsi range Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-12 7:31 ` Andy Shevchenko [this message]
2025-05-12 7:31 ` Andy Shevchenko
2025-05-11 13:39 ` [PATCH v3 19/23] ACPI: RISC-V: Add RPMI System MSI to GSI mapping Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 20/23] mailbox/riscv-sbi-mpxy: Add ACPI support Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-12 7:28 ` Andy Shevchenko
2025-05-12 7:28 ` Andy Shevchenko
2025-05-12 8:36 ` Sunil V L
2025-05-12 8:36 ` Sunil V L
2025-05-12 8:47 ` Andy Shevchenko
2025-05-12 8:47 ` Andy Shevchenko
2025-05-12 8:57 ` Sunil V L
2025-05-12 8:57 ` Sunil V L
2025-05-11 13:39 ` [PATCH v3 21/23] irqchip/riscv-rpmi-sysmsi: " Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-12 7:34 ` Andy Shevchenko
2025-05-12 7:34 ` Andy Shevchenko
2025-05-12 8:42 ` Sunil V L
2025-05-12 8:42 ` Sunil V L
2025-05-11 13:39 ` [PATCH v3 22/23] RISC-V: Enable GPIO keyboard and event device in RV64 defconfig Anup Patel
2025-05-11 13:39 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 23/23] MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers Anup Patel
2025-05-11 13:39 ` Anup Patel
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