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From: Ben Zong-You Xie <ben717@andestech.com>
To: Rob Herring <robh@kernel.org>
Cc: <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>, <krzk+dt@kernel.org>,
	<conor+dt@kernel.org>, <tglx@linutronix.de>,
	<daniel.lezcano@linaro.org>,
	<prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<geert+renesas@glider.be>, <magnus.damm@gmail.com>,
	<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <tim609@andestech.com>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v4 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller
Date: Thu, 15 May 2025 11:12:36 +0800	[thread overview]
Message-ID: <aCVbpNkyHlfg+vc7@atctrx.andestech.com> (raw)
In-Reply-To: <20250514150102.GA2180131-robh@kernel.org>

On Wed, May 14, 2025 at 10:01:02AM -0500, Rob Herring wrote:
> [EXTERNAL MAIL]
> 
> On Wed, May 14, 2025 at 05:53:45PM +0800, Ben Zong-You Xie wrote:
> > Add the DT binding documentation for Andes machine-level software
> > interrupt controller.
> >
> > In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
> > second time with all interrupt sources tied to zero as the software
> > interrupt controller (PLICSW). PLICSW can generate machine-level software
> > interrupts through programming its registers.
> >
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> > ---
> >  .../andestech,plicsw.yaml                     | 54 +++++++++++++++++++
> >  MAINTAINERS                                   |  1 +
> 
> This won't apply for me due to MAINTAINERS conflict with this series. So
> apply the bindings patches with the dts files.
> 
> Rob

The conflict is due to the second patch in this series not being applied.
Should I wait for that patch to be applied, or is there something specific
I can do to resolve the conflict?

Thanks,
Ben


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WARNING: multiple messages have this Message-ID (diff)
From: Ben Zong-You Xie <ben717@andestech.com>
To: Rob Herring <robh@kernel.org>
Cc: <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>, <krzk+dt@kernel.org>,
	<conor+dt@kernel.org>, <tglx@linutronix.de>,
	<daniel.lezcano@linaro.org>,
	<prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<geert+renesas@glider.be>, <magnus.damm@gmail.com>,
	<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <tim609@andestech.com>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v4 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller
Date: Thu, 15 May 2025 11:12:36 +0800	[thread overview]
Message-ID: <aCVbpNkyHlfg+vc7@atctrx.andestech.com> (raw)
In-Reply-To: <20250514150102.GA2180131-robh@kernel.org>

On Wed, May 14, 2025 at 10:01:02AM -0500, Rob Herring wrote:
> [EXTERNAL MAIL]
> 
> On Wed, May 14, 2025 at 05:53:45PM +0800, Ben Zong-You Xie wrote:
> > Add the DT binding documentation for Andes machine-level software
> > interrupt controller.
> >
> > In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
> > second time with all interrupt sources tied to zero as the software
> > interrupt controller (PLICSW). PLICSW can generate machine-level software
> > interrupts through programming its registers.
> >
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> > ---
> >  .../andestech,plicsw.yaml                     | 54 +++++++++++++++++++
> >  MAINTAINERS                                   |  1 +
> 
> This won't apply for me due to MAINTAINERS conflict with this series. So
> apply the bindings patches with the dts files.
> 
> Rob

The conflict is due to the second patch in this series not being applied.
Should I wait for that patch to be applied, or is there something specific
I can do to resolve the conflict?

Thanks,
Ben


  reply	other threads:[~2025-05-15  3:13 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-14  9:53 [PATCH v4 0/9] add Voyager board support Ben Zong-You Xie
2025-05-14  9:53 ` Ben Zong-You Xie
2025-05-14  9:53 ` [PATCH v4 1/9] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
2025-05-14  9:53   ` Ben Zong-You Xie
2025-05-14  9:53 ` [PATCH v4 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Ben Zong-You Xie
2025-05-14  9:53   ` Ben Zong-You Xie
2025-05-14  9:53 ` [PATCH v4 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Ben Zong-You Xie
2025-05-14  9:53   ` Ben Zong-You Xie
2025-05-14 14:53   ` Rob Herring (Arm)
2025-05-14 14:53     ` Rob Herring (Arm)
2025-05-14 15:01     ` Rob Herring
2025-05-14 15:01       ` Rob Herring
2025-05-15  3:25       ` Ben Zong-You Xie
2025-05-15  3:25         ` Ben Zong-You Xie
2025-05-14  9:53 ` [PATCH v4 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Ben Zong-You Xie
2025-05-14  9:53   ` Ben Zong-You Xie
2025-05-14 15:01   ` Rob Herring
2025-05-14 15:01     ` Rob Herring
2025-05-15  3:12     ` Ben Zong-You Xie [this message]
2025-05-15  3:12       ` Ben Zong-You Xie
2025-05-14  9:53 ` [PATCH v4 5/9] dt-bindings: timer: add Andes machine timer Ben Zong-You Xie
2025-05-14  9:53   ` Ben Zong-You Xie
2025-05-14 15:21   ` Daniel Lezcano
2025-05-14 15:21     ` Daniel Lezcano
2025-05-14  9:53 ` [PATCH v4 6/9] dt-bindings: cache: add QiLai compatible to ax45mp Ben Zong-You Xie
2025-05-14  9:53   ` Ben Zong-You Xie
2025-05-14  9:53 ` [PATCH v4 7/9] riscv: dts: andes: add QiLai SoC device tree Ben Zong-You Xie
2025-05-14  9:53   ` Ben Zong-You Xie
2025-05-14  9:53 ` [PATCH v4 8/9] riscv: dts: andes: add Voyager board " Ben Zong-You Xie
2025-05-14  9:53   ` Ben Zong-You Xie
2025-05-14  9:53 ` [PATCH v4 9/9] riscv: defconfig: enable Andes SoC Ben Zong-You Xie
2025-05-14  9:53   ` Ben Zong-You Xie
2025-05-14 15:53 ` (subset) [PATCH v4 0/9] add Voyager board support Conor Dooley
2025-05-14 15:53   ` Conor Dooley

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