From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: xen-devel@lists.xenproject.org,
"Anthony PERARD" <anthony.perard@vates.tech>,
"Michal Orzel" <michal.orzel@amd.com>,
"Jan Beulich" <jbeulich@suse.com>,
"Julien Grall" <julien@xen.org>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Stefano Stabellini" <sstabellini@kernel.org>,
trenchboot-devel@googlegroups.com
Subject: Re: [PATCH v2 09/22] xen/lib: add implementation of SHA-1
Date: Sat, 17 May 2025 21:17:51 +0300 [thread overview]
Message-ID: <aCjSz6QXHiFtAjFP@MjU3Nj> (raw)
In-Reply-To: <fdc5b712-4c93-42b4-a1b7-d992c720c387@citrix.com>
On Wed, May 14, 2025 at 05:58:59PM +0100, Andrew Cooper wrote:
> Please crib from sha2.h as much as you can. Use xen/types.h, drop the
> double underscore in the guard, and provide a link to the spec.
Until yesterday CODING_STYLE instructed to have 2 underscores, so I
thought sha2.h is outdated. I'll switch to <xen/types.h>, although it's
overkill there and only grows header dependency tree (it also brings
extra symbols thus hiding missing includes elsewhere).
> I think it's https://csrc.nist.gov/pubs/fips/180-1/final
Looks like https://csrc.nist.gov/pubs/fips/180-4/upd1/final is the
latest for all SHA algorithms.
> > +struct sha1_state {
> > + uint32_t state[SHA1_DIGEST_SIZE / 4];
> > + uint64_t count;
> > + uint8_t buffer[SHA1_BLOCK_SIZE];
> > +};
>
> As it's uint64_t, the count field needs to be first to avoid padding.
Will swap them.
> > +/* This "rolls" over the 512-bit array */
> > +static void set_w(uint32_t w[SHA1_WORKSPACE_WORDS], size_t i, uint32_t val)
> > +{
> > +#ifdef CONFIG_X86
> > + *(volatile uint32_t *)&w[i & SHA1_WORKSPACE_MASK] = val;
> > +#else
> > + w[i & SHA1_WORKSPACE_MASK] = val;
> > +# ifdef CONFIG_ARM
> > + barrier();
> > +# endif
> > +#endif
>
> This is horrible. I think the problems discussed are created by having
> the loops in sha1_transform() broken in a wrong (read, unhelpful) way.
> The 5-way shuffle of the chaining variables probably is beyond the
> compilers' ability to unroll given the multiples of 4 currently used.
>
> See the implementation in SKL where I spent a while optimising the code
> generation. Admittedly that was optimising for size rather than speed,
> but the end result look to be good for both.
I tried just doing regular writes and didn't notice any massive
changes in the disassembly with GCC 14.2.0, in fact the function got
shorter by 41 bytes and its stack frame size decreased by 8 bytes. That
comment was probably addressing misbehaviour of some older version.
> > + /* Round 1 - iterations 0-16 take their input from 'data' */
> > + for ( ; i < 16; ++i ) {
>
> Xen style has this { on the next line.
Will fix.
> > +static void sha1_update(struct sha1_state *sctx, const uint8_t *msg, size_t len)
> > +{
> > + unsigned int partial = sctx->count % SHA1_BLOCK_SIZE;
> > +
> > + sctx->count += len;
> > +
> > + if ( (partial + len) >= SHA1_BLOCK_SIZE )
> > + {
> > + if ( partial )
> > + {
> > + int rem = SHA1_BLOCK_SIZE - partial;
>
> Unsigned int please.
Will do.
> > +static void sha1_final(struct sha1_state *sctx, void *out)
>
> Please make this uint8_t digest[SHA1_DIGEST_SIZE] straight away. This
> was an oversight of mine in sha2-256.c which was fixed when exposing the
> function (c/s aea52ce607fe).
OK. I skipped that intentionally because it really only adds an
explicit cast in the body which is not much different from casting to
`void *` and back.
Regards
next prev parent reply other threads:[~2025-05-17 18:18 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-13 17:05 [PATCH v2 00/22] x86: Trenchboot Secure Launch DRTM (Xen) Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 01/22] x86/include/asm/intel-txt.h: constants and accessors for TXT registers and heap Sergii Dmytruk
2025-05-14 14:55 ` Andrew Cooper
2025-05-14 20:09 ` Krystian Hebel
2025-05-18 18:35 ` Sergii Dmytruk
2025-05-18 23:31 ` Rich Persaud
2025-05-19 13:43 ` Sergii Dmytruk
2025-05-19 20:55 ` Rich Persaud
2025-05-21 15:05 ` Jan Beulich
2025-05-21 15:19 ` Jan Beulich
2025-05-23 19:51 ` Sergii Dmytruk
2025-06-02 7:17 ` Jan Beulich
2025-06-02 22:00 ` Sergii Dmytruk
2025-06-03 7:06 ` Jan Beulich
2025-06-03 8:50 ` Sergii Dmytruk
2025-06-03 8:52 ` Jan Beulich
2025-06-03 15:20 ` Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 02/22] include/xen/slr-table.h: Secure Launch Resource Table definitions Sergii Dmytruk
2025-05-21 15:45 ` Jan Beulich
2025-05-21 15:50 ` Andrew Cooper
2025-05-23 22:19 ` Sergii Dmytruk
2025-06-02 7:31 ` Jan Beulich
2025-06-02 22:19 ` Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 03/22] x86/boot: add MLE header and Secure Launch entry point Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 04/22] x86/boot/slaunch-early: implement early initialization Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 05/22] x86/boot/slaunch-early: early TXT checks and boot data retrieval Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 06/22] xen/arch/x86: reserve TXT memory during Slaunch Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 07/22] x86/mtrr: expose functions for pausing caching Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 08/22] x86/slaunch: restore boot MTRRs after Intel TXT DRTM Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 09/22] xen/lib: add implementation of SHA-1 Sergii Dmytruk
2025-05-14 16:58 ` Andrew Cooper
2025-05-17 18:17 ` Sergii Dmytruk [this message]
2025-05-18 8:34 ` Jan Beulich
2025-05-18 11:32 ` Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 10/22] x86/tpm.c: code for early hashing and extending PCRs (for TPM1.2) Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 11/22] x86/tpm.c: support extending PCRs of TPM2.0 Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 12/22] x86/hvm: check for VMX in SMX if Slaunch is active Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 13/22] x86/tpm.c: implement event log for TPM2.0 Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 14/22] x86/boot: choose AP stack based on APIC ID Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 15/22] x86/smpboot.c: TXT AP bringup Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 16/22] x86/slaunch: process DRTM policy Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 17/22] x86/acpi: disallow S3 on Secure Launch boot Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 18/22] x86/boot/slaunch-early: find MBI and SLRT on AMD Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 19/22] x86/slaunch: support AMD SKINIT Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 20/22] x86/slaunch: support EFI boot Sergii Dmytruk
2025-05-14 1:25 ` Demi Marie Obenour
2025-05-14 14:24 ` Sergii Dmytruk
2025-05-14 15:58 ` Demi Marie Obenour
2025-05-14 16:12 ` Marek Marczykowski-Górecki
2025-05-15 14:39 ` Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 21/22] x86/cpu: report SMX, TXT and SKINIT capabilities Sergii Dmytruk
2025-05-13 17:05 ` [PATCH v2 22/22] MAINTAINERS: add a section for TrenchBoot Slaunch Sergii Dmytruk
2025-05-14 6:36 ` Jan Beulich
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