From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Frank Li <Frank.li@nxp.com>
Cc: Jorge Marques <jorge.marques@analog.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-i3c@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] i3c: master: Add driver for Analog Devices I3C Controller IP
Date: Thu, 5 Jun 2025 22:14:10 +0200 [thread overview]
Message-ID: <aEH6kpXStLc0dWZq@shikoro> (raw)
In-Reply-To: <aECaFQzkPYdfjagK@lizhi-Precision-Tower-5810>
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> > +static void adi_i3c_master_wr_to_tx_fifo(struct adi_i3c_master *master,
> > + const u8 *bytes, int nbytes)
> > +{
> > + writesl(master->regs + REG_SDO_FIFO, bytes, nbytes / 4);
> > + if (nbytes & 3) {
> > + u32 tmp = 0;
> > +
> > + memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
>
> ALIGN_DOWN(bytes, 4)?
>
> Do you need conside big/little endian to trim down data?
The driver uses the same code for reading/writing the FIFO as the
Designware and Cadence driver. The Renesas driver I am working on has
also the same pattern. Time for a helper function maybe
i3c_{read|write}l_to_fifo(register, data, length);
?
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WARNING: multiple messages have this Message-ID (diff)
From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Frank Li <Frank.li@nxp.com>
Cc: Jorge Marques <jorge.marques@analog.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-i3c@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] i3c: master: Add driver for Analog Devices I3C Controller IP
Date: Thu, 5 Jun 2025 22:14:10 +0200 [thread overview]
Message-ID: <aEH6kpXStLc0dWZq@shikoro> (raw)
In-Reply-To: <aECaFQzkPYdfjagK@lizhi-Precision-Tower-5810>
[-- Attachment #1: Type: text/plain, Size: 653 bytes --]
> > +static void adi_i3c_master_wr_to_tx_fifo(struct adi_i3c_master *master,
> > + const u8 *bytes, int nbytes)
> > +{
> > + writesl(master->regs + REG_SDO_FIFO, bytes, nbytes / 4);
> > + if (nbytes & 3) {
> > + u32 tmp = 0;
> > +
> > + memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
>
> ALIGN_DOWN(bytes, 4)?
>
> Do you need conside big/little endian to trim down data?
The driver uses the same code for reading/writing the FIFO as the
Designware and Cadence driver. The Renesas driver I am working on has
also the same pattern. Time for a helper function maybe
i3c_{read|write}l_to_fifo(register, data, length);
?
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next prev parent reply other threads:[~2025-06-24 0:30 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-04 15:48 [PATCH 0/2] Add ADI I3C Controller Jorge Marques
2025-06-04 15:48 ` Jorge Marques
2025-06-04 15:48 ` [PATCH 1/2] dt-bindings: i3c: Add adi-i3c-master Jorge Marques
2025-06-04 15:48 ` Jorge Marques
2025-06-04 18:36 ` Frank Li
2025-06-04 18:36 ` Frank Li
2025-06-06 9:40 ` Jorge Marques
2025-06-06 9:40 ` Jorge Marques
2025-06-04 15:48 ` [PATCH 2/2] i3c: master: Add driver for Analog Devices I3C Controller IP Jorge Marques
2025-06-04 15:48 ` Jorge Marques
2025-06-04 19:10 ` Frank Li
2025-06-04 19:10 ` Frank Li
2025-06-04 22:00 ` Wolfram Sang
2025-06-04 22:00 ` Wolfram Sang
2025-06-06 10:15 ` Jorge Marques
2025-06-06 10:15 ` Jorge Marques
2025-06-05 20:14 ` Wolfram Sang [this message]
2025-06-05 20:14 ` Wolfram Sang
2025-06-06 10:05 ` Jorge Marques
2025-06-06 10:05 ` Jorge Marques
2025-06-05 2:05 ` kernel test robot
2025-06-05 2:05 ` kernel test robot
2025-06-05 5:12 ` kernel test robot
2025-06-05 5:12 ` kernel test robot
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