From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-rockchip@lists.infradead.org,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 1/4] PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2
Date: Wed, 11 Jun 2025 00:46:03 -0300 [thread overview]
Message-ID: <aEj7-6fMGKSXQb3J@geday> (raw)
In-Reply-To: <20250610200744.GA820589@bhelgaas>
On Tue, Jun 10, 2025 at 03:07:44PM -0500, Bjorn Helgaas wrote:
> On Sat, Jun 07, 2025 at 08:00:54AM -0300, Geraldo Nascimento wrote:
> This stuff:
>
> #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
> #define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8)
> #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
> #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
> #define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0)
>
> *Looks* like it might be duplicates of:
>
> #define PCI_EXP_DEVCAP 0x04 /* Device capabilities */
> #define PCI_EXP_DEVCTL 0x08 /* Device Control */
> #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */
Hi again Bjorn,
Your message reminded me of something that may be important.
During my debugging I had the mild impression L0s capability is not
being cleared from Link Capabilities Register in the presence of
"aspm-no-l0s" DT property.
I can't confirm it right now but I might revisit this later on. From
what I've seen it can only be cleared from inside the port init
in pcie-rockchip.c and does nothing in present form.
Not a clear, confirmable report but something to watch out for...
Regards,
Geraldo Nascimento
WARNING: multiple messages have this Message-ID (diff)
From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-rockchip@lists.infradead.org,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 1/4] PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2
Date: Wed, 11 Jun 2025 00:46:03 -0300 [thread overview]
Message-ID: <aEj7-6fMGKSXQb3J@geday> (raw)
In-Reply-To: <20250610200744.GA820589@bhelgaas>
On Tue, Jun 10, 2025 at 03:07:44PM -0500, Bjorn Helgaas wrote:
> On Sat, Jun 07, 2025 at 08:00:54AM -0300, Geraldo Nascimento wrote:
> This stuff:
>
> #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
> #define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8)
> #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
> #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
> #define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0)
>
> *Looks* like it might be duplicates of:
>
> #define PCI_EXP_DEVCAP 0x04 /* Device capabilities */
> #define PCI_EXP_DEVCTL 0x08 /* Device Control */
> #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */
Hi again Bjorn,
Your message reminded me of something that may be important.
During my debugging I had the mild impression L0s capability is not
being cleared from Link Capabilities Register in the presence of
"aspm-no-l0s" DT property.
I can't confirm it right now but I might revisit this later on. From
what I've seen it can only be cleared from inside the port init
in pcie-rockchip.c and does nothing in present form.
Not a clear, confirmable report but something to watch out for...
Regards,
Geraldo Nascimento
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-rockchip@lists.infradead.org,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 1/4] PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2
Date: Wed, 11 Jun 2025 00:46:03 -0300 [thread overview]
Message-ID: <aEj7-6fMGKSXQb3J@geday> (raw)
In-Reply-To: <20250610200744.GA820589@bhelgaas>
On Tue, Jun 10, 2025 at 03:07:44PM -0500, Bjorn Helgaas wrote:
> On Sat, Jun 07, 2025 at 08:00:54AM -0300, Geraldo Nascimento wrote:
> This stuff:
>
> #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
> #define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8)
> #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
> #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
> #define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0)
>
> *Looks* like it might be duplicates of:
>
> #define PCI_EXP_DEVCAP 0x04 /* Device capabilities */
> #define PCI_EXP_DEVCTL 0x08 /* Device Control */
> #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */
Hi again Bjorn,
Your message reminded me of something that may be important.
During my debugging I had the mild impression L0s capability is not
being cleared from Link Capabilities Register in the presence of
"aspm-no-l0s" DT property.
I can't confirm it right now but I might revisit this later on. From
what I've seen it can only be cleared from inside the port init
in pcie-rockchip.c and does nothing in present form.
Not a clear, confirmable report but something to watch out for...
Regards,
Geraldo Nascimento
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2025-06-11 3:56 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-07 11:00 [RFC PATCH 1/4] PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2 Geraldo Nascimento
2025-06-07 11:00 ` Geraldo Nascimento
2025-06-07 11:00 ` Geraldo Nascimento
2025-06-10 20:07 ` Bjorn Helgaas
2025-06-10 20:07 ` Bjorn Helgaas
2025-06-10 20:07 ` Bjorn Helgaas
2025-06-10 20:09 ` Geraldo Nascimento
2025-06-10 20:09 ` Geraldo Nascimento
2025-06-10 20:09 ` Geraldo Nascimento
2025-06-11 3:46 ` Geraldo Nascimento [this message]
2025-06-11 3:46 ` Geraldo Nascimento
2025-06-11 3:46 ` Geraldo Nascimento
2025-06-11 3:59 ` Geraldo Nascimento
2025-06-11 3:59 ` Geraldo Nascimento
2025-06-11 3:59 ` Geraldo Nascimento
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