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From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: linux-rockchip@lists.infradead.org,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH v5 2/4] PCI: rockchip: Set Target Link Speed before retraining
Date: Fri, 20 Jun 2025 09:43:28 -0300	[thread overview]
Message-ID: <aFVXcIGHC9aeSuAF@geday> (raw)
In-Reply-To: <562662d4-69ca-4d0e-ad0d-fd8cece417e0@arm.com>

On Fri, Jun 20, 2025 at 01:33:11PM +0100, Robin Murphy wrote:
> On 2025-06-13 6:03 pm, Geraldo Nascimento wrote:
> > Current code may fail Gen2 retraining if Target Link Speed
> > is set to 2.5 GT/s in Link Control and Status Register 2.
> > Set it to 5.0 GT/s accordingly.
> 
> I have max-link-speed overridden to 2 in my local DTB, and indeed this 
> seems to make my NVMe report a 5.0 GT/s link where previously it was 
> still downgrading to 2.5, so:
> 
> Tested-by: Robin Murphy <robin.murphy@arm.com>
>

Hi Robin,

thanks for the testing, I'll include the tag in v6 once Bjorn gets back
to me on the 16-bit adjacent registers problem.

Geraldo Nascimento


WARNING: multiple messages have this Message-ID (diff)
From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: linux-rockchip@lists.infradead.org,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH v5 2/4] PCI: rockchip: Set Target Link Speed before retraining
Date: Fri, 20 Jun 2025 09:43:28 -0300	[thread overview]
Message-ID: <aFVXcIGHC9aeSuAF@geday> (raw)
In-Reply-To: <562662d4-69ca-4d0e-ad0d-fd8cece417e0@arm.com>

On Fri, Jun 20, 2025 at 01:33:11PM +0100, Robin Murphy wrote:
> On 2025-06-13 6:03 pm, Geraldo Nascimento wrote:
> > Current code may fail Gen2 retraining if Target Link Speed
> > is set to 2.5 GT/s in Link Control and Status Register 2.
> > Set it to 5.0 GT/s accordingly.
> 
> I have max-link-speed overridden to 2 in my local DTB, and indeed this 
> seems to make my NVMe report a 5.0 GT/s link where previously it was 
> still downgrading to 2.5, so:
> 
> Tested-by: Robin Murphy <robin.murphy@arm.com>
>

Hi Robin,

thanks for the testing, I'll include the tag in v6 once Bjorn gets back
to me on the 16-bit adjacent registers problem.

Geraldo Nascimento

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: linux-rockchip@lists.infradead.org,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH v5 2/4] PCI: rockchip: Set Target Link Speed before retraining
Date: Fri, 20 Jun 2025 09:43:28 -0300	[thread overview]
Message-ID: <aFVXcIGHC9aeSuAF@geday> (raw)
In-Reply-To: <562662d4-69ca-4d0e-ad0d-fd8cece417e0@arm.com>

On Fri, Jun 20, 2025 at 01:33:11PM +0100, Robin Murphy wrote:
> On 2025-06-13 6:03 pm, Geraldo Nascimento wrote:
> > Current code may fail Gen2 retraining if Target Link Speed
> > is set to 2.5 GT/s in Link Control and Status Register 2.
> > Set it to 5.0 GT/s accordingly.
> 
> I have max-link-speed overridden to 2 in my local DTB, and indeed this 
> seems to make my NVMe report a 5.0 GT/s link where previously it was 
> still downgrading to 2.5, so:
> 
> Tested-by: Robin Murphy <robin.murphy@arm.com>
>

Hi Robin,

thanks for the testing, I'll include the tag in v6 once Bjorn gets back
to me on the 16-bit adjacent registers problem.

Geraldo Nascimento

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

  reply	other threads:[~2025-06-20 12:58 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-13 17:03 [RFC PATCH v5 0/4] PCI: rockchip: Improve driver quality Geraldo Nascimento
2025-06-13 17:03 ` Geraldo Nascimento
2025-06-13 17:03 ` Geraldo Nascimento
2025-06-13 17:03 ` [RFC PATCH v5 1/4] PCI: rockchip: Use standard PCIe defines Geraldo Nascimento
2025-06-13 17:03   ` Geraldo Nascimento
2025-06-13 17:03   ` Geraldo Nascimento
2025-06-13 17:03 ` [RFC PATCH v5 2/4] PCI: rockchip: Set Target Link Speed before retraining Geraldo Nascimento
2025-06-13 17:03   ` Geraldo Nascimento
2025-06-13 17:03   ` Geraldo Nascimento
2025-06-13 18:06   ` Geraldo Nascimento
2025-06-13 18:06     ` Geraldo Nascimento
2025-06-13 18:06     ` Geraldo Nascimento
2025-06-20 12:33   ` Robin Murphy
2025-06-20 12:33     ` Robin Murphy
2025-06-20 12:33     ` Robin Murphy
2025-06-20 12:43     ` Geraldo Nascimento [this message]
2025-06-20 12:43       ` Geraldo Nascimento
2025-06-20 12:43       ` Geraldo Nascimento
2025-06-13 17:03 ` [RFC PATCH v5 3/4] phy: rockchip-pcie: Enable all four lanes Geraldo Nascimento
2025-06-13 17:03   ` Geraldo Nascimento
2025-06-13 17:03   ` Geraldo Nascimento
2025-06-20 12:04   ` Robin Murphy
2025-06-20 12:04     ` Robin Murphy
2025-06-20 12:04     ` Robin Murphy
2025-06-20 12:26     ` Geraldo Nascimento
2025-06-20 12:26       ` Geraldo Nascimento
2025-06-20 12:26       ` Geraldo Nascimento
2025-06-20 12:47       ` Robin Murphy
2025-06-20 12:47         ` Robin Murphy
2025-06-20 12:47         ` Robin Murphy
2025-06-20 13:00         ` Geraldo Nascimento
2025-06-20 13:00           ` Geraldo Nascimento
2025-06-20 13:00           ` Geraldo Nascimento
2025-06-20 12:50       ` Geraldo Nascimento
2025-06-20 12:50         ` Geraldo Nascimento
2025-06-20 12:50         ` Geraldo Nascimento
2025-06-13 17:04 ` [RFC PATCH v5 4/4] phy: rockchip-pcie: Adjust read mask and write Geraldo Nascimento
2025-06-13 17:04   ` Geraldo Nascimento
2025-06-13 17:04   ` Geraldo Nascimento
2025-06-20 14:19   ` Robin Murphy
2025-06-20 14:19     ` Robin Murphy
2025-06-20 14:19     ` Robin Murphy
2025-06-20 15:23     ` Geraldo Nascimento
2025-06-20 15:23       ` Geraldo Nascimento
2025-06-20 15:23       ` Geraldo Nascimento
2025-06-20 18:35     ` Geraldo Nascimento
2025-06-20 18:35       ` Geraldo Nascimento
2025-06-20 18:35       ` Geraldo Nascimento

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