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From: dmukhin@xen.org
To: Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
	michal.orzel@amd.com, roger.pau@citrix.com, dmukhin@ford.com
Subject: Re: [PATCH v5 07/15] emul/ns16x50: implement FCR register (write-only)
Date: Fri, 5 Sep 2025 15:33:25 -0700	[thread overview]
Message-ID: <aLtlNeuk18rDSs4p@kraken> (raw)
In-Reply-To: <alpine.DEB.2.22.394.2508291335260.341243@ubuntu-linux-20-04-desktop>

On Fri, Aug 29, 2025 at 01:38:02PM -0700, Stefano Stabellini wrote:
> On Thu, 28 Aug 2025, dmukhin@xen.org wrote:
> > From: Denis Mukhin <dmukhin@ford.com> 
> > 
> > Add emulation logic for FCR register.
> > 
> > Note, that does not hooks FIFO interrupt moderation to the FIFO management
> > code.
> > 
> > Signed-off-by: Denis Mukhin <dmukhin@ford.com>
> > ---
> > Changes since v4:
> > - new patch
> > ---
> >  xen/common/emul/vuart/ns16x50.c | 24 ++++++++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> > 
> > diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
> > index efb2f4c6441c..65ca96dd8bd3 100644
> > --- a/xen/common/emul/vuart/ns16x50.c
> > +++ b/xen/common/emul/vuart/ns16x50.c
> > @@ -363,6 +363,30 @@ static int ns16x50_io_write8(
> >  
> >              break;
> >  
> > +        case UART_FCR: /* WO */
> > +            if ( val & UART_FCR_RESERVED0 )
> > +                ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
> > +                             UART_FCR_RESERVED0);
> > +
> > +            if ( val & UART_FCR_RESERVED1 )
> > +                ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
> > +                             UART_FCR_RESERVED1);
> > +
> > +            if ( val & UART_FCR_CLRX )
> > +                ns16x50_fifo_rx_reset(vdev);
> > +
> > +            if ( val & UART_FCR_CLTX )
> > +                ns16x50_fifo_tx_flush(vdev);
> 
> Should UART_FCR_CLTX actually emit data or only clear the buffer?

Yes, thanks; should be just "tx_reset".

> 
> set UART_IIR_THR ?

Will do, thanks.

> 
> 
> > +
> > +            if ( val & UART_FCR_ENABLE )
> > +                val &= UART_FCR_ENABLE | UART_FCR_DMA | UART_FCR_TRG_MASK;
> > +            else
> > +                val = 0;
> > +
> > +            regs[UART_FCR] = val;
> 
> 
> ns16x50_irq_check ?

ns16x50_irq_check() is poked after the switch statement.

> 
> 
> > +            break;
> > +
> >          default:
> >              rc = -EINVAL;
> >              break;
> > -- 
> > 2.51.0
> > 


  reply	other threads:[~2025-09-05 22:33 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-28 23:53 [PATCH v5 00/15] x86: introduce NS16550-compatible UART emulator dmukhin
2025-08-28 23:53 ` [PATCH v5 01/15] emul/vuart: introduce framework for UART emulators dmukhin
2025-08-29 19:27   ` Stefano Stabellini
2025-09-01  8:14     ` Jan Beulich
2025-09-01 22:27       ` dmukhin
2025-09-02  6:14         ` Jan Beulich
2025-09-01 22:11     ` dmukhin
2025-08-28 23:53 ` [PATCH v5 02/15] xen/8250-uart: update definitions dmukhin
2025-08-29 19:32   ` Stefano Stabellini
2025-09-01 22:28     ` dmukhin
2025-08-28 23:53 ` [PATCH v5 03/15] emul/ns16x50: implement emulator stub dmukhin
2025-08-29 19:57   ` Stefano Stabellini
2025-09-01 23:11     ` dmukhin
2025-09-02  9:32       ` Jan Beulich
2025-09-05 23:34         ` dmukhin
2025-09-06  0:07           ` dmukhin
2025-09-02  9:36     ` Jan Beulich
2025-09-05 23:34       ` dmukhin
2025-08-28 23:53 ` [PATCH v5 04/15] emul/ns16x50: implement DLL/DLM registers dmukhin
2025-08-28 23:53 ` [PATCH v5 05/15] emul/ns16x50: implement EIR/IIR registers dmukhin
2025-08-29 20:14   ` Stefano Stabellini
2025-09-05 22:05     ` dmukhin
2025-08-28 23:54 ` [PATCH v5 06/15] emul/ns16x50: implement THR/RBR registers dmukhin
2025-08-29 20:28   ` Stefano Stabellini
2025-08-29 20:34     ` Stefano Stabellini
2025-09-05 22:29       ` dmukhin
2025-09-05 22:20     ` dmukhin
2025-08-28 23:54 ` [PATCH v5 07/15] emul/ns16x50: implement FCR register (write-only) dmukhin
2025-08-29 20:38   ` Stefano Stabellini
2025-09-05 22:33     ` dmukhin [this message]
2025-08-28 23:54 ` [PATCH v5 08/15] emul/ns16x50: implement LCR/LSR registers dmukhin
2025-08-28 23:54 ` [PATCH v5 09/15] emul/ns16x50: implement MCR/MSR registers dmukhin
2025-08-28 23:54 ` [PATCH v5 10/15] emul/ns16x50: implement SCR register dmukhin
2025-08-28 23:54 ` [PATCH v5 11/15] emul/ns16x50: implement put_rx() hook dmukhin
2025-08-28 23:54 ` [PATCH v5 12/15] emul/ns16550: implement dump_state() hook dmukhin
2025-08-28 23:54 ` [PATCH v5 13/15] x86/domain: enable per-domain I/O port bitmaps dmukhin
2025-08-29 21:43   ` Stefano Stabellini
2025-09-05 22:38     ` dmukhin
2025-08-28 23:54 ` [PATCH v5 14/15] xen/domain: allocate d->irq_caps before arch-specific initialization dmukhin
2025-08-29 21:46   ` Stefano Stabellini
2025-09-05 22:43     ` dmukhin
2025-08-28 23:54 ` [PATCH v5 15/15] emul/ns16x50: implement IRQ emulation via vIOAPIC dmukhin
2025-08-29 22:21   ` Stefano Stabellini
2025-09-05 22:54     ` dmukhin
2025-09-05 23:01       ` Stefano Stabellini
2025-09-05 23:44         ` dmukhin

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