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From: Aurelien Jarno <aurelien@aurel32.net>
To: Alex Elder <elder@riscstar.com>
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	bhelgaas@google.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org, vkoul@kernel.org,
	kishon@kernel.org, dlan@gentoo.org, guodong@riscstar.com,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, p.zabel@pengutronix.de,
	christian.bruel@foss.st.com, shradha.t@samsung.com,
	krishna.chundru@oss.qualcomm.com, qiang.yu@oss.qualcomm.com,
	namcao@linutronix.de, thippeswamy.havalige@amd.com,
	inochiama@gmail.com, devicetree@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-phy@lists.infradead.org,
	spacemit@lists.linux.dev, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller
Date: Thu, 16 Oct 2025 18:47:56 +0200	[thread overview]
Message-ID: <aPEhvFD8TzVtqE2n@aurel32.net> (raw)
In-Reply-To: <20251013153526.2276556-1-elder@riscstar.com>

Hi Alex,

On 2025-10-13 10:35, Alex Elder wrote:
> This series introduces a PHY driver and a PCIe driver to support PCIe
> on the SpacemiT K1 SoC.  The PCIe implementation is derived from a
> Synopsys DesignWare PCIe IP.  The PHY driver supports one combination
> PCIe/USB PHY as well as two PCIe-only PHYs.  The combo PHY port uses
> one PCIe lane, and the other two ports each have two lanes.  All PCIe
> ports operate at 5 GT/second.
> 
> The PCIe PHYs must be configured using a value that can only be
> determined using the combo PHY, operating in PCIe mode.  To allow
> that PHY to be used for USB, the calibration step is performed by
> the PHY driver automatically at probe time.  Once this step is done,
> the PHY can be used for either PCIe or USB.
> 
> Version 2 of this series incorporates suggestions made during the
> review of version 1.  Specific highlights are detailed below.

With the issues mentioned in patch 4 fixed, this patchset works fine for 
me. That said I had to disable ASPM by passing pcie_aspm=off on the 
command line, as it is now enabled by default since 6.18-rc1 [1]. At 
this stage, I am not sure if it is an issue with my NVME drive or an 
issue with the controller.

Regards
Aurelien

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f3ac2ff14834a0aa056ee3ae0e4b8c641c579961

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                     http://aurel32.net

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Aurelien Jarno <aurelien@aurel32.net>
To: Alex Elder <elder@riscstar.com>
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	bhelgaas@google.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org, vkoul@kernel.org,
	kishon@kernel.org, dlan@gentoo.org, guodong@riscstar.com,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, p.zabel@pengutronix.de,
	christian.bruel@foss.st.com, shradha.t@samsung.com,
	krishna.chundru@oss.qualcomm.com, qiang.yu@oss.qualcomm.com,
	namcao@linutronix.de, thippeswamy.havalige@amd.com,
	inochiama@gmail.com, devicetree@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-phy@lists.infradead.org,
	spacemit@lists.linux.dev, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller
Date: Thu, 16 Oct 2025 18:47:56 +0200	[thread overview]
Message-ID: <aPEhvFD8TzVtqE2n@aurel32.net> (raw)
In-Reply-To: <20251013153526.2276556-1-elder@riscstar.com>

Hi Alex,

On 2025-10-13 10:35, Alex Elder wrote:
> This series introduces a PHY driver and a PCIe driver to support PCIe
> on the SpacemiT K1 SoC.  The PCIe implementation is derived from a
> Synopsys DesignWare PCIe IP.  The PHY driver supports one combination
> PCIe/USB PHY as well as two PCIe-only PHYs.  The combo PHY port uses
> one PCIe lane, and the other two ports each have two lanes.  All PCIe
> ports operate at 5 GT/second.
> 
> The PCIe PHYs must be configured using a value that can only be
> determined using the combo PHY, operating in PCIe mode.  To allow
> that PHY to be used for USB, the calibration step is performed by
> the PHY driver automatically at probe time.  Once this step is done,
> the PHY can be used for either PCIe or USB.
> 
> Version 2 of this series incorporates suggestions made during the
> review of version 1.  Specific highlights are detailed below.

With the issues mentioned in patch 4 fixed, this patchset works fine for 
me. That said I had to disable ASPM by passing pcie_aspm=off on the 
command line, as it is now enabled by default since 6.18-rc1 [1]. At 
this stage, I am not sure if it is an issue with my NVME drive or an 
issue with the controller.

Regards
Aurelien

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f3ac2ff14834a0aa056ee3ae0e4b8c641c579961

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                     http://aurel32.net

WARNING: multiple messages have this Message-ID (diff)
From: Aurelien Jarno <aurelien@aurel32.net>
To: Alex Elder <elder@riscstar.com>
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	bhelgaas@google.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org, vkoul@kernel.org,
	kishon@kernel.org, dlan@gentoo.org, guodong@riscstar.com,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, p.zabel@pengutronix.de,
	christian.bruel@foss.st.com, shradha.t@samsung.com,
	krishna.chundru@oss.qualcomm.com, qiang.yu@oss.qualcomm.com,
	namcao@linutronix.de, thippeswamy.havalige@amd.com,
	inochiama@gmail.com, devicetree@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-phy@lists.infradead.org,
	spacemit@lists.linux.dev, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller
Date: Thu, 16 Oct 2025 18:47:56 +0200	[thread overview]
Message-ID: <aPEhvFD8TzVtqE2n@aurel32.net> (raw)
In-Reply-To: <20251013153526.2276556-1-elder@riscstar.com>

Hi Alex,

On 2025-10-13 10:35, Alex Elder wrote:
> This series introduces a PHY driver and a PCIe driver to support PCIe
> on the SpacemiT K1 SoC.  The PCIe implementation is derived from a
> Synopsys DesignWare PCIe IP.  The PHY driver supports one combination
> PCIe/USB PHY as well as two PCIe-only PHYs.  The combo PHY port uses
> one PCIe lane, and the other two ports each have two lanes.  All PCIe
> ports operate at 5 GT/second.
> 
> The PCIe PHYs must be configured using a value that can only be
> determined using the combo PHY, operating in PCIe mode.  To allow
> that PHY to be used for USB, the calibration step is performed by
> the PHY driver automatically at probe time.  Once this step is done,
> the PHY can be used for either PCIe or USB.
> 
> Version 2 of this series incorporates suggestions made during the
> review of version 1.  Specific highlights are detailed below.

With the issues mentioned in patch 4 fixed, this patchset works fine for 
me. That said I had to disable ASPM by passing pcie_aspm=off on the 
command line, as it is now enabled by default since 6.18-rc1 [1]. At 
this stage, I am not sure if it is an issue with my NVME drive or an 
issue with the controller.

Regards
Aurelien

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f3ac2ff14834a0aa056ee3ae0e4b8c641c579961

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                     http://aurel32.net

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2025-10-16 16:48 UTC|newest]

Thread overview: 120+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13 15:35 [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller Alex Elder
2025-10-13 15:35 ` Alex Elder
2025-10-13 15:35 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 1/7] dt-bindings: phy: spacemit: add SpacemiT PCIe/combo PHY Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-15 14:52   ` Rob Herring
2025-10-15 14:52     ` Rob Herring
2025-10-15 14:52     ` Rob Herring
2025-10-17 16:20     ` Alex Elder
2025-10-17 16:20       ` Alex Elder
2025-10-17 16:20       ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 2/7] dt-bindings: phy: spacemit: introduce PCIe PHY Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-15 16:41   ` Rob Herring (Arm)
2025-10-15 16:41     ` Rob Herring (Arm)
2025-10-15 16:41     ` Rob Herring (Arm)
2025-10-17 16:20     ` Alex Elder
2025-10-17 16:20       ` Alex Elder
2025-10-17 16:20       ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 3/7] dt-bindings: pci: spacemit: introduce PCIe host controller Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-14  1:55   ` Yao Zi
2025-10-14  1:55     ` Yao Zi
2025-10-14  1:55     ` Yao Zi
2025-10-14  1:57     ` Alex Elder
2025-10-14  1:57       ` Alex Elder
2025-10-14  1:57       ` Alex Elder
2025-10-15 16:47   ` Rob Herring
2025-10-15 16:47     ` Rob Herring
2025-10-15 16:47     ` Rob Herring
2025-10-17 16:20     ` Alex Elder
2025-10-17 16:20       ` Alex Elder
2025-10-17 16:20       ` Alex Elder
2025-10-26 16:38   ` Manivannan Sadhasivam
2025-10-26 16:38     ` Manivannan Sadhasivam
2025-10-26 16:38     ` Manivannan Sadhasivam
2025-10-27 22:24     ` Alex Elder
2025-10-27 22:24       ` Alex Elder
2025-10-27 22:24       ` Alex Elder
2025-10-28  5:58       ` Manivannan Sadhasivam
2025-10-28  5:58         ` Manivannan Sadhasivam
2025-10-28  5:58         ` Manivannan Sadhasivam
2025-10-30  0:10         ` Alex Elder
2025-10-30  0:10           ` Alex Elder
2025-10-30  0:10           ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 4/7] phy: spacemit: introduce PCIe/combo PHY Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-15 21:51   ` Aurelien Jarno
2025-10-15 21:51     ` Aurelien Jarno
2025-10-15 21:51     ` Aurelien Jarno
2025-10-17 16:21     ` Alex Elder
2025-10-17 16:21       ` Alex Elder
2025-10-17 16:21       ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 5/7] PCI: spacemit: introduce SpacemiT PCIe host driver Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-26 16:55   ` Manivannan Sadhasivam
2025-10-26 16:55     ` Manivannan Sadhasivam
2025-10-26 16:55     ` Manivannan Sadhasivam
2025-10-27 22:24     ` Alex Elder
2025-10-27 22:24       ` Alex Elder
2025-10-27 22:24       ` Alex Elder
2025-10-28  7:06       ` Manivannan Sadhasivam
2025-10-28  7:06         ` Manivannan Sadhasivam
2025-10-28  7:06         ` Manivannan Sadhasivam
2025-10-30  0:10         ` Alex Elder
2025-10-30  0:10           ` Alex Elder
2025-10-30  0:10           ` Alex Elder
2025-10-31  6:05           ` Manivannan Sadhasivam
2025-10-31  6:05             ` Manivannan Sadhasivam
2025-10-31  6:05             ` Manivannan Sadhasivam
2025-10-31 13:38             ` Alex Elder
2025-10-31 13:38               ` Alex Elder
2025-10-31 13:38               ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 6/7] riscv: dts: spacemit: add a PCIe regulator Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 7/7] riscv: dts: spacemit: PCIe and PHY-related updates Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-13 15:35   ` Alex Elder
2025-10-16 16:47 ` Aurelien Jarno [this message]
2025-10-16 16:47   ` [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller Aurelien Jarno
2025-10-16 16:47   ` Aurelien Jarno
2025-10-17 16:21   ` Alex Elder
2025-10-17 16:21     ` Alex Elder
2025-10-17 16:21     ` Alex Elder
2025-10-28 17:59     ` Aurelien Jarno
2025-10-28 17:59       ` Aurelien Jarno
2025-10-28 17:59       ` Aurelien Jarno
2025-10-28 18:42       ` Johannes Erdfelt
2025-10-28 18:42         ` Johannes Erdfelt
2025-10-28 18:42         ` Johannes Erdfelt
2025-10-28 19:10         ` Alex Elder
2025-10-28 19:10           ` Alex Elder
2025-10-28 19:10           ` Alex Elder
2025-10-28 20:48           ` Johannes Erdfelt
2025-10-28 20:48             ` Johannes Erdfelt
2025-10-28 20:48             ` Johannes Erdfelt
2025-10-28 20:49             ` Alex Elder
2025-10-28 20:49               ` Alex Elder
2025-10-28 20:49               ` Alex Elder
2025-10-30 16:41             ` Manivannan Sadhasivam
2025-10-30 16:41               ` Manivannan Sadhasivam
2025-10-30 16:41               ` Manivannan Sadhasivam
2025-10-30 17:49               ` Aurelien Jarno
2025-10-30 17:49                 ` Aurelien Jarno
2025-10-30 17:49                 ` Aurelien Jarno
2025-10-31  6:10                 ` Manivannan Sadhasivam
2025-10-31  6:10                   ` Manivannan Sadhasivam
2025-10-31  6:10                   ` Manivannan Sadhasivam
2025-11-03 16:42                   ` Alex Elder
2025-11-03 16:42                     ` Alex Elder
2025-11-03 16:42                     ` Alex Elder
2025-10-28 21:08           ` Aurelien Jarno
2025-10-28 21:08             ` Aurelien Jarno
2025-10-28 21:08             ` Aurelien Jarno

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