Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver

From: Randolph Lin <randolph@andestech.com>
To: Niklas Cassel <cassel@kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	<jingoohan1@gmail.com>, <mani@kernel.org>,
	<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,
	<robh@kernel.org>, <bhelgaas@google.com>, <krzk+dt@kernel.org>,
	<conor+dt@kernel.org>, <alex@ghiti.fr>, <aou@eecs.berkeley.edu>,
	<palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
	<ben717@andestech.com>, <inochiama@gmail.com>,
	<thippeswamy.havalige@amd.com>, <namcao@linutronix.de>,
	<shradha.t@samsung.com>, <pjw@kernel.org>,
	<randolph.sklin@gmail.com>, <tim609@andestech.com>,
	Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
Date: Mon, 20 Oct 2025 19:35:48 +0800	[thread overview]
Message-ID: <aPYehqSefwW_-pAI@swlinux02> (raw)
In-Reply-To: <aPDc-yclubiHbUcD@ryzen>

Hello Niklas,

On Thu, Oct 16, 2025 at 01:54:35PM +0200, Niklas Cassel wrote:
> [EXTERNAL MAIL]
> 
> Hello Randolph,
> 
> On Thu, Oct 16, 2025 at 07:12:36PM +0800, Randolph Lin wrote:
> > >
> > > Could we please get a better explaination than "satisfy platform-specific
> > > constraints" ?
> > >
> >
> > Due to this SoC design, only iATU regions with mapped addresses within the
> > 32-bits address range need to be programmed. However, this SoC has a design
> > limitation in which the maximum region size supported by a single iATU
> > entry is restricted to 4 GB, as it is based on a 32-bits address region.
> >
> > For most EP devices, we can only define one entry in the "ranges" property
> > of the devicetree that maps an address within the 32-bit range,
> > as shown below:
> >       ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>;
> >
> > For EP devices that require 64-bits address mapping (e.g., GPUs), BAR
> > resources cannot be assigned.
> > To support such devices, an additional entry for 64-bits address mapping is
> > required, as shown below:
> >       ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>,
> >                <0x43000000 0x1 0x00000000 0x1 0x00000000 0x7 0x00000000>;
> >
> > In the current common implementation, all ranges entries are programmed to
> > the iATU. However, the size of entry for 64-bit address mapping exceeds the
> > maximum region size that a single iATU entry can support. As a result, an
> > error is reported during iATU programming, showing that the size of 64-bit
> > address entry exceeds the region limit.
> 
> Note that each iATU can map up to IATU_LIMIT_ADDR_OFF_OUTBOUND_i +
> IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_i.
> 
> Some DWC controllers have this at 4G, others have this at 8G.
> 
> Samuel has submitted a patch to use multiple iATUs to support
> a window size larger than the iATU limit of a single iATU:
> https://lore.kernel.org/linux-pci/aPDObXsvMoz1OYso@ryzen/T/#m11c3d95215982411d0bbd36940e70122b70ae820
> 
> Perhaps this patch could be of use for you too?
>

Thank you for the information.
After applying Samuel’s patch, the code passes the basic functionality
tests. Therefore, the common code patch is no longer needed.

> 
> Kind regards,
> Niklas

Sincerely,
Randolph Lin