* [PATCH v6 0/5] Add support for Andes Qilai SoC PCIe controller
@ 2025-10-03 2:35 ` Randolph Lin
0 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
Add support for Andes Qilai SoC PCIe controller
These patches introduce driver support for the PCIe controller on the
Andes Qilai SoC.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
Changes in v6:
- Fix typo in the logic for adjusting the number of OB/IB windows
---
Changes in v5:
- Add support to adjust the number of OB/IB windows in the glue driver.
- Fix the number of OB windows in the Qilai PCIe driver.
- Remove meaningless properties from the device tree.
- Made minor adjustments based on the reviewer's suggestions.
---
Changes in v4:
- Add .post_init callback for enabling IOCP cache.
- Sort by vender name in Kconfig
- Using PROBE_PREFER_ASYNCHRONOUS as default probe type.
- Made minor adjustments based on the reviewer's suggestions.
---
Changes in v3:
- Remove outbound ATU address range validation callback and logic.
- Add logic to skip failed outbound iATU configuration and continue.
- Using PROBE_PREFER_ASYNCHRONOUS as default probe type.
- Made minor adjustments based on the reviewer's suggestions.
---
Changes in v2:
- Remove the patch that adds the dma-ranges property to the SoC node.
- Add dma-ranges to the PCIe parent node bus node.
- Refactor and rename outbound ATU address range validation callback and logic.
- Use parent_bus_offset instead of cpu_addr_fixup().
- Using PROBE_DEFAULT_STRATEGY as default probe type.
- Made minor adjustments based on the reviewer's suggestions.
Randolph Lin (5):
PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
dt-bindings: PCI: Add Andes QiLai PCIe support
riscv: dts: andes: Add PCIe node into the QiLai SoC
PCI: andes: Add Andes QiLai SoC PCIe host driver support
MAINTAINERS: Add maintainers for Andes QiLai PCIe driver
.../bindings/pci/andestech,qilai-pcie.yaml | 97 +++++++
MAINTAINERS | 7 +
arch/riscv/boot/dts/andes/qilai.dtsi | 106 ++++++++
drivers/pci/controller/dwc/Kconfig | 13 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-andes-qilai.c | 240 ++++++++++++++++++
drivers/pci/controller/dwc/pcie-designware.c | 12 +-
7 files changed, 474 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c
--
2.34.1
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
2025-10-03 2:35 ` Randolph Lin
@ 2025-10-03 2:35 ` Randolph Lin
-1 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
The number of ob/ib windows is determined through write-read loops
on registers in the core driver. Some glue drivers need to adjust
the number of ob/ib windows to meet specific requirements,such as
hardware limitations. This change allows the glue driver to adjust
the number of ob/ib windows to satisfy platform-specific constraints.
The glue driver may adjust the number of ob/ib windows, but the values
must stay within hardware limits.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 89aad5a08928..56c1e45adc06 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -907,8 +907,16 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
max = 0;
}
- pci->num_ob_windows = ob;
- pci->num_ib_windows = ib;
+ if (!pci->num_ob_windows)
+ pci->num_ob_windows = ob;
+ else if (pci->num_ob_windows > ob)
+ dev_err(pci->dev, "Adjusted ob windows exceed the limit\n");
+
+ if (!pci->num_ib_windows)
+ pci->num_ib_windows = ib;
+ else if (pci->num_ib_windows > ib)
+ dev_err(pci->dev, "Adjusted ib windows exceed the limit\n");
+
pci->region_align = 1 << fls(min);
pci->region_limit = (max << 32) | (SZ_4G - 1);
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
@ 2025-10-03 2:35 ` Randolph Lin
0 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
The number of ob/ib windows is determined through write-read loops
on registers in the core driver. Some glue drivers need to adjust
the number of ob/ib windows to meet specific requirements,such as
hardware limitations. This change allows the glue driver to adjust
the number of ob/ib windows to satisfy platform-specific constraints.
The glue driver may adjust the number of ob/ib windows, but the values
must stay within hardware limits.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 89aad5a08928..56c1e45adc06 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -907,8 +907,16 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
max = 0;
}
- pci->num_ob_windows = ob;
- pci->num_ib_windows = ib;
+ if (!pci->num_ob_windows)
+ pci->num_ob_windows = ob;
+ else if (pci->num_ob_windows > ob)
+ dev_err(pci->dev, "Adjusted ob windows exceed the limit\n");
+
+ if (!pci->num_ib_windows)
+ pci->num_ib_windows = ib;
+ else if (pci->num_ib_windows > ib)
+ dev_err(pci->dev, "Adjusted ib windows exceed the limit\n");
+
pci->region_align = 1 << fls(min);
pci->region_limit = (max << 32) | (SZ_4G - 1);
--
2.34.1
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
2025-10-03 2:35 ` Randolph Lin
@ 2025-10-14 9:43 ` Niklas Cassel
-1 siblings, 0 replies; 25+ messages in thread
From: Niklas Cassel @ 2025-10-14 9:43 UTC (permalink / raw)
To: Randolph Lin
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
mani, lpieralisi, kwilczynski, robh, bhelgaas, krzk+dt, conor+dt,
alex, aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, randolph.sklin,
tim609
On Fri, Oct 03, 2025 at 10:35:23AM +0800, Randolph Lin wrote:
> The number of ob/ib windows is determined through write-read loops
> on registers in the core driver. Some glue drivers need to adjust
> the number of ob/ib windows to meet specific requirements,such as
Missing space after comma.
> hardware limitations. This change allows the glue driver to adjust
> the number of ob/ib windows to satisfy platform-specific constraints.
> The glue driver may adjust the number of ob/ib windows, but the values
> must stay within hardware limits.
Could we please get a better explaination than "satisfy platform-specific
constraints" ?
Your PCIe controller is synthesized with a certain number of {in,out}bound
windows, and I assume that dw_pcie_iatu_detect() correctly detects the number
of {in,out}bound windows, and initializes num_ob_windows/num_ib_windows
accordingly.
So, is the problem that because of some errata, you cannot use all the
{in,out}bound windows of the iATU?
Because it is hard to understand what kind of "hardware limit" that would
cause your SoC to not be able to use all the available {in,out}bound windows.
Because it is simply a mapping in the iATU (internal Address Translation Unit).
In fact, in many cases, e.g. the NVMe EPF driver, then number of {in,out}bound
windows is a major limiting factor of how many outstanding I/Os you can have,
so usually, you really want to be able to use the maximum that the hardware
supports.
TL;DR: to modify this common code, I think your reasoning has to be more
detailed.
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
@ 2025-10-14 9:43 ` Niklas Cassel
0 siblings, 0 replies; 25+ messages in thread
From: Niklas Cassel @ 2025-10-14 9:43 UTC (permalink / raw)
To: Randolph Lin
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
mani, lpieralisi, kwilczynski, robh, bhelgaas, krzk+dt, conor+dt,
alex, aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, randolph.sklin,
tim609
On Fri, Oct 03, 2025 at 10:35:23AM +0800, Randolph Lin wrote:
> The number of ob/ib windows is determined through write-read loops
> on registers in the core driver. Some glue drivers need to adjust
> the number of ob/ib windows to meet specific requirements,such as
Missing space after comma.
> hardware limitations. This change allows the glue driver to adjust
> the number of ob/ib windows to satisfy platform-specific constraints.
> The glue driver may adjust the number of ob/ib windows, but the values
> must stay within hardware limits.
Could we please get a better explaination than "satisfy platform-specific
constraints" ?
Your PCIe controller is synthesized with a certain number of {in,out}bound
windows, and I assume that dw_pcie_iatu_detect() correctly detects the number
of {in,out}bound windows, and initializes num_ob_windows/num_ib_windows
accordingly.
So, is the problem that because of some errata, you cannot use all the
{in,out}bound windows of the iATU?
Because it is hard to understand what kind of "hardware limit" that would
cause your SoC to not be able to use all the available {in,out}bound windows.
Because it is simply a mapping in the iATU (internal Address Translation Unit).
In fact, in many cases, e.g. the NVMe EPF driver, then number of {in,out}bound
windows is a major limiting factor of how many outstanding I/Os you can have,
so usually, you really want to be able to use the maximum that the hardware
supports.
TL;DR: to modify this common code, I think your reasoning has to be more
detailed.
Kind regards,
Niklas
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
2025-10-14 9:43 ` Niklas Cassel
@ 2025-10-16 11:12 ` Randolph Lin
-1 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-16 11:12 UTC (permalink / raw)
To: Niklas Cassel
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
mani, lpieralisi, kwilczynski, robh, bhelgaas, krzk+dt, conor+dt,
alex, aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, randolph.sklin,
tim609
Hi Niklas,
On Tue, Oct 14, 2025 at 11:43:53AM +0200, Niklas Cassel wrote:
> [EXTERNAL MAIL]
>
> On Fri, Oct 03, 2025 at 10:35:23AM +0800, Randolph Lin wrote:
> > The number of ob/ib windows is determined through write-read loops
> > on registers in the core driver. Some glue drivers need to adjust
> > the number of ob/ib windows to meet specific requirements,such as
>
> Missing space after comma.
>
>
Thanks a lot. I will fix it in the next patch.
> > hardware limitations. This change allows the glue driver to adjust
> > the number of ob/ib windows to satisfy platform-specific constraints.
> > The glue driver may adjust the number of ob/ib windows, but the values
> > must stay within hardware limits.
>
> Could we please get a better explaination than "satisfy platform-specific
> constraints" ?
>
Due to this SoC design, only iATU regions with mapped addresses within the
32-bits address range need to be programmed. However, this SoC has a design
limitation in which the maximum region size supported by a single iATU
entry is restricted to 4 GB, as it is based on a 32-bits address region.
For most EP devices, we can only define one entry in the "ranges" property
of the devicetree that maps an address within the 32-bit range,
as shown below:
ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>;
For EP devices that require 64-bits address mapping (e.g., GPUs), BAR
resources cannot be assigned.
To support such devices, an additional entry for 64-bits address mapping is
required, as shown below:
ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>,
<0x43000000 0x1 0x00000000 0x1 0x00000000 0x7 0x00000000>;
In the current common implementation, all ranges entries are programmed to
the iATU. However, the size of entry for 64-bit address mapping exceeds the
maximum region size that a single iATU entry can support. As a result, an
error is reported during iATU programming, showing that the size of 64-bit
address entry exceeds the region limit.
In this SoC design, 64-bit addresses are hard-wired and can skip iATU
programming. Thus, the driver needs to recount the "ranges" entries whose
size fits within the 4GB platform limit.
There are four scenarios:
32-bits address, size < 4GB: program to iATU
64-bits address, size < 4GB: program to iATU
32-bits address, size > 4GB: assuming this condition does not exist
64-bits address, size > 4GB: skip case
We will recount how many outbound windows will be programmed to the iATU;
this is why we need to adjust the number of entries programmed to the iATU.
> Your PCIe controller is synthesized with a certain number of {in,out}bound
> windows, and I assume that dw_pcie_iatu_detect() correctly detects the number
> of {in,out}bound windows, and initializes num_ob_windows/num_ib_windows
> accordingly.
>
> So, is the problem that because of some errata, you cannot use all the
> {in,out}bound windows of the iATU?
>
Similar to the erratum, all inbound and outbound windows remain functional,
as long as each iATU entry complies with the 4 GB size constraint.
> Because it is hard to understand what kind of "hardware limit" that would
> cause your SoC to not be able to use all the available {in,out}bound windows.
>
> Because it is simply a mapping in the iATU (internal Address Translation Unit).
>
> In fact, in many cases, e.g. the NVMe EPF driver, then number of {in,out}bound
> windows is a major limiting factor of how many outstanding I/Os you can have,
> so usually, you really want to be able to use the maximum that the hardware
> supports.
>
>
> TL;DR: to modify this common code, I think your reasoning has to be more
> detailed.
>
I will include additional explanations along with the application scenarios of
this SoC, and refactor the commit message.
>
>
> Kind regards,
> Niklas
Sincerely,
Randolph
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
@ 2025-10-16 11:12 ` Randolph Lin
0 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-16 11:12 UTC (permalink / raw)
To: Niklas Cassel
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
mani, lpieralisi, kwilczynski, robh, bhelgaas, krzk+dt, conor+dt,
alex, aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, randolph.sklin,
tim609
Hi Niklas,
On Tue, Oct 14, 2025 at 11:43:53AM +0200, Niklas Cassel wrote:
> [EXTERNAL MAIL]
>
> On Fri, Oct 03, 2025 at 10:35:23AM +0800, Randolph Lin wrote:
> > The number of ob/ib windows is determined through write-read loops
> > on registers in the core driver. Some glue drivers need to adjust
> > the number of ob/ib windows to meet specific requirements,such as
>
> Missing space after comma.
>
>
Thanks a lot. I will fix it in the next patch.
> > hardware limitations. This change allows the glue driver to adjust
> > the number of ob/ib windows to satisfy platform-specific constraints.
> > The glue driver may adjust the number of ob/ib windows, but the values
> > must stay within hardware limits.
>
> Could we please get a better explaination than "satisfy platform-specific
> constraints" ?
>
Due to this SoC design, only iATU regions with mapped addresses within the
32-bits address range need to be programmed. However, this SoC has a design
limitation in which the maximum region size supported by a single iATU
entry is restricted to 4 GB, as it is based on a 32-bits address region.
For most EP devices, we can only define one entry in the "ranges" property
of the devicetree that maps an address within the 32-bit range,
as shown below:
ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>;
For EP devices that require 64-bits address mapping (e.g., GPUs), BAR
resources cannot be assigned.
To support such devices, an additional entry for 64-bits address mapping is
required, as shown below:
ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>,
<0x43000000 0x1 0x00000000 0x1 0x00000000 0x7 0x00000000>;
In the current common implementation, all ranges entries are programmed to
the iATU. However, the size of entry for 64-bit address mapping exceeds the
maximum region size that a single iATU entry can support. As a result, an
error is reported during iATU programming, showing that the size of 64-bit
address entry exceeds the region limit.
In this SoC design, 64-bit addresses are hard-wired and can skip iATU
programming. Thus, the driver needs to recount the "ranges" entries whose
size fits within the 4GB platform limit.
There are four scenarios:
32-bits address, size < 4GB: program to iATU
64-bits address, size < 4GB: program to iATU
32-bits address, size > 4GB: assuming this condition does not exist
64-bits address, size > 4GB: skip case
We will recount how many outbound windows will be programmed to the iATU;
this is why we need to adjust the number of entries programmed to the iATU.
> Your PCIe controller is synthesized with a certain number of {in,out}bound
> windows, and I assume that dw_pcie_iatu_detect() correctly detects the number
> of {in,out}bound windows, and initializes num_ob_windows/num_ib_windows
> accordingly.
>
> So, is the problem that because of some errata, you cannot use all the
> {in,out}bound windows of the iATU?
>
Similar to the erratum, all inbound and outbound windows remain functional,
as long as each iATU entry complies with the 4 GB size constraint.
> Because it is hard to understand what kind of "hardware limit" that would
> cause your SoC to not be able to use all the available {in,out}bound windows.
>
> Because it is simply a mapping in the iATU (internal Address Translation Unit).
>
> In fact, in many cases, e.g. the NVMe EPF driver, then number of {in,out}bound
> windows is a major limiting factor of how many outstanding I/Os you can have,
> so usually, you really want to be able to use the maximum that the hardware
> supports.
>
>
> TL;DR: to modify this common code, I think your reasoning has to be more
> detailed.
>
I will include additional explanations along with the application scenarios of
this SoC, and refactor the commit message.
>
>
> Kind regards,
> Niklas
Sincerely,
Randolph
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
2025-10-16 11:12 ` Randolph Lin
@ 2025-10-16 11:54 ` Niklas Cassel
-1 siblings, 0 replies; 25+ messages in thread
From: Niklas Cassel @ 2025-10-16 11:54 UTC (permalink / raw)
To: Randolph Lin
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
mani, lpieralisi, kwilczynski, robh, bhelgaas, krzk+dt, conor+dt,
alex, aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, randolph.sklin,
tim609, Samuel Holland
Hello Randolph,
On Thu, Oct 16, 2025 at 07:12:36PM +0800, Randolph Lin wrote:
> >
> > Could we please get a better explaination than "satisfy platform-specific
> > constraints" ?
> >
>
> Due to this SoC design, only iATU regions with mapped addresses within the
> 32-bits address range need to be programmed. However, this SoC has a design
> limitation in which the maximum region size supported by a single iATU
> entry is restricted to 4 GB, as it is based on a 32-bits address region.
>
> For most EP devices, we can only define one entry in the "ranges" property
> of the devicetree that maps an address within the 32-bit range,
> as shown below:
> ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>;
>
> For EP devices that require 64-bits address mapping (e.g., GPUs), BAR
> resources cannot be assigned.
> To support such devices, an additional entry for 64-bits address mapping is
> required, as shown below:
> ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>,
> <0x43000000 0x1 0x00000000 0x1 0x00000000 0x7 0x00000000>;
>
> In the current common implementation, all ranges entries are programmed to
> the iATU. However, the size of entry for 64-bit address mapping exceeds the
> maximum region size that a single iATU entry can support. As a result, an
> error is reported during iATU programming, showing that the size of 64-bit
> address entry exceeds the region limit.
Note that each iATU can map up to IATU_LIMIT_ADDR_OFF_OUTBOUND_i +
IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_i.
Some DWC controllers have this at 4G, others have this at 8G.
Samuel has submitted a patch to use multiple iATUs to support
a window size larger than the iATU limit of a single iATU:
https://lore.kernel.org/linux-pci/aPDObXsvMoz1OYso@ryzen/T/#m11c3d95215982411d0bbd36940e70122b70ae820
Perhaps this patch could be of use for you too?
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
@ 2025-10-16 11:54 ` Niklas Cassel
0 siblings, 0 replies; 25+ messages in thread
From: Niklas Cassel @ 2025-10-16 11:54 UTC (permalink / raw)
To: Randolph Lin
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
mani, lpieralisi, kwilczynski, robh, bhelgaas, krzk+dt, conor+dt,
alex, aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, randolph.sklin,
tim609, Samuel Holland
Hello Randolph,
On Thu, Oct 16, 2025 at 07:12:36PM +0800, Randolph Lin wrote:
> >
> > Could we please get a better explaination than "satisfy platform-specific
> > constraints" ?
> >
>
> Due to this SoC design, only iATU regions with mapped addresses within the
> 32-bits address range need to be programmed. However, this SoC has a design
> limitation in which the maximum region size supported by a single iATU
> entry is restricted to 4 GB, as it is based on a 32-bits address region.
>
> For most EP devices, we can only define one entry in the "ranges" property
> of the devicetree that maps an address within the 32-bit range,
> as shown below:
> ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>;
>
> For EP devices that require 64-bits address mapping (e.g., GPUs), BAR
> resources cannot be assigned.
> To support such devices, an additional entry for 64-bits address mapping is
> required, as shown below:
> ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>,
> <0x43000000 0x1 0x00000000 0x1 0x00000000 0x7 0x00000000>;
>
> In the current common implementation, all ranges entries are programmed to
> the iATU. However, the size of entry for 64-bit address mapping exceeds the
> maximum region size that a single iATU entry can support. As a result, an
> error is reported during iATU programming, showing that the size of 64-bit
> address entry exceeds the region limit.
Note that each iATU can map up to IATU_LIMIT_ADDR_OFF_OUTBOUND_i +
IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_i.
Some DWC controllers have this at 4G, others have this at 8G.
Samuel has submitted a patch to use multiple iATUs to support
a window size larger than the iATU limit of a single iATU:
https://lore.kernel.org/linux-pci/aPDObXsvMoz1OYso@ryzen/T/#m11c3d95215982411d0bbd36940e70122b70ae820
Perhaps this patch could be of use for you too?
Kind regards,
Niklas
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
2025-10-16 11:54 ` Niklas Cassel
@ 2025-10-20 11:35 ` Randolph Lin
-1 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-20 11:35 UTC (permalink / raw)
To: Niklas Cassel
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
mani, lpieralisi, kwilczynski, robh, bhelgaas, krzk+dt, conor+dt,
alex, aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, randolph.sklin,
tim609, Samuel Holland
Hello Niklas,
On Thu, Oct 16, 2025 at 01:54:35PM +0200, Niklas Cassel wrote:
> [EXTERNAL MAIL]
>
> Hello Randolph,
>
> On Thu, Oct 16, 2025 at 07:12:36PM +0800, Randolph Lin wrote:
> > >
> > > Could we please get a better explaination than "satisfy platform-specific
> > > constraints" ?
> > >
> >
> > Due to this SoC design, only iATU regions with mapped addresses within the
> > 32-bits address range need to be programmed. However, this SoC has a design
> > limitation in which the maximum region size supported by a single iATU
> > entry is restricted to 4 GB, as it is based on a 32-bits address region.
> >
> > For most EP devices, we can only define one entry in the "ranges" property
> > of the devicetree that maps an address within the 32-bit range,
> > as shown below:
> > ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>;
> >
> > For EP devices that require 64-bits address mapping (e.g., GPUs), BAR
> > resources cannot be assigned.
> > To support such devices, an additional entry for 64-bits address mapping is
> > required, as shown below:
> > ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>,
> > <0x43000000 0x1 0x00000000 0x1 0x00000000 0x7 0x00000000>;
> >
> > In the current common implementation, all ranges entries are programmed to
> > the iATU. However, the size of entry for 64-bit address mapping exceeds the
> > maximum region size that a single iATU entry can support. As a result, an
> > error is reported during iATU programming, showing that the size of 64-bit
> > address entry exceeds the region limit.
>
> Note that each iATU can map up to IATU_LIMIT_ADDR_OFF_OUTBOUND_i +
> IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_i.
>
> Some DWC controllers have this at 4G, others have this at 8G.
>
> Samuel has submitted a patch to use multiple iATUs to support
> a window size larger than the iATU limit of a single iATU:
> https://lore.kernel.org/linux-pci/aPDObXsvMoz1OYso@ryzen/T/#m11c3d95215982411d0bbd36940e70122b70ae820
>
> Perhaps this patch could be of use for you too?
>
Thank you for the information.
After applying Samuel’s patch, the code passes the basic functionality
tests. Therefore, the common code patch is no longer needed.
>
> Kind regards,
> Niklas
Sincerely,
Randolph Lin
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver
@ 2025-10-20 11:35 ` Randolph Lin
0 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-20 11:35 UTC (permalink / raw)
To: Niklas Cassel
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
mani, lpieralisi, kwilczynski, robh, bhelgaas, krzk+dt, conor+dt,
alex, aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, randolph.sklin,
tim609, Samuel Holland
Hello Niklas,
On Thu, Oct 16, 2025 at 01:54:35PM +0200, Niklas Cassel wrote:
> [EXTERNAL MAIL]
>
> Hello Randolph,
>
> On Thu, Oct 16, 2025 at 07:12:36PM +0800, Randolph Lin wrote:
> > >
> > > Could we please get a better explaination than "satisfy platform-specific
> > > constraints" ?
> > >
> >
> > Due to this SoC design, only iATU regions with mapped addresses within the
> > 32-bits address range need to be programmed. However, this SoC has a design
> > limitation in which the maximum region size supported by a single iATU
> > entry is restricted to 4 GB, as it is based on a 32-bits address region.
> >
> > For most EP devices, we can only define one entry in the "ranges" property
> > of the devicetree that maps an address within the 32-bit range,
> > as shown below:
> > ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>;
> >
> > For EP devices that require 64-bits address mapping (e.g., GPUs), BAR
> > resources cannot be assigned.
> > To support such devices, an additional entry for 64-bits address mapping is
> > required, as shown below:
> > ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>,
> > <0x43000000 0x1 0x00000000 0x1 0x00000000 0x7 0x00000000>;
> >
> > In the current common implementation, all ranges entries are programmed to
> > the iATU. However, the size of entry for 64-bit address mapping exceeds the
> > maximum region size that a single iATU entry can support. As a result, an
> > error is reported during iATU programming, showing that the size of 64-bit
> > address entry exceeds the region limit.
>
> Note that each iATU can map up to IATU_LIMIT_ADDR_OFF_OUTBOUND_i +
> IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_i.
>
> Some DWC controllers have this at 4G, others have this at 8G.
>
> Samuel has submitted a patch to use multiple iATUs to support
> a window size larger than the iATU limit of a single iATU:
> https://lore.kernel.org/linux-pci/aPDObXsvMoz1OYso@ryzen/T/#m11c3d95215982411d0bbd36940e70122b70ae820
>
> Perhaps this patch could be of use for you too?
>
Thank you for the information.
After applying Samuel’s patch, the code passes the basic functionality
tests. Therefore, the common code patch is no longer needed.
>
> Kind regards,
> Niklas
Sincerely,
Randolph Lin
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v6 2/5] dt-bindings: PCI: Add Andes QiLai PCIe support
2025-10-03 2:35 ` Randolph Lin
@ 2025-10-03 2:35 ` Randolph Lin
-1 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Only one example is required in the DTS bindings YAML file.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
.../bindings/pci/andestech,qilai-pcie.yaml | 97 +++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
new file mode 100644
index 000000000000..419468430e7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes QiLai PCIe host controller
+
+description:
+ Andes QiLai PCIe host controller is based on the Synopsys DesignWare
+ PCI core. It shares common features with the PCIe DesignWare core and
+ inherits common properties defined in
+ Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
+
+maintainers:
+ - Randolph Lin <randolph@andestech.com>
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ const: andestech,qilai-pcie
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: APB registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: apb
+ - const: config
+
+ ranges:
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupt-map: true
+
+required:
+ - reg
+ - reg-names
+ - "#interrupt-cells"
+ - interrupts
+ - interrupt-names
+ - interrupt-map-mask
+ - interrupt-map
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ bus@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@80000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x0 0x80000000 0x0 0x20000000>,
+ <0x0 0x04000000 0x0 0x00001000>,
+ <0x0 0x00000000 0x0 0x00010000>;
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x0000000 0x1f 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xf>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic0>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 2/5] dt-bindings: PCI: Add Andes QiLai PCIe support
@ 2025-10-03 2:35 ` Randolph Lin
0 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Only one example is required in the DTS bindings YAML file.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
.../bindings/pci/andestech,qilai-pcie.yaml | 97 +++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
new file mode 100644
index 000000000000..419468430e7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes QiLai PCIe host controller
+
+description:
+ Andes QiLai PCIe host controller is based on the Synopsys DesignWare
+ PCI core. It shares common features with the PCIe DesignWare core and
+ inherits common properties defined in
+ Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
+
+maintainers:
+ - Randolph Lin <randolph@andestech.com>
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ const: andestech,qilai-pcie
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: APB registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: apb
+ - const: config
+
+ ranges:
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupt-map: true
+
+required:
+ - reg
+ - reg-names
+ - "#interrupt-cells"
+ - interrupts
+ - interrupt-names
+ - interrupt-map-mask
+ - interrupt-map
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ bus@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@80000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x0 0x80000000 0x0 0x20000000>,
+ <0x0 0x04000000 0x0 0x00001000>,
+ <0x0 0x00000000 0x0 0x00010000>;
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x0000000 0x1f 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xf>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic0>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH v6 2/5] dt-bindings: PCI: Add Andes QiLai PCIe support
2025-10-03 2:35 ` Randolph Lin
@ 2025-10-06 18:52 ` Rob Herring
-1 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2025-10-06 18:52 UTC (permalink / raw)
To: Randolph Lin
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
mani, lpieralisi, kwilczynski, bhelgaas, krzk+dt, conor+dt, alex,
aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, randolph.sklin,
tim609
On Fri, Oct 03, 2025 at 10:35:24AM +0800, Randolph Lin wrote:
> Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
> Only one example is required in the DTS bindings YAML file.
>
> Signed-off-by: Randolph Lin <randolph@andestech.com>
> ---
> .../bindings/pci/andestech,qilai-pcie.yaml | 97 +++++++++++++++++++
> 1 file changed, 97 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
> new file mode 100644
> index 000000000000..419468430e7e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
> @@ -0,0 +1,97 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Andes QiLai PCIe host controller
> +
> +description:
> + Andes QiLai PCIe host controller is based on the Synopsys DesignWare
> + PCI core. It shares common features with the PCIe DesignWare core and
> + inherits common properties defined in
> + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
> +
> +maintainers:
> + - Randolph Lin <randolph@andestech.com>
> +
> +allOf:
> + - $ref: /schemas/pci/snps,dw-pcie.yaml#
> +
> +properties:
> + compatible:
> + const: andestech,qilai-pcie
> +
> + reg:
> + items:
> + - description: Data Bus Interface (DBI) registers.
> + - description: APB registers.
> + - description: PCIe configuration space region.
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: apb
> + - const: config
> +
> + ranges:
> + maxItems: 2
> +
> + interrupts:
> + maxItems: 1
> +
> + "#interrupt-cells":
> + const: 1
You can drop this. #interrupt-cells is already defined in
pci-bus-common.yaml.
> +
> + interrupt-map: true
> +
> +required:
> + - reg
> + - reg-names
> + - "#interrupt-cells"
> + - interrupts
> + - interrupt-names
> + - interrupt-map-mask
> + - interrupt-map
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + bus@80000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
Drop this node. No reason to show "simple-bus" in this example. Also it
fails checks:
Documentation/devicetree/bindings/pci/andestech,qilai-pcie.example.dts:30.24-59.13: Warning (unit_address_vs_reg): /example-0/soc/bus@80000000: node has a unit name, but no reg or ranges property
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.example.dtb: bus@80000000 (simple-bus): 'ranges' is a required property
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
> +
> + pcie@80000000 {
> + compatible = "andestech,qilai-pcie";
> + device_type = "pci";
> + reg = <0x0 0x80000000 0x0 0x20000000>,
> + <0x0 0x04000000 0x0 0x00001000>,
> + <0x0 0x00000000 0x0 0x00010000>;
> + reg-names = "dbi", "apb", "config";
> +
> + linux,pci-domain = <0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
> + <0x43000000 0x01 0x00000000 0x01 0x0000000 0x1f 0x00000000>;
> +
> + #interrupt-cells = <1>;
> + interrupts = <0xf>;
> + interrupt-names = "msi";
> + interrupt-parent = <&plic0>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v6 2/5] dt-bindings: PCI: Add Andes QiLai PCIe support
@ 2025-10-06 18:52 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2025-10-06 18:52 UTC (permalink / raw)
To: Randolph Lin
Cc: linux-kernel, linux-pci, linux-riscv, devicetree, jingoohan1,
mani, lpieralisi, kwilczynski, bhelgaas, krzk+dt, conor+dt, alex,
aou, palmer, paul.walmsley, ben717, inochiama,
thippeswamy.havalige, namcao, shradha.t, pjw, randolph.sklin,
tim609
On Fri, Oct 03, 2025 at 10:35:24AM +0800, Randolph Lin wrote:
> Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
> Only one example is required in the DTS bindings YAML file.
>
> Signed-off-by: Randolph Lin <randolph@andestech.com>
> ---
> .../bindings/pci/andestech,qilai-pcie.yaml | 97 +++++++++++++++++++
> 1 file changed, 97 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
> new file mode 100644
> index 000000000000..419468430e7e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
> @@ -0,0 +1,97 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Andes QiLai PCIe host controller
> +
> +description:
> + Andes QiLai PCIe host controller is based on the Synopsys DesignWare
> + PCI core. It shares common features with the PCIe DesignWare core and
> + inherits common properties defined in
> + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
> +
> +maintainers:
> + - Randolph Lin <randolph@andestech.com>
> +
> +allOf:
> + - $ref: /schemas/pci/snps,dw-pcie.yaml#
> +
> +properties:
> + compatible:
> + const: andestech,qilai-pcie
> +
> + reg:
> + items:
> + - description: Data Bus Interface (DBI) registers.
> + - description: APB registers.
> + - description: PCIe configuration space region.
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: apb
> + - const: config
> +
> + ranges:
> + maxItems: 2
> +
> + interrupts:
> + maxItems: 1
> +
> + "#interrupt-cells":
> + const: 1
You can drop this. #interrupt-cells is already defined in
pci-bus-common.yaml.
> +
> + interrupt-map: true
> +
> +required:
> + - reg
> + - reg-names
> + - "#interrupt-cells"
> + - interrupts
> + - interrupt-names
> + - interrupt-map-mask
> + - interrupt-map
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + bus@80000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
Drop this node. No reason to show "simple-bus" in this example. Also it
fails checks:
Documentation/devicetree/bindings/pci/andestech,qilai-pcie.example.dts:30.24-59.13: Warning (unit_address_vs_reg): /example-0/soc/bus@80000000: node has a unit name, but no reg or ranges property
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.example.dtb: bus@80000000 (simple-bus): 'ranges' is a required property
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
> +
> + pcie@80000000 {
> + compatible = "andestech,qilai-pcie";
> + device_type = "pci";
> + reg = <0x0 0x80000000 0x0 0x20000000>,
> + <0x0 0x04000000 0x0 0x00001000>,
> + <0x0 0x00000000 0x0 0x00010000>;
> + reg-names = "dbi", "apb", "config";
> +
> + linux,pci-domain = <0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
> + <0x43000000 0x01 0x00000000 0x01 0x0000000 0x1f 0x00000000>;
> +
> + #interrupt-cells = <1>;
> + interrupts = <0xf>;
> + interrupt-names = "msi";
> + interrupt-parent = <&plic0>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> --
> 2.34.1
>
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v6 3/5] riscv: dts: andes: Add PCIe node into the QiLai SoC
2025-10-03 2:35 ` Randolph Lin
@ 2025-10-03 2:35 ` Randolph Lin
-1 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
arch/riscv/boot/dts/andes/qilai.dtsi | 106 +++++++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
index de3de32f8c39..afa7b75a7e7a 100644
--- a/arch/riscv/boot/dts/andes/qilai.dtsi
+++ b/arch/riscv/boot/dts/andes/qilai.dtsi
@@ -182,5 +182,111 @@ uart0: serial@30300000 {
reg-io-width = <4>;
no-loopback-test;
};
+
+ bus@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x20000000>,
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x00001000>,
+ <0x00 0x00000000 0x20 0x00000000 0x20 0x00000000>;
+
+ pcie@80000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0x80000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04000000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x1f 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xf 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xf 0x4>,
+ <0 0 0 2 &plic 0xf 0x4>,
+ <0 0 0 3 &plic 0xf 0x4>,
+ <0 0 0 4 &plic 0xf 0x4>;
+ };
+ };
+
+ bus@a0000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0xa0000000 0x00 0xa0000000 0x00 0x20000000>,
+ <0x00 0x04001000 0x00 0x04001000 0x00 0x00001000>,
+ <0x00 0x00000000 0x10 0x00000000 0x08 0x00000000>;
+
+ pcie@a0000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0xa0000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04001000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xe 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xe 0x4>,
+ <0 0 0 2 &plic 0xe 0x4>,
+ <0 0 0 3 &plic 0xe 0x4>,
+ <0 0 0 4 &plic 0xe 0x4>;
+ };
+ };
+
+ bus@c0000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0xc0000000 0x00 0xc0000000 0x00 0x20000000>,
+ <0x00 0x04002000 0x00 0x04002000 0x00 0x00001000>,
+ <0x00 0x00000000 0x18 0x00000000 0x08 0x00000000>;
+
+ pcie@c0000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0xc0000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04002000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xd 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xd 0x4>,
+ <0 0 0 2 &plic 0xd 0x4>,
+ <0 0 0 3 &plic 0xd 0x4>,
+ <0 0 0 4 &plic 0xd 0x4>;
+ };
+ };
+
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 3/5] riscv: dts: andes: Add PCIe node into the QiLai SoC
@ 2025-10-03 2:35 ` Randolph Lin
0 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
arch/riscv/boot/dts/andes/qilai.dtsi | 106 +++++++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
index de3de32f8c39..afa7b75a7e7a 100644
--- a/arch/riscv/boot/dts/andes/qilai.dtsi
+++ b/arch/riscv/boot/dts/andes/qilai.dtsi
@@ -182,5 +182,111 @@ uart0: serial@30300000 {
reg-io-width = <4>;
no-loopback-test;
};
+
+ bus@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x20000000>,
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x00001000>,
+ <0x00 0x00000000 0x20 0x00000000 0x20 0x00000000>;
+
+ pcie@80000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0x80000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04000000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x1f 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xf 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xf 0x4>,
+ <0 0 0 2 &plic 0xf 0x4>,
+ <0 0 0 3 &plic 0xf 0x4>,
+ <0 0 0 4 &plic 0xf 0x4>;
+ };
+ };
+
+ bus@a0000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0xa0000000 0x00 0xa0000000 0x00 0x20000000>,
+ <0x00 0x04001000 0x00 0x04001000 0x00 0x00001000>,
+ <0x00 0x00000000 0x10 0x00000000 0x08 0x00000000>;
+
+ pcie@a0000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0xa0000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04001000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xe 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xe 0x4>,
+ <0 0 0 2 &plic 0xe 0x4>,
+ <0 0 0 3 &plic 0xe 0x4>,
+ <0 0 0 4 &plic 0xe 0x4>;
+ };
+ };
+
+ bus@c0000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0xc0000000 0x00 0xc0000000 0x00 0x20000000>,
+ <0x00 0x04002000 0x00 0x04002000 0x00 0x00001000>,
+ <0x00 0x00000000 0x18 0x00000000 0x08 0x00000000>;
+
+ pcie@c0000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0xc0000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04002000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xd 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xd 0x4>,
+ <0 0 0 2 &plic 0xd 0x4>,
+ <0 0 0 3 &plic 0xd 0x4>,
+ <0 0 0 4 &plic 0xd 0x4>;
+ };
+ };
+
};
};
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v6 4/5] PCI: andes: Add Andes QiLai SoC PCIe host driver support
2025-10-03 2:35 ` Randolph Lin
@ 2025-10-03 2:35 ` Randolph Lin
-1 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
Add driver support for DesignWare based PCIe controller in Andes
QiLai SoC. The driver only supports the Root Complex mode.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
drivers/pci/controller/dwc/Kconfig | 13 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-andes-qilai.c | 240 ++++++++++++++++++
3 files changed, 254 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index ff6b6d9e18ec..15cf19c9449f 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -60,6 +60,19 @@ config PCI_MESON
and therefore the driver re-uses the DesignWare core functions to
implement the driver.
+config PCIE_ANDES_QILAI
+ tristate "Andes QiLai PCIe controller"
+ depends on ARCH_ANDES || COMPILE_TEST
+ depends on PCI_MSI
+ select PCIE_DW_HOST
+ help
+ Say Y here to enable PCIe controller support on Andes QiLai SoCs,
+ which operate in Root Complex mode. The Andes QiLai SoC PCIe
+ controller is based on DesignWare IP (5.97a version) and therefore
+ the driver re-uses the DesignWare core functions to implement the
+ driver. The Andes QiLai SoC features three Root Complexes, each
+ operating on PCIe 4.0.
+
config PCIE_ARTPEC6
bool
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 6919d27798d1..de9583cbd675 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
+obj-$(CONFIG_PCIE_ANDES_QILAI) += pcie-andes-qilai.o
obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
diff --git a/drivers/pci/controller/dwc/pcie-andes-qilai.c b/drivers/pci/controller/dwc/pcie-andes-qilai.c
new file mode 100644
index 000000000000..fd1521a5e89c
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-andes-qilai.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the PCIe Controller in QiLai from Andes
+ *
+ * Copyright (C) 2025 Andes Technology Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+#include "pcie-designware.h"
+
+#define PCIE_INTR_CONTROL1 0x15c
+#define PCIE_MSI_CTRL_INT_EN BIT(28)
+
+#define PCIE_LOGIC_COHERENCY_CONTROL3 0x8e8
+
+/*
+ * Refer to Table A4-5 (Memory type encoding) in the
+ * AMBA AXI and ACE Protocol Specification.
+ *
+ * The selected value corresponds to the Memory type field:
+ * "Write-back, Read and Write-allocate".
+ *
+ * The last three rows in the table A4-5 in
+ * AMBA AXI and ACE Protocol Specification:
+ * ARCACHE AWCACHE Memory type
+ * ------------------------------------------------------------------
+ * 1111 (0111) 0111 Write-back Read-allocate
+ * 1011 1111 (1011) Write-back Write-allocate
+ * 1111 1111 Write-back Read and Write-allocate (selected)
+ */
+#define IOCP_ARCACHE 0b1111
+#define IOCP_AWCACHE 0b1111
+
+#define PCIE_CFG_MSTR_ARCACHE_MODE GENMASK(6, 3)
+#define PCIE_CFG_MSTR_AWCACHE_MODE GENMASK(14, 11)
+#define PCIE_CFG_MSTR_ARCACHE_VALUE GENMASK(22, 19)
+#define PCIE_CFG_MSTR_AWCACHE_VALUE GENMASK(30, 27)
+
+#define PCIE_GEN_CONTROL2 0x54
+#define PCIE_CFG_LTSSM_EN BIT(0)
+
+#define PCIE_REGS_PCIE_SII_PM_STATE 0xc0
+#define SMLH_LINK_UP BIT(6)
+#define RDLH_LINK_UP BIT(7)
+#define PCIE_REGS_PCIE_SII_LINK_UP (SMLH_LINK_UP | RDLH_LINK_UP)
+
+struct qilai_pcie {
+ struct dw_pcie pci;
+ void __iomem *apb_base;
+};
+
+#define to_qilai_pcie(_pci) container_of(_pci, struct qilai_pcie, pci)
+
+static bool qilai_pcie_link_up(struct dw_pcie *pci)
+{
+ struct qilai_pcie *pcie = to_qilai_pcie(pci);
+ u32 val;
+
+ /* Read smlh & rdlh link up by checking debug port */
+ val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE);
+
+ return (val & PCIE_REGS_PCIE_SII_LINK_UP) == PCIE_REGS_PCIE_SII_LINK_UP;
+}
+
+static int qilai_pcie_start_link(struct dw_pcie *pci)
+{
+ struct qilai_pcie *pcie = to_qilai_pcie(pci);
+ u32 val;
+
+ val = readl(pcie->apb_base + PCIE_GEN_CONTROL2);
+ val |= PCIE_CFG_LTSSM_EN;
+ writel(val, pcie->apb_base + PCIE_GEN_CONTROL2);
+
+ return 0;
+}
+
+static const struct dw_pcie_ops qilai_pcie_ops = {
+ .link_up = qilai_pcie_link_up,
+ .start_link = qilai_pcie_start_link,
+};
+
+/*
+ * Setup the Qilai PCIe IOCP (IO Coherence Port) Read/Write Behaviors to the
+ * Write-Back, Read and Write Allocate mode.
+ *
+ * The IOCP HW target is SoC last-level cache (L2 Cache), which serves as the
+ * system cache. The IOCP HW helps maintain cache monitoring, ensuring that
+ * the device can snoop data from/to the cache.
+ */
+static void qilai_pcie_iocp_cache_setup(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ u32 val;
+
+ dw_pcie_dbi_ro_wr_en(pci);
+
+ dw_pcie_read(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3,
+ sizeof(val), &val);
+ FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_MODE, &val, IOCP_ARCACHE);
+ FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_MODE, &val, IOCP_AWCACHE);
+ FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_VALUE, &val, IOCP_ARCACHE);
+ FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_VALUE, &val, IOCP_AWCACHE);
+ dw_pcie_write(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3,
+ sizeof(val), val);
+
+ dw_pcie_dbi_ro_wr_dis(pci);
+}
+
+static void qilai_pcie_enable_msi(struct qilai_pcie *pcie)
+{
+ u32 val;
+
+ val = readl(pcie->apb_base + PCIE_INTR_CONTROL1);
+ val |= PCIE_MSI_CTRL_INT_EN;
+ writel(val, pcie->apb_base + PCIE_INTR_CONTROL1);
+}
+
+/*
+ * The QiLai SoC PCIe controller's outbound iATU region supports
+ * a maximum size of SZ_4G - 1. To prevent programming failures,
+ * only consider bridge->windows with sizes within this limit.
+ *
+ * To ensure compatibility with most endpoint devices, at least
+ * one memory region must be mapped within the 32-bits address space.
+ */
+static int qilai_pcie_host_fix_ob_iatu_count(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct device *dev = pci->dev;
+ struct resource_entry *entry;
+ /* Reserved 1 ob iATU for config space */
+ int count = 1;
+ int ranges_32bits;
+ u64 pci_addr;
+ u64 size;
+
+ resource_list_for_each_entry(entry, &pp->bridge->windows) {
+ if (resource_type(entry->res) != IORESOURCE_MEM)
+ continue;
+
+ size = resource_size(entry->res);
+ if (size < SZ_4G)
+ count++;
+
+ pci_addr = entry->res->start - entry->offset;
+ if (pci_addr < SZ_4G)
+ ranges_32bits = true;
+ }
+
+ if (!ranges_32bits) {
+ dev_err(dev, "Bridge window must contain 32-bits address\n");
+ return -EINVAL;
+ }
+
+ pci->num_ob_windows = count;
+
+ return 0;
+}
+
+static int qilai_pcie_host_init(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct qilai_pcie *pcie = to_qilai_pcie(pci);
+
+ qilai_pcie_enable_msi(pcie);
+
+ return qilai_pcie_host_fix_ob_iatu_count(pp);
+}
+
+static void qilai_pcie_host_post_init(struct dw_pcie_rp *pp)
+{
+ qilai_pcie_iocp_cache_setup(pp);
+}
+
+static const struct dw_pcie_host_ops qilai_pcie_host_ops = {
+ .init = qilai_pcie_host_init,
+ .post_init = qilai_pcie_host_post_init,
+};
+
+static int qilai_pcie_probe(struct platform_device *pdev)
+{
+ struct qilai_pcie *pcie;
+ struct dw_pcie *pci;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pcie);
+
+ pci = &pcie->pci;
+ pcie->pci.dev = dev;
+ pcie->pci.ops = &qilai_pcie_ops;
+ pcie->pci.pp.ops = &qilai_pcie_host_ops;
+ pci->use_parent_dt_ranges = true;
+
+ dw_pcie_cap_set(&pcie->pci, REQ_RES);
+
+ pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
+ if (IS_ERR(pcie->apb_base))
+ return PTR_ERR(pcie->apb_base);
+
+ ret = dw_pcie_host_init(&pcie->pci.pp);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to initialize PCIe host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id qilai_pcie_of_match[] = {
+ { .compatible = "andestech,qilai-pcie" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, qilai_pcie_of_match);
+
+static struct platform_driver qilai_pcie_driver = {
+ .probe = qilai_pcie_probe,
+ .driver = {
+ .name = "qilai-pcie",
+ .of_match_table = qilai_pcie_of_match,
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ },
+};
+
+builtin_platform_driver(qilai_pcie_driver);
+
+MODULE_AUTHOR("Randolph Lin <randolph@andestech.com>");
+MODULE_DESCRIPTION("Andes Qilai PCIe driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 4/5] PCI: andes: Add Andes QiLai SoC PCIe host driver support
@ 2025-10-03 2:35 ` Randolph Lin
0 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
Add driver support for DesignWare based PCIe controller in Andes
QiLai SoC. The driver only supports the Root Complex mode.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
drivers/pci/controller/dwc/Kconfig | 13 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-andes-qilai.c | 240 ++++++++++++++++++
3 files changed, 254 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index ff6b6d9e18ec..15cf19c9449f 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -60,6 +60,19 @@ config PCI_MESON
and therefore the driver re-uses the DesignWare core functions to
implement the driver.
+config PCIE_ANDES_QILAI
+ tristate "Andes QiLai PCIe controller"
+ depends on ARCH_ANDES || COMPILE_TEST
+ depends on PCI_MSI
+ select PCIE_DW_HOST
+ help
+ Say Y here to enable PCIe controller support on Andes QiLai SoCs,
+ which operate in Root Complex mode. The Andes QiLai SoC PCIe
+ controller is based on DesignWare IP (5.97a version) and therefore
+ the driver re-uses the DesignWare core functions to implement the
+ driver. The Andes QiLai SoC features three Root Complexes, each
+ operating on PCIe 4.0.
+
config PCIE_ARTPEC6
bool
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 6919d27798d1..de9583cbd675 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
+obj-$(CONFIG_PCIE_ANDES_QILAI) += pcie-andes-qilai.o
obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
diff --git a/drivers/pci/controller/dwc/pcie-andes-qilai.c b/drivers/pci/controller/dwc/pcie-andes-qilai.c
new file mode 100644
index 000000000000..fd1521a5e89c
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-andes-qilai.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the PCIe Controller in QiLai from Andes
+ *
+ * Copyright (C) 2025 Andes Technology Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+#include "pcie-designware.h"
+
+#define PCIE_INTR_CONTROL1 0x15c
+#define PCIE_MSI_CTRL_INT_EN BIT(28)
+
+#define PCIE_LOGIC_COHERENCY_CONTROL3 0x8e8
+
+/*
+ * Refer to Table A4-5 (Memory type encoding) in the
+ * AMBA AXI and ACE Protocol Specification.
+ *
+ * The selected value corresponds to the Memory type field:
+ * "Write-back, Read and Write-allocate".
+ *
+ * The last three rows in the table A4-5 in
+ * AMBA AXI and ACE Protocol Specification:
+ * ARCACHE AWCACHE Memory type
+ * ------------------------------------------------------------------
+ * 1111 (0111) 0111 Write-back Read-allocate
+ * 1011 1111 (1011) Write-back Write-allocate
+ * 1111 1111 Write-back Read and Write-allocate (selected)
+ */
+#define IOCP_ARCACHE 0b1111
+#define IOCP_AWCACHE 0b1111
+
+#define PCIE_CFG_MSTR_ARCACHE_MODE GENMASK(6, 3)
+#define PCIE_CFG_MSTR_AWCACHE_MODE GENMASK(14, 11)
+#define PCIE_CFG_MSTR_ARCACHE_VALUE GENMASK(22, 19)
+#define PCIE_CFG_MSTR_AWCACHE_VALUE GENMASK(30, 27)
+
+#define PCIE_GEN_CONTROL2 0x54
+#define PCIE_CFG_LTSSM_EN BIT(0)
+
+#define PCIE_REGS_PCIE_SII_PM_STATE 0xc0
+#define SMLH_LINK_UP BIT(6)
+#define RDLH_LINK_UP BIT(7)
+#define PCIE_REGS_PCIE_SII_LINK_UP (SMLH_LINK_UP | RDLH_LINK_UP)
+
+struct qilai_pcie {
+ struct dw_pcie pci;
+ void __iomem *apb_base;
+};
+
+#define to_qilai_pcie(_pci) container_of(_pci, struct qilai_pcie, pci)
+
+static bool qilai_pcie_link_up(struct dw_pcie *pci)
+{
+ struct qilai_pcie *pcie = to_qilai_pcie(pci);
+ u32 val;
+
+ /* Read smlh & rdlh link up by checking debug port */
+ val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE);
+
+ return (val & PCIE_REGS_PCIE_SII_LINK_UP) == PCIE_REGS_PCIE_SII_LINK_UP;
+}
+
+static int qilai_pcie_start_link(struct dw_pcie *pci)
+{
+ struct qilai_pcie *pcie = to_qilai_pcie(pci);
+ u32 val;
+
+ val = readl(pcie->apb_base + PCIE_GEN_CONTROL2);
+ val |= PCIE_CFG_LTSSM_EN;
+ writel(val, pcie->apb_base + PCIE_GEN_CONTROL2);
+
+ return 0;
+}
+
+static const struct dw_pcie_ops qilai_pcie_ops = {
+ .link_up = qilai_pcie_link_up,
+ .start_link = qilai_pcie_start_link,
+};
+
+/*
+ * Setup the Qilai PCIe IOCP (IO Coherence Port) Read/Write Behaviors to the
+ * Write-Back, Read and Write Allocate mode.
+ *
+ * The IOCP HW target is SoC last-level cache (L2 Cache), which serves as the
+ * system cache. The IOCP HW helps maintain cache monitoring, ensuring that
+ * the device can snoop data from/to the cache.
+ */
+static void qilai_pcie_iocp_cache_setup(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ u32 val;
+
+ dw_pcie_dbi_ro_wr_en(pci);
+
+ dw_pcie_read(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3,
+ sizeof(val), &val);
+ FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_MODE, &val, IOCP_ARCACHE);
+ FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_MODE, &val, IOCP_AWCACHE);
+ FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_VALUE, &val, IOCP_ARCACHE);
+ FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_VALUE, &val, IOCP_AWCACHE);
+ dw_pcie_write(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3,
+ sizeof(val), val);
+
+ dw_pcie_dbi_ro_wr_dis(pci);
+}
+
+static void qilai_pcie_enable_msi(struct qilai_pcie *pcie)
+{
+ u32 val;
+
+ val = readl(pcie->apb_base + PCIE_INTR_CONTROL1);
+ val |= PCIE_MSI_CTRL_INT_EN;
+ writel(val, pcie->apb_base + PCIE_INTR_CONTROL1);
+}
+
+/*
+ * The QiLai SoC PCIe controller's outbound iATU region supports
+ * a maximum size of SZ_4G - 1. To prevent programming failures,
+ * only consider bridge->windows with sizes within this limit.
+ *
+ * To ensure compatibility with most endpoint devices, at least
+ * one memory region must be mapped within the 32-bits address space.
+ */
+static int qilai_pcie_host_fix_ob_iatu_count(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct device *dev = pci->dev;
+ struct resource_entry *entry;
+ /* Reserved 1 ob iATU for config space */
+ int count = 1;
+ int ranges_32bits;
+ u64 pci_addr;
+ u64 size;
+
+ resource_list_for_each_entry(entry, &pp->bridge->windows) {
+ if (resource_type(entry->res) != IORESOURCE_MEM)
+ continue;
+
+ size = resource_size(entry->res);
+ if (size < SZ_4G)
+ count++;
+
+ pci_addr = entry->res->start - entry->offset;
+ if (pci_addr < SZ_4G)
+ ranges_32bits = true;
+ }
+
+ if (!ranges_32bits) {
+ dev_err(dev, "Bridge window must contain 32-bits address\n");
+ return -EINVAL;
+ }
+
+ pci->num_ob_windows = count;
+
+ return 0;
+}
+
+static int qilai_pcie_host_init(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct qilai_pcie *pcie = to_qilai_pcie(pci);
+
+ qilai_pcie_enable_msi(pcie);
+
+ return qilai_pcie_host_fix_ob_iatu_count(pp);
+}
+
+static void qilai_pcie_host_post_init(struct dw_pcie_rp *pp)
+{
+ qilai_pcie_iocp_cache_setup(pp);
+}
+
+static const struct dw_pcie_host_ops qilai_pcie_host_ops = {
+ .init = qilai_pcie_host_init,
+ .post_init = qilai_pcie_host_post_init,
+};
+
+static int qilai_pcie_probe(struct platform_device *pdev)
+{
+ struct qilai_pcie *pcie;
+ struct dw_pcie *pci;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pcie);
+
+ pci = &pcie->pci;
+ pcie->pci.dev = dev;
+ pcie->pci.ops = &qilai_pcie_ops;
+ pcie->pci.pp.ops = &qilai_pcie_host_ops;
+ pci->use_parent_dt_ranges = true;
+
+ dw_pcie_cap_set(&pcie->pci, REQ_RES);
+
+ pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
+ if (IS_ERR(pcie->apb_base))
+ return PTR_ERR(pcie->apb_base);
+
+ ret = dw_pcie_host_init(&pcie->pci.pp);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to initialize PCIe host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id qilai_pcie_of_match[] = {
+ { .compatible = "andestech,qilai-pcie" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, qilai_pcie_of_match);
+
+static struct platform_driver qilai_pcie_driver = {
+ .probe = qilai_pcie_probe,
+ .driver = {
+ .name = "qilai-pcie",
+ .of_match_table = qilai_pcie_of_match,
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ },
+};
+
+builtin_platform_driver(qilai_pcie_driver);
+
+MODULE_AUTHOR("Randolph Lin <randolph@andestech.com>");
+MODULE_DESCRIPTION("Andes Qilai PCIe driver");
+MODULE_LICENSE("GPL");
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v6 5/5] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver
2025-10-03 2:35 ` Randolph Lin
@ 2025-10-03 2:35 ` Randolph Lin
-1 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
Here add maintainer information for Andes QiLai PCIe driver.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 49aace3381cd..6f6021863e7d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19401,6 +19401,13 @@ S: Supported
F: Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
F: drivers/pci/controller/pcie-altera.c
+PCI DRIVER FOR ANDES QILAI PCIE
+M: Randolph Lin <randolph@andestech.com>
+L: linux-pci@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
+F: drivers/pci/controller/dwc/pcie-andes-qilai.c
+
PCI DRIVER FOR APPLIEDMICRO XGENE
M: Toan Le <toan@os.amperecomputing.com>
L: linux-pci@vger.kernel.org
--
2.34.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v6 5/5] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver
@ 2025-10-03 2:35 ` Randolph Lin
0 siblings, 0 replies; 25+ messages in thread
From: Randolph Lin @ 2025-10-03 2:35 UTC (permalink / raw)
To: linux-kernel
Cc: linux-pci, linux-riscv, devicetree, jingoohan1, mani, lpieralisi,
kwilczynski, robh, bhelgaas, krzk+dt, conor+dt, alex, aou, palmer,
paul.walmsley, ben717, inochiama, thippeswamy.havalige, namcao,
shradha.t, pjw, randolph.sklin, tim609, Randolph Lin
Here add maintainer information for Andes QiLai PCIe driver.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 49aace3381cd..6f6021863e7d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19401,6 +19401,13 @@ S: Supported
F: Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
F: drivers/pci/controller/pcie-altera.c
+PCI DRIVER FOR ANDES QILAI PCIE
+M: Randolph Lin <randolph@andestech.com>
+L: linux-pci@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
+F: drivers/pci/controller/dwc/pcie-andes-qilai.c
+
PCI DRIVER FOR APPLIEDMICRO XGENE
M: Toan Le <toan@os.amperecomputing.com>
L: linux-pci@vger.kernel.org
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 25+ messages in thread