Re: [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext

From: Drew Fustini <fustini@kernel.org>
To: "Radim Krčmář" <rkrcmar@ventanamicro.com>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Conor Dooley" <conor@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Kornel Dulęba" <mindal@semihalf.com>,
	"Adrien Ricciardi" <aricciardi@baylibre.com>,
	"James Morse" <james.morse@arm.com>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Atish Patra" <atish.patra@linux.dev>,
	"Vasudevan Srinivasan" <vasu@rivosinc.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org,
	linux-riscv <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext
Date: Fri, 7 Nov 2025 09:44:17 -0800	[thread overview]
Message-ID: <aQ4v8QhQjRYrxNK3@x1> (raw)
In-Reply-To: <DDH2Q0N2HLKF.2QSW4DB5FTJI6@ventanamicro.com>

On Mon, Oct 13, 2025 at 11:06:50AM +0200, Radim Krčmář wrote:
> 2025-10-11T11:35:46-07:00, Drew Fustini <fustini@kernel.org>:
> > On Thu, Oct 09, 2025 at 08:47:27AM +0200, Radim Krčmář wrote:
> >> 2025-10-07T23:21:12-07:00, Drew Fustini <fustini@kernel.org>:
> >> > diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h
> >> > +static inline void __switch_to_srmcfg(struct task_struct *next)
> >> > +{
> >> > +	u32 *cpu_srmcfg_ptr = this_cpu_ptr(&cpu_srmcfg);
> >> > +	u32 thread_srmcfg;
> >> > +
> >> > +	thread_srmcfg = READ_ONCE(next->thread.srmcfg);
> >> > +
> >> > +	if (thread_srmcfg != *cpu_srmcfg_ptr) {
> >> 
> >> Wouldn't prev->thread.srmcfg have the value of CSR_SRMCFG when executing
> >> switch_to?
> >
> > Thanks for reviewing. Yes, you are right that prev->thread.srmcfg should
> > have same value as CSR_SRMCFG. Are you suggesting that the cpu_srmcfg is
> > not necessary as prev->thread.srmcfg should have same value?
> 
> Yes, it would be more consistent with other context switched state.
> I just wasn't sure if srmcfg doesn't have special race conditions.

I did some testing and the per-cpu cache of CSR_SRMCFG is needed. This
is because thread.srmcfg is changed asynchronously from when CSR_SRMCFG
is updated in __switch_to_srmcfg.

The srmcfg value for a thread is updated when a user writes the pid to a
control group's tasks file in the resctrl virtual filesystem:

void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32 rmid)
{
       u32 srmcfg;

       WARN_ON_ONCE((closid & SRMCFG_RCID_MASK) != closid);
       WARN_ON_ONCE((rmid & SRMCFG_MCID_MASK) != rmid);

       srmcfg = rmid << SRMCFG_MCID_SHIFT;
       srmcfg |= closid;
       WRITE_ONCE(tsk->thread.srmcfg, srmcfg);
}

I'm getting a full patch series ready that has both the Ssqosid and the
CBQRI resctrl patches, and I will post that soon. I'm also preparing
a freshly rebased Qemu series that adds the CBQRI controllers.

Thanks,
Drew

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