From: Yao Zi <ziyao@disroot.org>
To: Drew Fustini <fustini@kernel.org>
Cc: Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
devicetree@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-clk@vger.kernel.org, Guo Ren <guoren@kernel.org>,
Han Gao <rabenda.cn@gmail.com>, Han Gao <gaohan@iscas.ac.cn>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <pjw@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Fu Wei <wefu@redhat.com>
Subject: Re: [PATCH 2/7] clk: thead: th1520-ap: Poll for PLL lock and wait for stability
Date: Wed, 26 Nov 2025 15:16:54 +0000 [thread overview]
Message-ID: <aScZ5mwesY3wQTQl@pie> (raw)
In-Reply-To: <aScUELnY-TC8kVzV@gen8>
On Wed, Nov 26, 2025 at 08:52:00AM -0600, Drew Fustini wrote:
> On Thu, Nov 20, 2025 at 01:14:11PM +0000, Yao Zi wrote:
> > All PLLs found on TH1520 SoC take 21250ns at maximum to lock, and their
> > lock status is indicated by register PLL_STS (offset 0x80 inside AP
> > clock controller). We should poll the register to ensure the PLL
> > actually locks after enabling it.
> >
> > Furthermore, a 30us delay is added after enabling the PLL, after which
> > the PLL could be considered stable as stated by vendor clock code.
> >
> > Fixes: 56a48c1833aa ("clk: thead: add support for enabling/disabling PLLs")
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> > drivers/clk/thead/clk-th1520-ap.c | 34 +++++++++++++++++++++++++++++--
> > 1 file changed, 32 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
> [...]
> > +/*
> > + * All PLLs in TH1520 take 21250ns at maximum to lock, let's take its double
> > + * for safety.
> > + */
> > +#define TH1520_PLL_LOCK_TIMEOUT_US 44
> > +#define TH1520_PLL_STABLE_DELAY_US 30
>
> I'm taking a second look at this and I think it might be best to add a
> define for the polling loop delay of 5. It could be helpful when other
> people read the code later.
>
> [...]
> > + ret = regmap_read_poll_timeout_atomic(pll->common.map, TH1520_PLL_STS,
> > + reg, reg & pll->lock_sts_mask,
> > + 5, TH1520_PLL_LOCK_TIMEOUT_US);
>
> The loop delay is only used here but I think using a #define would make
> it more readable.
There are TH1520_PLL_LOCK_TIMEOUT_US and TH1520_PLL_STABLE_DELAY_US
defined because they're meaningful constants, either specified by TRM or
implied by vendor code, however the 5us delay is only a randomly-picked
value, as what I've mentioned before.
Anyway, I'm fine with a separate definition. So please go ahead if it
looks better to you.
> Other than that:
> Reviewed-by: Drew Fustini <fustini@kernel.org>
>
> If no other changes are needed I could fix this up on apply. Let's see
> what other comments there may be. It's too late for me to send a 6.19
> clk pull request so this will have to target the next merge window. I
> can put it into linux-next once 6.19-rc1 is released.
Many thanks for it.
> Thanks,
> Drew
Best regards,
Yao Zi
WARNING: multiple messages have this Message-ID (diff)
From: Yao Zi <ziyao@disroot.org>
To: Drew Fustini <fustini@kernel.org>
Cc: Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
devicetree@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-clk@vger.kernel.org, Guo Ren <guoren@kernel.org>,
Han Gao <rabenda.cn@gmail.com>, Han Gao <gaohan@iscas.ac.cn>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <pjw@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Fu Wei <wefu@redhat.com>
Subject: Re: [PATCH 2/7] clk: thead: th1520-ap: Poll for PLL lock and wait for stability
Date: Wed, 26 Nov 2025 15:16:54 +0000 [thread overview]
Message-ID: <aScZ5mwesY3wQTQl@pie> (raw)
In-Reply-To: <aScUELnY-TC8kVzV@gen8>
On Wed, Nov 26, 2025 at 08:52:00AM -0600, Drew Fustini wrote:
> On Thu, Nov 20, 2025 at 01:14:11PM +0000, Yao Zi wrote:
> > All PLLs found on TH1520 SoC take 21250ns at maximum to lock, and their
> > lock status is indicated by register PLL_STS (offset 0x80 inside AP
> > clock controller). We should poll the register to ensure the PLL
> > actually locks after enabling it.
> >
> > Furthermore, a 30us delay is added after enabling the PLL, after which
> > the PLL could be considered stable as stated by vendor clock code.
> >
> > Fixes: 56a48c1833aa ("clk: thead: add support for enabling/disabling PLLs")
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> > drivers/clk/thead/clk-th1520-ap.c | 34 +++++++++++++++++++++++++++++--
> > 1 file changed, 32 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
> [...]
> > +/*
> > + * All PLLs in TH1520 take 21250ns at maximum to lock, let's take its double
> > + * for safety.
> > + */
> > +#define TH1520_PLL_LOCK_TIMEOUT_US 44
> > +#define TH1520_PLL_STABLE_DELAY_US 30
>
> I'm taking a second look at this and I think it might be best to add a
> define for the polling loop delay of 5. It could be helpful when other
> people read the code later.
>
> [...]
> > + ret = regmap_read_poll_timeout_atomic(pll->common.map, TH1520_PLL_STS,
> > + reg, reg & pll->lock_sts_mask,
> > + 5, TH1520_PLL_LOCK_TIMEOUT_US);
>
> The loop delay is only used here but I think using a #define would make
> it more readable.
There are TH1520_PLL_LOCK_TIMEOUT_US and TH1520_PLL_STABLE_DELAY_US
defined because they're meaningful constants, either specified by TRM or
implied by vendor code, however the 5us delay is only a randomly-picked
value, as what I've mentioned before.
Anyway, I'm fine with a separate definition. So please go ahead if it
looks better to you.
> Other than that:
> Reviewed-by: Drew Fustini <fustini@kernel.org>
>
> If no other changes are needed I could fix this up on apply. Let's see
> what other comments there may be. It's too late for me to send a 6.19
> clk pull request so this will have to target the next merge window. I
> can put it into linux-next once 6.19-rc1 is released.
Many thanks for it.
> Thanks,
> Drew
Best regards,
Yao Zi
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next prev parent reply other threads:[~2025-11-26 15:17 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-20 13:14 [PATCH 0/7] Implement CPU frequency scaling for TH1520 Yao Zi
2025-11-20 13:14 ` Yao Zi
2025-11-20 13:14 ` [PATCH 1/7] dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock Yao Zi
2025-11-20 13:14 ` Yao Zi
2025-11-20 18:01 ` Conor Dooley
2025-11-20 18:01 ` Conor Dooley
2025-11-20 13:14 ` [PATCH 2/7] clk: thead: th1520-ap: Poll for PLL lock and wait for stability Yao Zi
2025-11-20 13:14 ` Yao Zi
2025-11-24 22:08 ` Drew Fustini
2025-11-24 22:08 ` Drew Fustini
2025-11-25 3:19 ` Yao Zi
2025-11-25 3:19 ` Yao Zi
2025-11-26 14:39 ` Drew Fustini
2025-11-26 14:39 ` Drew Fustini
2025-11-26 14:52 ` Drew Fustini
2025-11-26 14:52 ` Drew Fustini
2025-11-26 15:16 ` Yao Zi [this message]
2025-11-26 15:16 ` Yao Zi
2025-11-20 13:14 ` [PATCH 3/7] clk: thead: th1520-ap: Add C910 bus clock Yao Zi
2025-11-20 13:14 ` Yao Zi
2025-11-26 15:46 ` Drew Fustini
2025-11-26 15:46 ` Drew Fustini
2025-11-20 13:14 ` [PATCH 4/7] clk: thead: th1520-ap: Support setting PLL rates Yao Zi
2025-11-20 13:14 ` Yao Zi
2025-11-26 15:46 ` Drew Fustini
2025-11-26 15:46 ` Drew Fustini
2025-11-20 13:14 ` [PATCH 5/7] clk: thead: th1520-ap: Add macro to define multiplexers with flags Yao Zi
2025-11-20 13:14 ` Yao Zi
2025-11-24 22:14 ` Drew Fustini
2025-11-24 22:14 ` Drew Fustini
2025-11-25 3:25 ` Yao Zi
2025-11-25 3:25 ` Yao Zi
2025-11-26 15:47 ` Drew Fustini
2025-11-26 15:47 ` Drew Fustini
2025-11-20 13:14 ` [PATCH 6/7] clk: thead: th1520-ap: Support CPU frequency scaling Yao Zi
2025-11-20 13:14 ` Yao Zi
2025-11-27 20:33 ` Drew Fustini
2025-11-27 20:33 ` Drew Fustini
2025-11-20 13:14 ` [PATCH 7/7] [Not For Upstream] riscv: dts: thead: Add CPU clock and OPP table for TH1520 Yao Zi
2025-11-20 13:14 ` Yao Zi
2025-12-19 19:32 ` [PATCH 0/7] Implement CPU frequency scaling " Drew Fustini
2025-12-19 19:32 ` Drew Fustini
2026-01-15 1:50 ` Drew Fustini
2026-01-15 1:50 ` Drew Fustini
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