[PATCH 0/2] RISC-V: implement private GCC library

[PATCH 0/2] RISC-V: implement private GCC library

[Heinrich Schuchardt]

We currently include libgcc.a when building for the RISC-V architecture.
For instance lib/mbedtls/external/mbedtls/library/bignum.c uses __ctzdi2().

At least the Ubuntu Linux distribution has switched to building libgcc.a
for the RVA23S64 profile. Using this library on RVA20 systems results in
crashes. We therefore need a private replacement library.

With the series a private GCC library and unit tests are provided for
64-bit RISC-V. This is enough to build for CONFIG_WGET_HTTPS as suggested
in E's patch

[PATCH] configs: starfive: enable wget https
https://lore.kernel.org/u-boot/20251112005451.41285-1-e@freeshell.de/

Heinrich Schuchardt (2):
  RISC-V: implement private GCC library
  test: provide unit tests for the RISC-V private GCC library

 arch/Kconfig            |   1 +
 arch/riscv/lib/Makefile |   2 +
 arch/riscv/lib/clz.c    | 105 ++++++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/ctz.c    |  97 +++++++++++++++++++++++++++++++++++++
 lib/Kconfig             |   2 +-
 test/lib/Makefile       |   4 ++
 test/lib/test_clz.c     |  53 ++++++++++++++++++++
 test/lib/test_ctz.c     |  53 ++++++++++++++++++++
 8 files changed, 316 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/lib/clz.c
 create mode 100644 arch/riscv/lib/ctz.c
 create mode 100644 test/lib/test_clz.c
 create mode 100644 test/lib/test_ctz.c

-- 
2.51.0

[PATCH 1/2] RISC-V: implement private GCC library

[Heinrich Schuchardt]

From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

The following functions are provided:

Count leading zero bits

* int __clzsi2 (unsigned int a)
* int __clzdi2 (unsigned long a)
* int __clzti2 (unsigned long long a)

Count trailing zero bits

* int __ctzsi2 (unsigned int a)
* int __ctzdi2 (unsigned long a)
* int __ctzti2 (unsigned long long a)

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Heinrich Schuchardt <zfsdt@canonical.com>
---
 arch/Kconfig            |   1 +
 arch/riscv/lib/Makefile |   2 +
 arch/riscv/lib/clz.c    | 105 ++++++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/ctz.c    |  95 ++++++++++++++++++++++++++++++++++++
 lib/Kconfig             |   2 +-
 5 files changed, 204 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/lib/clz.c
 create mode 100644 arch/riscv/lib/ctz.c

diff --git a/arch/Kconfig b/arch/Kconfig
index 3133f892f94..4af0da2485f 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -159,6 +159,7 @@ config PPC
 config RISCV
 	bool "RISC-V architecture"
 	select CREATE_ARCH_SYMLINK
+	select HAVE_PRIVATE_LIBGCC if 64BIT
 	select HAVE_SETJMP
 	select HAVE_INITJMP
 	select SUPPORT_ACPI
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index f1f50918eff..a527b3e9ae3 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -6,6 +6,8 @@
 # Copyright (C) 2017 Andes Technology Corporation
 # Rick Chen, Andes Technology Corporation <rick@andestech.com>
 
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += clz.o ctz.o
+
 obj-$(CONFIG_$(PHASE_)LIB_BOOTM) += bootm.o
 obj-$(CONFIG_$(PHASE_)LIB_BOOTI) += image.o
 obj-$(CONFIG_CMD_GO) += boot.o
diff --git a/arch/riscv/lib/clz.c b/arch/riscv/lib/clz.c
new file mode 100644
index 00000000000..7b173d3c858
--- /dev/null
+++ b/arch/riscv/lib/clz.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * libgcc replacement - count leading bits
+ *
+ * Copyright 2025, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+ */
+
+#include <linux/types.h>
+
+/**
+ * __clzti2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzti2(long long x)
+{
+	int ret = 64;
+
+	if (!x)
+		return 64;
+
+	if (x & 0xFFFFFFFF00000000LL) {
+		ret -= 32;
+		x >>= 32;
+	}
+	if (x & 0xFFFF0000LL) {
+		ret -= 16;
+		x >>= 16;
+	}
+	if (x & 0xFF00LL) {
+		ret -= 8;
+		x >>= 8;
+	}
+	if (x & 0xF0LL) {
+		ret -= 4;
+		x >>= 4;
+	}
+	if (x & 0xCLL) {
+		ret -= 2;
+		x >>= 2;
+	}
+	if (x & 0x2LL) {
+		ret -= 1;
+		x >>= 1;
+	}
+	if (x)
+		ret -= 1;
+
+	return ret;
+}
+
+/**
+ * __clzsi2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzsi2(int x)
+{
+	int ret = 32;
+
+	if (!x)
+		return 32;
+
+	if (x & 0xFFFF0000) {
+		ret -= 16;
+		x >>= 16;
+	}
+	if (x & 0xFF00) {
+		ret -= 8;
+		x >>= 8;
+	}
+	if (x & 0xF0) {
+		ret -= 4;
+		x >>= 4;
+	}
+	if (x & 0xC) {
+		ret -= 2;
+		x >>= 2;
+	}
+	if (x & 0x2) {
+		ret -= 1;
+		x >>= 1;
+	}
+	if (x)
+		ret -= 1;
+
+	return ret;
+}
+
+/**
+ * __clzdi2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzdi2(long x)
+{
+#if BITS_PER_LONG == 64
+	return __clzti2(x);
+#else
+	return __clzsi2(x);
+#endif
+}
diff --git a/arch/riscv/lib/ctz.c b/arch/riscv/lib/ctz.c
new file mode 100644
index 00000000000..6c875e39f0e
--- /dev/null
+++ b/arch/riscv/lib/ctz.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * libgcc replacement - count trailing bits
+ */
+
+#include <linux/types.h>
+
+/**
+ * __ctzti2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzti2(long long x)
+{
+	int ret = 0;
+
+	if (!x)
+		return 64;
+
+	if (!(x & 0xFFFFFFFFLL)) {
+		ret += 32;
+		x >>= 32;
+	}
+	if (!(x & 0xFFFFLL)) {
+		ret += 16;
+		x >>= 16;
+	}
+	if (!(x & 0xFFLL)) {
+		ret += 8;
+		x >>= 8;
+	}
+	if (!(x & 0xFLL)) {
+		ret += 4;
+		x >>= 4;
+	}
+	if (!(x & 0x3LL)) {
+		ret += 2;
+		x >>= 2;
+	}
+	if (!(x & 0x1ll))
+		ret += 1;
+
+	return ret;
+}
+
+/**
+ * __ctzsi2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzsi2(int x)
+{
+	int ret = 0;
+
+	if (!x)
+		return 32;
+
+	if (!(x & 0xFFFF)) {
+		ret += 16;
+		x >>= 16;
+	}
+	if (!(x & 0xFF)) {
+		ret += 8;
+		x >>= 8;
+	}
+	if (!(x & 0xF)) {
+		ret += 4;
+		x >>= 4;
+	}
+	if (!(x & 0x3)) {
+		ret += 2;
+		x >>= 2;
+	}
+	if (!(x & 0x1))
+		ret += 1;
+
+	return ret;
+}
+
+/**
+ * __ctzdi2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzdi2(long x)
+{
+#if BITS_PER_LONG == 64
+	return __ctzti2(x);
+#else
+	return __ctzsi2(x);
+#endif
+}
diff --git a/lib/Kconfig b/lib/Kconfig
index f5c1731f456..7b390608b33 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -212,7 +212,7 @@ config IMAGE_SPARSE_FILLBUF_SIZE
 config USE_PRIVATE_LIBGCC
 	bool "Use private libgcc"
 	depends on HAVE_PRIVATE_LIBGCC
-	default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS)
+	default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS || RISCV)
 	help
 	  This option allows you to use the built-in libgcc implementation
 	  of U-Boot instead of the one provided by the compiler.
-- 
2.51.0

[PATCH 2/2] test: provide unit tests for the RISC-V private GCC library

[Heinrich Schuchardt]

From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

Add unit tests for the functions for counting leading and trailing zero
bits.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Heinrich Schuchardt <zfsdt@canonical.com>
---
 test/lib/Makefile   |  4 ++++
 test/lib/test_clz.c | 53 +++++++++++++++++++++++++++++++++++++++++++++
 test/lib/test_ctz.c | 53 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 110 insertions(+)
 create mode 100644 test/lib/test_clz.c
 create mode 100644 test/lib/test_ctz.c

diff --git a/test/lib/Makefile b/test/lib/Makefile
index 35b40b584c4..7c9dc180c8d 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -10,6 +10,10 @@ obj-y += abuf.o
 obj-y += alist.o
 obj-$(CONFIG_EFI_LOADER) += efi_device_path.o efi_memory.o
 obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o
+ifdef CONFIG_RISCV
+obj-$(CONFIG_USE_PRIVATE_LIBGCC) += test_clz.o
+obj-$(CONFIG_USE_PRIVATE_LIBGCC) += test_ctz.o
+endif
 obj-y += hexdump.o
 obj-$(CONFIG_SANDBOX) += kconfig.o
 obj-y += lmb.o
diff --git a/test/lib/test_clz.c b/test/lib/test_clz.c
new file mode 100644
index 00000000000..11fd527d063
--- /dev/null
+++ b/test/lib/test_clz.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2025, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+ */
+
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+int __clzsi2(int a);
+int __clzdi2(long a);
+int __clzti2(long long a);
+
+/**
+ * test_clz() - test library functions to count leading zero bits
+ *
+ * @uts:	unit test state
+ */
+static int test_clz(struct unit_test_state *uts)
+{
+	ut_asserteq(0, __clzti2(0xffffffffffffffffLL));
+	ut_asserteq(0, __clzti2(0x8000000000000000LL));
+	ut_asserteq(1, __clzti2(0x4000000000000000LL));
+	ut_asserteq(17, __clzti2(0x0000500000a00000LL));
+	ut_asserteq(62, __clzti2(0x0000000000000002LL));
+	ut_asserteq(63, __clzti2(0x0000000000000001LL));
+
+#if BITS_PER_LONG == 64
+	ut_asserteq(0, __clzdi2(0xffffffffffffffffLL));
+	ut_asserteq(0, __clzti2(0x8000000000000000LL));
+	ut_asserteq(1, __clzti2(0x4000000000000000LL));
+	ut_asserteq(17, __clzdi2(0x0000500000a00000LL));
+	ut_asserteq(62, __clzdi2(0x0000000000000002LL));
+	ut_asserteq(63, __clzdi2(0x0000000000000001LL));
+#else
+	ut_asserteq(0, __clzdi2(0xffffffff));
+	ut_asserteq(0, __clzdi2(0x80000000));
+	ut_asserteq(1, __clzdi2(0x40000000));
+	ut_asserteq(9, __clzdi2(0x0050a000));
+	ut_asserteq(30, __clzdi2(0x00000002));
+	ut_asserteq(31, __clzdi2(0x00000001));
+#endif
+
+	ut_asserteq(0, __clzsi2(0xffffffff));
+	ut_asserteq(0, __clzsi2(0x80000000));
+	ut_asserteq(1, __clzsi2(0x40000000));
+	ut_asserteq(9, __clzsi2(0x0050a000));
+	ut_asserteq(30, __clzsi2(0x00000002));
+	ut_asserteq(31, __clzsi2(0x00000001));
+
+	return 0;
+}
+LIB_TEST(test_clz, 0);
diff --git a/test/lib/test_ctz.c b/test/lib/test_ctz.c
new file mode 100644
index 00000000000..96c08202dc2
--- /dev/null
+++ b/test/lib/test_ctz.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2025, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+ */
+
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+int __ctzsi2(int a);
+int __ctzdi2(long a);
+int __ctzti2(long long a);
+
+/**
+ * test_ctz() - test library functions to count trailing zero bits
+ *
+ * @uts:	unit test state
+ */
+static int test_ctz(struct unit_test_state *uts)
+{
+	ut_asserteq(0, __ctzti2(0xffffffffffffffffLL));
+	ut_asserteq(63, __ctzti2(0x8000000000000000LL));
+	ut_asserteq(62, __ctzti2(0x4000000000000000LL));
+	ut_asserteq(21, __ctzti2(0x0000500000a00000LL));
+	ut_asserteq(1, __ctzti2(0x0000000000000002LL));
+	ut_asserteq(0, __ctzti2(0x0000000000000001LL));
+
+#if BITS_PER_LONG == 64
+	ut_asserteq(0, __ctzdi2(0xffffffffffffffffLL));
+	ut_asserteq(63, __ctzdi2(0x8000000000000000LL));
+	ut_asserteq(62, __ctzdi2(0x4000000000000000LL));
+	ut_asserteq(21, __ctzdi2(0x0000500000a00000LL));
+	ut_asserteq(1, __ctzdi2(0x0000000000000002LL));
+	ut_asserteq(0, __ctzdi2(0x0000000000000001LL));
+#else
+	ut_asserteq(0, __ctzdi2(0xffffffff));
+	ut_asserteq(31, __ctzdi2(0x80000000));
+	ut_asserteq(30, __ctzdi2(0x40000000));
+	ut_asserteq(13, __ctzdi2(0x0050a000));
+	ut_asserteq(1, __ctzdi2(0x00000002));
+	ut_asserteq(0, __ctzdi2(0x00000001));
+#endif
+
+	ut_asserteq(0, __ctzsi2(0xffffffff));
+	ut_asserteq(31, __ctzsi2(0x80000000));
+	ut_asserteq(30, __ctzsi2(0x40000000));
+	ut_asserteq(13, __ctzsi2(0x0050a000));
+	ut_asserteq(1, __ctzsi2(0x00000002));
+	ut_asserteq(0, __ctzsi2(0x00000001));
+
+	return 0;
+}
+LIB_TEST(test_ctz, 0);
-- 
2.51.0

[PATCH 1/2] RISC-V: implement private GCC library

[Heinrich Schuchardt]

The following functions are provided:

Count leading zero bits

* int __clzsi2 (unsigned int a)
* int __clzdi2 (unsigned long a)
* int __clzti2 (unsigned long long a)

Count trailing zero bits

* int __ctzsi2 (unsigned int a)
* int __ctzdi2 (unsigned long a)
* int __ctzti2 (unsigned long long a)

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 arch/Kconfig            |   1 +
 arch/riscv/lib/Makefile |   2 +
 arch/riscv/lib/clz.c    | 105 ++++++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/ctz.c    |  95 ++++++++++++++++++++++++++++++++++++
 lib/Kconfig             |   2 +-
 5 files changed, 204 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/lib/clz.c
 create mode 100644 arch/riscv/lib/ctz.c

diff --git a/arch/Kconfig b/arch/Kconfig
index 3133f892f94..4af0da2485f 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -159,6 +159,7 @@ config PPC
 config RISCV
 	bool "RISC-V architecture"
 	select CREATE_ARCH_SYMLINK
+	select HAVE_PRIVATE_LIBGCC if 64BIT
 	select HAVE_SETJMP
 	select HAVE_INITJMP
 	select SUPPORT_ACPI
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index f1f50918eff..a527b3e9ae3 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -6,6 +6,8 @@
 # Copyright (C) 2017 Andes Technology Corporation
 # Rick Chen, Andes Technology Corporation <rick@andestech.com>
 
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += clz.o ctz.o
+
 obj-$(CONFIG_$(PHASE_)LIB_BOOTM) += bootm.o
 obj-$(CONFIG_$(PHASE_)LIB_BOOTI) += image.o
 obj-$(CONFIG_CMD_GO) += boot.o
diff --git a/arch/riscv/lib/clz.c b/arch/riscv/lib/clz.c
new file mode 100644
index 00000000000..7b173d3c858
--- /dev/null
+++ b/arch/riscv/lib/clz.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * libgcc replacement - count leading bits
+ *
+ * Copyright 2025, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+ */
+
+#include <linux/types.h>
+
+/**
+ * __clzti2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzti2(long long x)
+{
+	int ret = 64;
+
+	if (!x)
+		return 64;
+
+	if (x & 0xFFFFFFFF00000000LL) {
+		ret -= 32;
+		x >>= 32;
+	}
+	if (x & 0xFFFF0000LL) {
+		ret -= 16;
+		x >>= 16;
+	}
+	if (x & 0xFF00LL) {
+		ret -= 8;
+		x >>= 8;
+	}
+	if (x & 0xF0LL) {
+		ret -= 4;
+		x >>= 4;
+	}
+	if (x & 0xCLL) {
+		ret -= 2;
+		x >>= 2;
+	}
+	if (x & 0x2LL) {
+		ret -= 1;
+		x >>= 1;
+	}
+	if (x)
+		ret -= 1;
+
+	return ret;
+}
+
+/**
+ * __clzsi2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzsi2(int x)
+{
+	int ret = 32;
+
+	if (!x)
+		return 32;
+
+	if (x & 0xFFFF0000) {
+		ret -= 16;
+		x >>= 16;
+	}
+	if (x & 0xFF00) {
+		ret -= 8;
+		x >>= 8;
+	}
+	if (x & 0xF0) {
+		ret -= 4;
+		x >>= 4;
+	}
+	if (x & 0xC) {
+		ret -= 2;
+		x >>= 2;
+	}
+	if (x & 0x2) {
+		ret -= 1;
+		x >>= 1;
+	}
+	if (x)
+		ret -= 1;
+
+	return ret;
+}
+
+/**
+ * __clzdi2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzdi2(long x)
+{
+#if BITS_PER_LONG == 64
+	return __clzti2(x);
+#else
+	return __clzsi2(x);
+#endif
+}
diff --git a/arch/riscv/lib/ctz.c b/arch/riscv/lib/ctz.c
new file mode 100644
index 00000000000..6c875e39f0e
--- /dev/null
+++ b/arch/riscv/lib/ctz.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * libgcc replacement - count trailing bits
+ */
+
+#include <linux/types.h>
+
+/**
+ * __ctzti2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzti2(long long x)
+{
+	int ret = 0;
+
+	if (!x)
+		return 64;
+
+	if (!(x & 0xFFFFFFFFLL)) {
+		ret += 32;
+		x >>= 32;
+	}
+	if (!(x & 0xFFFFLL)) {
+		ret += 16;
+		x >>= 16;
+	}
+	if (!(x & 0xFFLL)) {
+		ret += 8;
+		x >>= 8;
+	}
+	if (!(x & 0xFLL)) {
+		ret += 4;
+		x >>= 4;
+	}
+	if (!(x & 0x3LL)) {
+		ret += 2;
+		x >>= 2;
+	}
+	if (!(x & 0x1ll))
+		ret += 1;
+
+	return ret;
+}
+
+/**
+ * __ctzsi2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzsi2(int x)
+{
+	int ret = 0;
+
+	if (!x)
+		return 32;
+
+	if (!(x & 0xFFFF)) {
+		ret += 16;
+		x >>= 16;
+	}
+	if (!(x & 0xFF)) {
+		ret += 8;
+		x >>= 8;
+	}
+	if (!(x & 0xF)) {
+		ret += 4;
+		x >>= 4;
+	}
+	if (!(x & 0x3)) {
+		ret += 2;
+		x >>= 2;
+	}
+	if (!(x & 0x1))
+		ret += 1;
+
+	return ret;
+}
+
+/**
+ * __ctzdi2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzdi2(long x)
+{
+#if BITS_PER_LONG == 64
+	return __ctzti2(x);
+#else
+	return __ctzsi2(x);
+#endif
+}
diff --git a/lib/Kconfig b/lib/Kconfig
index f5c1731f456..7b390608b33 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -212,7 +212,7 @@ config IMAGE_SPARSE_FILLBUF_SIZE
 config USE_PRIVATE_LIBGCC
 	bool "Use private libgcc"
 	depends on HAVE_PRIVATE_LIBGCC
-	default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS)
+	default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS || RISCV)
 	help
 	  This option allows you to use the built-in libgcc implementation
 	  of U-Boot instead of the one provided by the compiler.
-- 
2.51.0

Re: [PATCH 1/2] RISC-V: implement private GCC library

[Yao Zi]

On Mon, Dec 01, 2025 at 06:49:03PM +0100, Heinrich Schuchardt wrote:
> The following functions are provided:
> 
> Count leading zero bits
> 
> * int __clzsi2 (unsigned int a)
> * int __clzdi2 (unsigned long a)
> * int __clzti2 (unsigned long long a)
> 
> Count trailing zero bits
> 
> * int __ctzsi2 (unsigned int a)
> * int __ctzdi2 (unsigned long a)
> * int __ctzti2 (unsigned long long a)
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---

I noted there's another series with the same subject[1] sent almost at
the same time, and I couldn't tell the difference at the first glance.
Is this an incident?

>  arch/Kconfig            |   1 +
>  arch/riscv/lib/Makefile |   2 +
>  arch/riscv/lib/clz.c    | 105 ++++++++++++++++++++++++++++++++++++++++
>  arch/riscv/lib/ctz.c    |  95 ++++++++++++++++++++++++++++++++++++
>  lib/Kconfig             |   2 +-
>  5 files changed, 204 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/lib/clz.c
>  create mode 100644 arch/riscv/lib/ctz.c
> 
> diff --git a/arch/Kconfig b/arch/Kconfig
> index 3133f892f94..4af0da2485f 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -159,6 +159,7 @@ config PPC
>  config RISCV
>  	bool "RISC-V architecture"
>  	select CREATE_ARCH_SYMLINK
> +	select HAVE_PRIVATE_LIBGCC if 64BIT

Are 32-bit platforms excluded for lacking of enough library functions?
Should we exclude !RISCV_ISA_F || !RISCV_ISA_D platforms as well? Though
there's no in-tree 64-bit port without F/D extension.

>  	select HAVE_SETJMP
>  	select HAVE_INITJMP
>  	select SUPPORT_ACPI

Regards,
Yao Zi

[1]: https://lore.kernel.org/u-boot/20251201174705.652626-1-zfsdt@canonical.com/

Re: [PATCH 1/2] RISC-V: implement private GCC library

[Heinrich Schuchardt]

On 12/2/25 04:57, Yao Zi wrote:
> On Mon, Dec 01, 2025 at 06:49:03PM +0100, Heinrich Schuchardt wrote:
>> The following functions are provided:
>>
>> Count leading zero bits
>>
>> * int __clzsi2 (unsigned int a)
>> * int __clzdi2 (unsigned long a)
>> * int __clzti2 (unsigned long long a)
>>
>> Count trailing zero bits
>>
>> * int __ctzsi2 (unsigned int a)
>> * int __ctzdi2 (unsigned long a)
>> * int __ctzti2 (unsigned long long a)
>>
>> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
>> ---
> 
> I noted there's another series with the same subject[1] sent almost at
> the same time, and I couldn't tell the difference at the first glance.
> Is this an incident?

Thank you for reviewing.

That was my mistake. I have set the first mail series [1] to superseded 
in Patchwork.

> 
>>   arch/Kconfig            |   1 +
>>   arch/riscv/lib/Makefile |   2 +
>>   arch/riscv/lib/clz.c    | 105 ++++++++++++++++++++++++++++++++++++++++
>>   arch/riscv/lib/ctz.c    |  95 ++++++++++++++++++++++++++++++++++++
>>   lib/Kconfig             |   2 +-
>>   5 files changed, 204 insertions(+), 1 deletion(-)
>>   create mode 100644 arch/riscv/lib/clz.c
>>   create mode 100644 arch/riscv/lib/ctz.c
>>
>> diff --git a/arch/Kconfig b/arch/Kconfig
>> index 3133f892f94..4af0da2485f 100644
>> --- a/arch/Kconfig
>> +++ b/arch/Kconfig
>> @@ -159,6 +159,7 @@ config PPC
>>   config RISCV
>>   	bool "RISC-V architecture"
>>   	select CREATE_ARCH_SYMLINK
>> +	select HAVE_PRIVATE_LIBGCC if 64BIT
> 
> Are 32-bit platforms excluded for lacking of enough library functions?
> Should we exclude !RISCV_ISA_F || !RISCV_ISA_D platforms as well? Though
> there's no in-tree 64-bit port without F/D extension.

As I am not aware of any RVA23 distro for 32bit RISC-V, I see no current 
need.

32-bit support will require additionally implementing __ashldi3, 
__lshldi3, __udivdi3.

If you want to implement these extra functions, you cannot trust the 
documentation. The functions don't take the arguments described in 
https://gcc.gnu.org/onlinedocs/gccint/Integer-library-routines.html. E.g 
__ashldi3 expects a 64 bit value passed in registers a0 (low bits), a1 
(high bits) while the shift is passed in a2. 32-bit __udivdi3 expects 
two 64-bit values.

See 
https://github.com/gcc-mirror/gcc/blob/addda4a7e8593c37c90eb4c1d7edda29fa4bde31/libgcc/libgcc2.c#L412

libgcc is published under GPL-3 and therefore we cannot simply copy that 
code into our GPL-2 project.

Best regards

Heinrich

> 
>>   	select HAVE_SETJMP
>>   	select HAVE_INITJMP
>>   	select SUPPORT_ACPI
> 
> Regards,
> Yao Zi
> 
> [1]: https://lore.kernel.org/u-boot/20251201174705.652626-1-zfsdt@canonical.com/

Re: [PATCH 1/2] RISC-V: implement private GCC library

[Icenowy Zheng]

在 2025-12-02星期二的 03:57 +0000，Yao Zi写道：
> On Mon, Dec 01, 2025 at 06:49:03PM +0100, Heinrich Schuchardt wrote:
> > The following functions are provided:
> > 
> > Count leading zero bits
> > 
> > * int __clzsi2 (unsigned int a)
> > * int __clzdi2 (unsigned long a)
> > * int __clzti2 (unsigned long long a)
> > 
> > Count trailing zero bits
> > 
> > * int __ctzsi2 (unsigned int a)
> > * int __ctzdi2 (unsigned long a)
> > * int __ctzti2 (unsigned long long a)
> > 
> > Signed-off-by: Heinrich Schuchardt
> > <heinrich.schuchardt@canonical.com>
> > ---
> 
> I noted there's another series with the same subject[1] sent almost
> at
> the same time, and I couldn't tell the difference at the first
> glance.
> Is this an incident?
> 
> >  arch/Kconfig            |   1 +
> >  arch/riscv/lib/Makefile |   2 +
> >  arch/riscv/lib/clz.c    | 105
> > ++++++++++++++++++++++++++++++++++++++++
> >  arch/riscv/lib/ctz.c    |  95 ++++++++++++++++++++++++++++++++++++
> >  lib/Kconfig             |   2 +-
> >  5 files changed, 204 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/riscv/lib/clz.c
> >  create mode 100644 arch/riscv/lib/ctz.c
> > 
> > diff --git a/arch/Kconfig b/arch/Kconfig
> > index 3133f892f94..4af0da2485f 100644
> > --- a/arch/Kconfig
> > +++ b/arch/Kconfig
> > @@ -159,6 +159,7 @@ config PPC
> >  config RISCV
> >         bool "RISC-V architecture"
> >         select CREATE_ARCH_SYMLINK
> > +       select HAVE_PRIVATE_LIBGCC if 64BIT
> 
> Are 32-bit platforms excluded for lacking of enough library
> functions?
> Should we exclude !RISCV_ISA_F || !RISCV_ISA_D platforms as well?
> Though
> there's no in-tree 64-bit port without F/D extension.

The S7 core in U74-MC complex seems to have only IMAC, no F/D.

> 
> >         select HAVE_SETJMP
> >         select HAVE_INITJMP
> >         select SUPPORT_ACPI
> 
> Regards,
> Yao Zi
> 
> [1]:
> https://lore.kernel.org/u-boot/20251201174705.652626-1-zfsdt@canonical.com/

Re: [PATCH 1/2] RISC-V: implement private GCC library

[Heinrich Schuchardt]

On 12/2/25 06:28, Icenowy Zheng wrote:
> 在 2025-12-02星期二的 03:57 +0000，Yao Zi写道：
>> On Mon, Dec 01, 2025 at 06:49:03PM +0100, Heinrich Schuchardt wrote:
>>> The following functions are provided:
>>>
>>> Count leading zero bits
>>>
>>> * int __clzsi2 (unsigned int a)
>>> * int __clzdi2 (unsigned long a)
>>> * int __clzti2 (unsigned long long a)
>>>
>>> Count trailing zero bits
>>>
>>> * int __ctzsi2 (unsigned int a)
>>> * int __ctzdi2 (unsigned long a)
>>> * int __ctzti2 (unsigned long long a)
>>>
>>> Signed-off-by: Heinrich Schuchardt
>>> <heinrich.schuchardt@canonical.com>
>>> ---
>>
>> I noted there's another series with the same subject[1] sent almost
>> at
>> the same time, and I couldn't tell the difference at the first
>> glance.
>> Is this an incident?
>>
>>>   arch/Kconfig            |   1 +
>>>   arch/riscv/lib/Makefile |   2 +
>>>   arch/riscv/lib/clz.c    | 105
>>> ++++++++++++++++++++++++++++++++++++++++
>>>   arch/riscv/lib/ctz.c    |  95 ++++++++++++++++++++++++++++++++++++
>>>   lib/Kconfig             |   2 +-
>>>   5 files changed, 204 insertions(+), 1 deletion(-)
>>>   create mode 100644 arch/riscv/lib/clz.c
>>>   create mode 100644 arch/riscv/lib/ctz.c
>>>
>>> diff --git a/arch/Kconfig b/arch/Kconfig
>>> index 3133f892f94..4af0da2485f 100644
>>> --- a/arch/Kconfig
>>> +++ b/arch/Kconfig
>>> @@ -159,6 +159,7 @@ config PPC
>>>   config RISCV
>>>          bool "RISC-V architecture"
>>>          select CREATE_ARCH_SYMLINK
>>> +       select HAVE_PRIVATE_LIBGCC if 64BIT
>>
>> Are 32-bit platforms excluded for lacking of enough library
>> functions?

Yes. See 
https://lore.kernel.org/u-boot/20251201174904.652954-1-heinrich.schuchardt@canonical.com/T/#mbf44c9f5073649bbf2e1368ffbeaec82680a268d

>> Should we exclude !RISCV_ISA_F || !RISCV_ISA_D platforms as well?
>> Though

libgcc.a as provided by distros assumes that you have the D and F 
extensions. Either a specific libgcc.a will be needed or we will have to 
implement the missing functions in the private lib if such platforms.

It would make more sense to set CONFIG_USE_PRIVATE_LIBGCC=n for such 
platforms than setting CONFIG_HAVE_PRIVATE_LIBGCC=n.

Which way we want to go can be decided when such platforms arrive.

>> there's no in-tree 64-bit port without F/D extension.
> 
> The S7 core in U74-MC complex seems to have only IMAC, no F/D.
The S7 core is not supported by U-Boot.

Best regards

Heinrich

> 
>>
>>>          select HAVE_SETJMP
>>>          select HAVE_INITJMP
>>>          select SUPPORT_ACPI
>>
>> Regards,
>> Yao Zi
>>
>> [1]:
>> https://lore.kernel.org/u-boot/20251201174705.652626-1-zfsdt@canonical.com/
> 

Re: [PATCH 1/2] RISC-V: implement private GCC library

[Icenowy Zheng]

在 2025-12-02星期二的 07:15 +0100，Heinrich Schuchardt写道：
> On 12/2/25 06:28, Icenowy Zheng wrote:
> > 在 2025-12-02星期二的 03:57 +0000，Yao Zi写道：
> > > On Mon, Dec 01, 2025 at 06:49:03PM +0100, Heinrich Schuchardt
> > > wrote:
> > > > The following functions are provided:
> > > > 
> > > > Count leading zero bits
> > > > 
> > > > * int __clzsi2 (unsigned int a)
> > > > * int __clzdi2 (unsigned long a)
> > > > * int __clzti2 (unsigned long long a)
> > > > 
> > > > Count trailing zero bits
> > > > 
> > > > * int __ctzsi2 (unsigned int a)
> > > > * int __ctzdi2 (unsigned long a)
> > > > * int __ctzti2 (unsigned long long a)
> > > > 
> > > > Signed-off-by: Heinrich Schuchardt
> > > > <heinrich.schuchardt@canonical.com>
> > > > ---
> > > 
> > > I noted there's another series with the same subject[1] sent
> > > almost
> > > at
> > > the same time, and I couldn't tell the difference at the first
> > > glance.
> > > Is this an incident?
> > > 
> > > >   arch/Kconfig            |   1 +
> > > >   arch/riscv/lib/Makefile |   2 +
> > > >   arch/riscv/lib/clz.c    | 105
> > > > ++++++++++++++++++++++++++++++++++++++++
> > > >   arch/riscv/lib/ctz.c    |  95
> > > > ++++++++++++++++++++++++++++++++++++
> > > >   lib/Kconfig             |   2 +-
> > > >   5 files changed, 204 insertions(+), 1 deletion(-)
> > > >   create mode 100644 arch/riscv/lib/clz.c
> > > >   create mode 100644 arch/riscv/lib/ctz.c
> > > > 
> > > > diff --git a/arch/Kconfig b/arch/Kconfig
> > > > index 3133f892f94..4af0da2485f 100644
> > > > --- a/arch/Kconfig
> > > > +++ b/arch/Kconfig
> > > > @@ -159,6 +159,7 @@ config PPC
> > > >   config RISCV
> > > >          bool "RISC-V architecture"
> > > >          select CREATE_ARCH_SYMLINK
> > > > +       select HAVE_PRIVATE_LIBGCC if 64BIT
> > > 
> > > Are 32-bit platforms excluded for lacking of enough library
> > > functions?
> 
> Yes. See 
> https://lore.kernel.org/u-boot/20251201174904.652954-1-heinrich.schuchardt@canonical.com/T/#mbf44c9f5073649bbf2e1368ffbeaec82680a268d
> 
> > > Should we exclude !RISCV_ISA_F || !RISCV_ISA_D platforms as well?
> > > Though
> 
> libgcc.a as provided by distros assumes that you have the D and F 
> extensions. Either a specific libgcc.a will be needed or we will have
> to 
> implement the missing functions in the private lib if such platforms.
> 
> It would make more sense to set CONFIG_USE_PRIVATE_LIBGCC=n for such 
> platforms than setting CONFIG_HAVE_PRIVATE_LIBGCC=n.
> 
> Which way we want to go can be decided when such platforms arrive.
> 
> > > there's no in-tree 64-bit port without F/D extension.
> > 
> > The S7 core in U74-MC complex seems to have only IMAC, no F/D.
> The S7 core is not supported by U-Boot.

Well at least SPL is run on the S7 cores, although the SBI should keep
the S7 core from being running main U-Boot.

> 
> Best regards
> 
> Heinrich
> 
> > 
> > > 
> > > >          select HAVE_SETJMP
> > > >          select HAVE_INITJMP
> > > >          select SUPPORT_ACPI
> > > 
> > > Regards,
> > > Yao Zi
> > > 
> > > [1]:
> > > https://lore.kernel.org/u-boot/20251201174705.652626-1-zfsdt@canonical.com/
> > 
> 

Re: [PATCH 1/2] RISC-V: implement private GCC library

[Heinrich Schuchardt]

On 12/2/25 08:03, Icenowy Zheng wrote:
> 在 2025-12-02星期二的 07:15 +0100，Heinrich Schuchardt写道：
>> On 12/2/25 06:28, Icenowy Zheng wrote:
>>> 在 2025-12-02星期二的 03:57 +0000，Yao Zi写道：
>>>> On Mon, Dec 01, 2025 at 06:49:03PM +0100, Heinrich Schuchardt
>>>> wrote:
>>>>> The following functions are provided:
>>>>>
>>>>> Count leading zero bits
>>>>>
>>>>> * int __clzsi2 (unsigned int a)
>>>>> * int __clzdi2 (unsigned long a)
>>>>> * int __clzti2 (unsigned long long a)
>>>>>
>>>>> Count trailing zero bits
>>>>>
>>>>> * int __ctzsi2 (unsigned int a)
>>>>> * int __ctzdi2 (unsigned long a)
>>>>> * int __ctzti2 (unsigned long long a)
>>>>>
>>>>> Signed-off-by: Heinrich Schuchardt
>>>>> <heinrich.schuchardt@canonical.com>
>>>>> ---
>>>>
>>>> I noted there's another series with the same subject[1] sent
>>>> almost
>>>> at
>>>> the same time, and I couldn't tell the difference at the first
>>>> glance.
>>>> Is this an incident?
>>>>
>>>>>    arch/Kconfig            |   1 +
>>>>>    arch/riscv/lib/Makefile |   2 +
>>>>>    arch/riscv/lib/clz.c    | 105
>>>>> ++++++++++++++++++++++++++++++++++++++++
>>>>>    arch/riscv/lib/ctz.c    |  95
>>>>> ++++++++++++++++++++++++++++++++++++
>>>>>    lib/Kconfig             |   2 +-
>>>>>    5 files changed, 204 insertions(+), 1 deletion(-)
>>>>>    create mode 100644 arch/riscv/lib/clz.c
>>>>>    create mode 100644 arch/riscv/lib/ctz.c
>>>>>
>>>>> diff --git a/arch/Kconfig b/arch/Kconfig
>>>>> index 3133f892f94..4af0da2485f 100644
>>>>> --- a/arch/Kconfig
>>>>> +++ b/arch/Kconfig
>>>>> @@ -159,6 +159,7 @@ config PPC
>>>>>    config RISCV
>>>>>           bool "RISC-V architecture"
>>>>>           select CREATE_ARCH_SYMLINK
>>>>> +       select HAVE_PRIVATE_LIBGCC if 64BIT
>>>>
>>>> Are 32-bit platforms excluded for lacking of enough library
>>>> functions?
>>
>> Yes. See
>> https://lore.kernel.org/u-boot/20251201174904.652954-1-heinrich.schuchardt@canonical.com/T/#mbf44c9f5073649bbf2e1368ffbeaec82680a268d
>>
>>>> Should we exclude !RISCV_ISA_F || !RISCV_ISA_D platforms as well?
>>>> Though
>>
>> libgcc.a as provided by distros assumes that you have the D and F
>> extensions. Either a specific libgcc.a will be needed or we will have
>> to
>> implement the missing functions in the private lib if such platforms.
>>
>> It would make more sense to set CONFIG_USE_PRIVATE_LIBGCC=n for such
>> platforms than setting CONFIG_HAVE_PRIVATE_LIBGCC=n.
>>
>> Which way we want to go can be decided when such platforms arrive.
>>
>>>> there's no in-tree 64-bit port without F/D extension.
>>>
>>> The S7 core in U74-MC complex seems to have only IMAC, no F/D.
>> The S7 core is not supported by U-Boot.

https://starfivetech.com/uploads/u74_core_complex_manual_21G1.pdf
talks of U7 and has "The U7 FPU provides full hardware support for the 
IEEE 754-2008 floating-point standard for 32-bit single-precision and 
64-bit double-precision arithmetic."

https://www.sifive.com/document-file/freedom-u740-c000-manual mentions: 
"The S7 RISC‑V Core supports the RV64IMAC extension string."

The main user of floating point variables in U-Boot is the TrueType 
library. I guess without TrueType you will not be using the floating 
point unit

> 
> Well at least SPL is run on the S7 cores, although the SBI should keep
> the S7 core from being running main U-Boot.

On the Unmatched board the HSM extension reports the S7 hart of the 
Unmatched board as stopped.

Harts:
   0: stopped
   1: started
   2: stopped
   3: stopped
   4: stopped

But it seems that the SBI API does not allow to determine if a hart 
actually has entered OpenSBI.

qemu-riscv64_smode_defconfig can be booted with
-cpu rv64,zfa=off,f=off,d=off

Best regards

Heinrich
>>>
>>>>
>>>>>           select HAVE_SETJMP
>>>>>           select HAVE_INITJMP
>>>>>           select SUPPORT_ACPI
>>>>
>>>> Regards,
>>>> Yao Zi
>>>>
>>>> [1]:
>>>> https://lore.kernel.org/u-boot/20251201174705.652626-1-zfsdt@canonical.com/
>>>
>>
> 

Re: [PATCH 0/2] RISC-V: implement private GCC library

[Mark Kettenis]

> From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> Date: Mon,  1 Dec 2025 18:47:03 +0100
> 
> We currently include libgcc.a when building for the RISC-V architecture.
> For instance lib/mbedtls/external/mbedtls/library/bignum.c uses __ctzdi2().
> 
> At least the Ubuntu Linux distribution has switched to building libgcc.a
> for the RVA23S64 profile. Using this library on RVA20 systems results in
> crashes. We therefore need a private replacement library.

Sound like the real problem here is using a native toolchain instead
of a toolchain for the target at hand.

That said, the solution a sensible one.

> With the series a private GCC library and unit tests are provided for
> 64-bit RISC-V. This is enough to build for CONFIG_WGET_HTTPS as suggested
> in E's patch
> 
> [PATCH] configs: starfive: enable wget https
> https://lore.kernel.org/u-boot/20251112005451.41285-1-e@freeshell.de/
> 
> Heinrich Schuchardt (2):
>   RISC-V: implement private GCC library
>   test: provide unit tests for the RISC-V private GCC library
> 
>  arch/Kconfig            |   1 +
>  arch/riscv/lib/Makefile |   2 +
>  arch/riscv/lib/clz.c    | 105 ++++++++++++++++++++++++++++++++++++++++
>  arch/riscv/lib/ctz.c    |  97 +++++++++++++++++++++++++++++++++++++
>  lib/Kconfig             |   2 +-
>  test/lib/Makefile       |   4 ++
>  test/lib/test_clz.c     |  53 ++++++++++++++++++++
>  test/lib/test_ctz.c     |  53 ++++++++++++++++++++
>  8 files changed, 316 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/lib/clz.c
>  create mode 100644 arch/riscv/lib/ctz.c
>  create mode 100644 test/lib/test_clz.c
>  create mode 100644 test/lib/test_ctz.c
> 
> -- 
> 2.51.0
> 
> 

Re: [PATCH 1/2] RISC-V: implement private GCC library

[Leo Liang]

On Mon, Dec 01, 2025 at 06:47:04PM +0100, Heinrich Schuchardt wrote:
> [EXTERNAL MAIL]
> 
> From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> 
> The following functions are provided:
> 
> Count leading zero bits
> 
> * int __clzsi2 (unsigned int a)
> * int __clzdi2 (unsigned long a)
> * int __clzti2 (unsigned long long a)
> 
> Count trailing zero bits
> 
> * int __ctzsi2 (unsigned int a)
> * int __ctzdi2 (unsigned long a)
> * int __ctzti2 (unsigned long long a)
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> Signed-off-by: Heinrich Schuchardt <zfsdt@canonical.com>
> ---
>  arch/Kconfig            |   1 +
>  arch/riscv/lib/Makefile |   2 +
>  arch/riscv/lib/clz.c    | 105 ++++++++++++++++++++++++++++++++++++++++
>  arch/riscv/lib/ctz.c    |  95 ++++++++++++++++++++++++++++++++++++
>  lib/Kconfig             |   2 +-
>  5 files changed, 204 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/lib/clz.c
>  create mode 100644 arch/riscv/lib/ctz.c

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 1/2] RISC-V: implement private GCC library

[Leo Liang]

On Mon, Dec 01, 2025 at 06:47:04PM +0100, Heinrich Schuchardt wrote:
> [EXTERNAL MAIL]
> 
> From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> 
> The following functions are provided:
> 
> Count leading zero bits
> 
> * int __clzsi2 (unsigned int a)
> * int __clzdi2 (unsigned long a)
> * int __clzti2 (unsigned long long a)
> 
> Count trailing zero bits
> 
> * int __ctzsi2 (unsigned int a)
> * int __ctzdi2 (unsigned long a)
> * int __ctzti2 (unsigned long long a)
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> Signed-off-by: Heinrich Schuchardt <zfsdt@canonical.com>
> ---
>  arch/Kconfig            |   1 +
>  arch/riscv/lib/Makefile |   2 +
>  arch/riscv/lib/clz.c    | 105 ++++++++++++++++++++++++++++++++++++++++
>  arch/riscv/lib/ctz.c    |  95 ++++++++++++++++++++++++++++++++++++
>  lib/Kconfig             |   2 +-
>  5 files changed, 204 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/lib/clz.c
>  create mode 100644 arch/riscv/lib/ctz.c

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>