[PATCH 0/3] fpu: Fix OCP FP8 E4M3 conversion issues

[PATCH 0/3] fpu: Fix OCP FP8 E4M3 conversion issues

[Max Chou]

This series fix following issues related to OCP FP8 E4M3 conversion.

- Numeric overflow to E4M3 produces incorrect exponent values due to a
  missing local variable update after calling uncanon_e4m3_overflow.
- Converting infinity to E4M3 incorrectly raises OF|NX exception flags.
- The E4M3 NaN classification logic in parts_canonicalize uses an
  indirect method that obscures the architecture-dependent semantics.

rnax

Max Chou (3):
  fpu: Fix repacking issues in the uncanonical step for E4M3 overflow
  fpu: Fix unexpected exception flags when converting infinity to OCP
    E4M3
  fpu: Simplify OCP FP8 E4M3 NaN classification in parts_canonicalize

 fpu/softfloat-parts.c.inc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

-- 
2.52.0

[PATCH 1/3] fpu: Fix repacking issues in the uncanonical step for E4M3 overflow

[Max Chou]

In the uncanonical step, the input FloatParts will be repacked to the
target FloatFmt. This commit fixes following issues after calling
uncanon_e4m3_overflow in the uncanon/uncanon_normal functions.

- Add the local exp update after calling uncanon_e4m3_overflow in the
  parts_uncanon_normal function.
- Add the fraction shift after calling uncanon_e4m3_overflow in the
  parts_uncanon function.

Fixes: 27e989f99c ("fpu: Add conversion routines for OCP FP8 E4M3")
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 fpu/softfloat-parts.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index 61b07307bf..a738758aee 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -387,6 +387,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
             case float_expmax_e4m3:
                 if (exp > exp_max || p->frac_hi > E4M3_NORMAL_FRAC_MAX) {
                     partsN(uncanon_e4m3_overflow)(p, s, fmt, overflow_norm);
+                    exp = p->exp;
                 }
                 break;
 
@@ -496,6 +497,7 @@ static void partsN(uncanon)(FloatPartsN *p, float_status *s,
                 break;
             case float_expmax_e4m3:
                 partsN(uncanon_e4m3_overflow)(p, s, fmt, saturate);
+                frac_shr(p, fmt->frac_shift);
                 break;
             case float_expmax_normal:
             default:
-- 
2.52.0

[PATCH 2/3] fpu: Fix unexpected exception flags when converting infinity to OCP E4M3

[Max Chou]

Infinity is a special case distinct from numeric overflow:
- Numeric overflow: finite value exceeds format's max normal
  -> overflow|inexact
- Infinity conversion: input is already infinite
  -> no flags

This commit fixes the unexpect exception flags by relocating the float
exception flag update flow to be outside the uncanon_e4m3_overflow.
And raising the overflow|inexact for numeric overflow in uncanon_normal.

Fixes: 27e989f99c ("fpu: Add conversion routines for OCP FP8 E4M3")
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 fpu/softfloat-parts.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index a738758aee..3c323c0cec 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -277,7 +277,6 @@ static void partsN(uncanon_e4m3_overflow)(FloatPartsN *p, float_status *s,
                                           const FloatFmt *fmt, bool saturate)
 {
     assert(N == 64);
-    float_raise(float_flag_overflow | float_flag_inexact, s);
     if (saturate) {
         p->exp = fmt->exp_max;
         p->frac_hi = E4M3_NORMAL_FRAC_MAX;
@@ -388,6 +387,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
                 if (exp > exp_max || p->frac_hi > E4M3_NORMAL_FRAC_MAX) {
                     partsN(uncanon_e4m3_overflow)(p, s, fmt, overflow_norm);
                     exp = p->exp;
+                    flags |= (float_flag_overflow | float_flag_inexact);
                 }
                 break;
 
-- 
2.52.0

[PATCH 3/3] fpu: Simplify OCP FP8 E4M3 NaN classification in parts_canonicalize

[Max Chou]

The OCP FP8 E4M3 format has only a single NaN encoding (0x7F/0xFF),
Replace the indirect check via parts_is_snan_frac with a direct
check of no_signaling_nans to make the intent clearer.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 fpu/softfloat-parts.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index 3c323c0cec..5ef7e2d921 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -245,8 +245,8 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status,
         case float_expmax_e4m3:
             if (p->frac_hi == 0b111) {
                 frac_shl(p, fmt->frac_shift);
-                p->cls = (parts_is_snan_frac(p->frac_hi, status)
-                          ? float_class_snan : float_class_qnan);
+                p->cls = no_signaling_nans(status) ? float_class_qnan :
+                                                     float_class_snan;
                 return;
             }
             /* otherwise normal */
-- 
2.52.0

Re: [PATCH 3/3] fpu: Simplify OCP FP8 E4M3 NaN classification in parts_canonicalize

[Chao Liu]

On Wed, Feb 25, 2026 at 07:08:02PM +0800, Max Chou wrote:
> The OCP FP8 E4M3 format has only a single NaN encoding (0x7F/0xFF),
> Replace the indirect check via parts_is_snan_frac with a direct
> check of no_signaling_nans to make the intent clearer.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>  fpu/softfloat-parts.c.inc | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
> index 3c323c0cec..5ef7e2d921 100644
> --- a/fpu/softfloat-parts.c.inc
> +++ b/fpu/softfloat-parts.c.inc
> @@ -245,8 +245,8 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status,
>          case float_expmax_e4m3:
>              if (p->frac_hi == 0b111) {
>                  frac_shl(p, fmt->frac_shift);
> -                p->cls = (parts_is_snan_frac(p->frac_hi, status)
> -                          ? float_class_snan : float_class_qnan);
> +                p->cls = no_signaling_nans(status) ? float_class_qnan :
> +                                                     float_class_snan;
>                  return;
>              }
>              /* otherwise normal */
> -- 
> 2.52.0
> 
> 

Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

Thanks,
Chao

Re: [PATCH 2/3] fpu: Fix unexpected exception flags when converting infinity to OCP E4M3

[Chao Liu]

On Wed, Feb 25, 2026 at 07:08:01PM +0800, Max Chou wrote:
> Infinity is a special case distinct from numeric overflow:
> - Numeric overflow: finite value exceeds format's max normal
>   -> overflow|inexact
> - Infinity conversion: input is already infinite
>   -> no flags
> 
> This commit fixes the unexpect exception flags by relocating the float
> exception flag update flow to be outside the uncanon_e4m3_overflow.
> And raising the overflow|inexact for numeric overflow in uncanon_normal.
> 
> Fixes: 27e989f99c ("fpu: Add conversion routines for OCP FP8 E4M3")
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>  fpu/softfloat-parts.c.inc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
> index a738758aee..3c323c0cec 100644
> --- a/fpu/softfloat-parts.c.inc
> +++ b/fpu/softfloat-parts.c.inc
> @@ -277,7 +277,6 @@ static void partsN(uncanon_e4m3_overflow)(FloatPartsN *p, float_status *s,
>                                            const FloatFmt *fmt, bool saturate)
>  {
>      assert(N == 64);
> -    float_raise(float_flag_overflow | float_flag_inexact, s);
>      if (saturate) {
>          p->exp = fmt->exp_max;
>          p->frac_hi = E4M3_NORMAL_FRAC_MAX;
> @@ -388,6 +387,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
>                  if (exp > exp_max || p->frac_hi > E4M3_NORMAL_FRAC_MAX) {
>                      partsN(uncanon_e4m3_overflow)(p, s, fmt, overflow_norm);
>                      exp = p->exp;
> +                    flags |= (float_flag_overflow | float_flag_inexact);
>                  }
>                  break;
>  
> -- 
> 2.52.0
> 
> 

Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

Thanks,
Chao

Re: [PATCH 1/3] fpu: Fix repacking issues in the uncanonical step for E4M3 overflow

[Chao Liu]

On Wed, Feb 25, 2026 at 07:08:00PM +0800, Max Chou wrote:
> In the uncanonical step, the input FloatParts will be repacked to the
> target FloatFmt. This commit fixes following issues after calling
> uncanon_e4m3_overflow in the uncanon/uncanon_normal functions.
> 
> - Add the local exp update after calling uncanon_e4m3_overflow in the
>   parts_uncanon_normal function.
> - Add the fraction shift after calling uncanon_e4m3_overflow in the
>   parts_uncanon function.
> 
> Fixes: 27e989f99c ("fpu: Add conversion routines for OCP FP8 E4M3")
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>  fpu/softfloat-parts.c.inc | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
> index 61b07307bf..a738758aee 100644
> --- a/fpu/softfloat-parts.c.inc
> +++ b/fpu/softfloat-parts.c.inc
> @@ -387,6 +387,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
>              case float_expmax_e4m3:
>                  if (exp > exp_max || p->frac_hi > E4M3_NORMAL_FRAC_MAX) {
>                      partsN(uncanon_e4m3_overflow)(p, s, fmt, overflow_norm);
> +                    exp = p->exp;
>                  }
>                  break;
>  
> @@ -496,6 +497,7 @@ static void partsN(uncanon)(FloatPartsN *p, float_status *s,
>                  break;
>              case float_expmax_e4m3:
>                  partsN(uncanon_e4m3_overflow)(p, s, fmt, saturate);
> +                frac_shr(p, fmt->frac_shift);
>                  break;
>              case float_expmax_normal:
>              default:
> -- 
> 2.52.0
> 
> 

Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

Thanks,
Chao

Re: [PATCH 3/3] fpu: Simplify OCP FP8 E4M3 NaN classification in parts_canonicalize

[Richard Henderson]

On 2/25/26 22:08, Max Chou wrote:
> The OCP FP8 E4M3 format has only a single NaN encoding (0x7F/0xFF),
> Replace the indirect check via parts_is_snan_frac with a direct
> check of no_signaling_nans to make the intent clearer.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   fpu/softfloat-parts.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
> index 3c323c0cec..5ef7e2d921 100644
> --- a/fpu/softfloat-parts.c.inc
> +++ b/fpu/softfloat-parts.c.inc
> @@ -245,8 +245,8 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status,
>           case float_expmax_e4m3:
>               if (p->frac_hi == 0b111) {
>                   frac_shl(p, fmt->frac_shift);
> -                p->cls = (parts_is_snan_frac(p->frac_hi, status)
> -                          ? float_class_snan : float_class_qnan);
> +                p->cls = no_signaling_nans(status) ? float_class_qnan :
> +                                                     float_class_snan;
>                   return;
>               }
>               /* otherwise normal */

But parts_is_snan_frac also checks snan_bit_is_one.


r~

Re: [PATCH 2/3] fpu: Fix unexpected exception flags when converting infinity to OCP E4M3

[Richard Henderson]

On 2/25/26 22:08, Max Chou wrote:
> Infinity is a special case distinct from numeric overflow:
> - Numeric overflow: finite value exceeds format's max normal
>    -> overflow|inexact
> - Infinity conversion: input is already infinite
>    -> no flags
> 
> This commit fixes the unexpect exception flags by relocating the float
> exception flag update flow to be outside the uncanon_e4m3_overflow.
> And raising the overflow|inexact for numeric overflow in uncanon_normal.
> 
> Fixes: 27e989f99c ("fpu: Add conversion routines for OCP FP8 E4M3")
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   fpu/softfloat-parts.c.inc | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
> index a738758aee..3c323c0cec 100644
> --- a/fpu/softfloat-parts.c.inc
> +++ b/fpu/softfloat-parts.c.inc
> @@ -277,7 +277,6 @@ static void partsN(uncanon_e4m3_overflow)(FloatPartsN *p, float_status *s,
>                                             const FloatFmt *fmt, bool saturate)
>   {
>       assert(N == 64);
> -    float_raise(float_flag_overflow | float_flag_inexact, s);
>       if (saturate) {
>           p->exp = fmt->exp_max;
>           p->frac_hi = E4M3_NORMAL_FRAC_MAX;
> @@ -388,6 +387,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
>                   if (exp > exp_max || p->frac_hi > E4M3_NORMAL_FRAC_MAX) {
>                       partsN(uncanon_e4m3_overflow)(p, s, fmt, overflow_norm);
>                       exp = p->exp;
> +                    flags |= (float_flag_overflow | float_flag_inexact);
>                   }
>                   break;
>   

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 1/3] fpu: Fix repacking issues in the uncanonical step for E4M3 overflow

[Richard Henderson]

On 2/25/26 22:08, Max Chou wrote:
> In the uncanonical step, the input FloatParts will be repacked to the
> target FloatFmt. This commit fixes following issues after calling
> uncanon_e4m3_overflow in the uncanon/uncanon_normal functions.
> 
> - Add the local exp update after calling uncanon_e4m3_overflow in the
>    parts_uncanon_normal function.
> - Add the fraction shift after calling uncanon_e4m3_overflow in the
>    parts_uncanon function.
> 
> Fixes: 27e989f99c ("fpu: Add conversion routines for OCP FP8 E4M3")
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   fpu/softfloat-parts.c.inc | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
> index 61b07307bf..a738758aee 100644
> --- a/fpu/softfloat-parts.c.inc
> +++ b/fpu/softfloat-parts.c.inc
> @@ -387,6 +387,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
>               case float_expmax_e4m3:
>                   if (exp > exp_max || p->frac_hi > E4M3_NORMAL_FRAC_MAX) {
>                       partsN(uncanon_e4m3_overflow)(p, s, fmt, overflow_norm);
> +                    exp = p->exp;
>                   }
>                   break;
>   
> @@ -496,6 +497,7 @@ static void partsN(uncanon)(FloatPartsN *p, float_status *s,
>                   break;
>               case float_expmax_e4m3:
>                   partsN(uncanon_e4m3_overflow)(p, s, fmt, saturate);
> +                frac_shr(p, fmt->frac_shift);
>                   break;
>               case float_expmax_normal:
>               default:

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 3/3] fpu: Simplify OCP FP8 E4M3 NaN classification in parts_canonicalize

[Max Chou]

On 2026-02-26 08:06, Richard Henderson wrote:
> On 2/25/26 22:08, Max Chou wrote:
> > The OCP FP8 E4M3 format has only a single NaN encoding (0x7F/0xFF),
> > Replace the indirect check via parts_is_snan_frac with a direct
> > check of no_signaling_nans to make the intent clearer.
> > 
> > Signed-off-by: Max Chou <max.chou@sifive.com>
> > ---
> >   fpu/softfloat-parts.c.inc | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
> > index 3c323c0cec..5ef7e2d921 100644
> > --- a/fpu/softfloat-parts.c.inc
> > +++ b/fpu/softfloat-parts.c.inc
> > @@ -245,8 +245,8 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status,
> >           case float_expmax_e4m3:
> >               if (p->frac_hi == 0b111) {
> >                   frac_shl(p, fmt->frac_shift);
> > -                p->cls = (parts_is_snan_frac(p->frac_hi, status)
> > -                          ? float_class_snan : float_class_qnan);
> > +                p->cls = no_signaling_nans(status) ? float_class_qnan :
> > +                                                     float_class_snan;
> >                   return;
> >               }
> >               /* otherwise normal */
> 
> But parts_is_snan_frac also checks snan_bit_is_one.
> 
> 
> r~

Hi Richard,

You're right. I missed that parts_is_snan_frac respects both
snan_bit_is_one and no_signaling_nans flags and I just assumed that user
will use no_signaling_nans flag to define the E4M3 NaN.
The current implementation correctly allows targets to control E4M3 NaN
classification through either mechanism, and this change would have removed
the snan_bit_is_one flexibility.

I'll drop this patch and send a v2 series containing only the two bug fix
patches:

Thanks,
rnax