From: Max Chou <max.chou@sifive.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Chao Liu <chao.liu.zevorn@gmail.com>
Subject: Re: [PATCH v5 0/9] Add Zvfbfa extension support
Date: Thu, 12 Mar 2026 19:16:08 +0800 [thread overview]
Message-ID: <abKfuTO7zg5d67E8@sifive.com> (raw)
In-Reply-To: <CAKmqyKP7VKi21xfMAiKi9nmAGaaNdrtH9u=6ktCbWBk7kiRoJA@mail.gmail.com>
On 2026-03-09 14:51, Alistair Francis wrote:
> On Fri, Mar 6, 2026 at 5:13 PM Max Chou <max.chou@sifive.com> wrote:
> >
> > This patch series adds support for the RISC-V Zvfbfa extension, which
> > provides additional BF16 vector compute support.
> >
> > The isa spec of Zvfbfa extension is not ratified yet, so this patch
> > series is based on the latest draft of the spec (v0.1) and make the
> > Zvfbfa extension as an experimental extension.
>
> It's not only not ratified, there isn't even a draft spec. A personal
> GitHub repo without any tags or releases is not enough for us to take
> this unfortunately.
>
> >
> > The Zvfbfa extension adds a 1-bit field, altfmt, to the vtype CSR in
> > bit position 8.
> > The Zvfbfa extension requires the Zve32f and Zfbfmin extensions.
> >
> > Specification:
> > https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc
>
> Overall this looks ok. Once a draft spec is released we can apply it
>
> Alistair
>
Hi Alistair,
Thanks for the review. You asked for a pointer to the standalone ISA
spec repo for Zvfbfa — I want to explain why that doesn’t exist and
where the spec lives instead.
RVIA changed the ISA development workflow: new ISA specifications are
no longer developed in standalone repositories. Instead, they are
developed as forked branches of the base ISA manual repo
(riscv/riscv-isa-manual) and merged into it upon ratification [1].
For Zvfbfa specifically, the official spec artifact under this new
workflow is a PR against riscv-isa-manual [2], incorporating the spec
text [3]. The PR notes that the spec has passed internal review and
ARC review, as documented in the tech-unprivileged list thread [4].
PR #2743 is currently open, meaning ratification is pending but not
yet complete. Under the new workflow, merge into main of
riscv-isa-manual is the signal that ratification is finalized. If you
prefer to wait until that merge happens before applying this patchset,
I completely understand. Alternatively, if you are comfortable
accepting it as ratification-pending, I am happy to address any
remaining technical comments.
Please let me know how you would like to proceed.
References:
[1] https://lists.riscv.org/g/sig-documentation/message/275
[2] https://github.com/riscv/riscv-isa-manual/pull/2743
[3] https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc
[4] https://lists.riscv.org/g/tech-unprivileged/message/1031
https://lists.riscv.org/g/tech-unprivileged/message/1085
https://lists.riscv.org/g/tech-unprivileged/message/1109
Best regards,
rnax
next prev parent reply other threads:[~2026-03-12 11:17 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-06 7:10 [PATCH v5 0/9] Add Zvfbfa extension support Max Chou
2026-03-06 7:10 ` [PATCH v5 1/9] target/riscv: Add cfg properties for Zvfbfa extensions Max Chou
2026-03-09 4:44 ` Alistair Francis
2026-03-06 7:10 ` [PATCH v5 2/9] target/riscv: Add the Zvfbfa extension implied rule Max Chou
2026-03-09 4:45 ` Alistair Francis
2026-03-06 7:10 ` [PATCH v5 3/9] target/riscv: rvv: Add new VTYPE CSR field - altfmt Max Chou
2026-03-09 4:55 ` Alistair Francis
2026-03-16 9:20 ` Nutty.Liu
2026-03-06 7:10 ` [PATCH v5 4/9] target/riscv: rvv: Introduce reset_ill_vtype to reset illegal vtype CSR Max Chou
2026-03-09 4:55 ` Alistair Francis
2026-03-16 9:22 ` Nutty.Liu
2026-03-06 7:11 ` [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags Max Chou
2026-03-09 5:01 ` Alistair Francis
2026-03-12 11:42 ` Max Chou
2026-03-13 0:59 ` Alistair Francis
2026-03-06 7:11 ` [PATCH v5 6/9] target/riscv: Introduce altfmt into DisasContext Max Chou
2026-03-09 5:02 ` Alistair Francis
2026-03-06 7:11 ` [PATCH v5 7/9] target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension Max Chou
2026-03-09 5:04 ` Alistair Francis
2026-03-06 7:11 ` [PATCH v5 8/9] target/riscv: rvv: Support Zvfbfa vector bf16 operations Max Chou
2026-03-06 7:11 ` [PATCH v5 9/9] target/riscv: Expose Zvfbfa extension as an experimental cpu property Max Chou
2026-03-09 4:51 ` [PATCH v5 0/9] Add Zvfbfa extension support Alistair Francis
2026-03-12 11:16 ` Max Chou [this message]
2026-03-13 1:09 ` Alistair Francis
2026-03-16 8:28 ` Max Chou
2026-03-19 3:45 ` Alistair Francis
2026-03-26 3:42 ` Max Chou
2026-03-26 6:07 ` Chao Liu
2026-04-02 1:20 ` Alistair Francis
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