Re: [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags

[Max Chou <max.chou@sifive.com>]

On 2026-03-09 15:01, Alistair Francis wrote:
> On Fri, Mar 6, 2026 at 5:13 PM Max Chou <max.chou@sifive.com> wrote:
> >
> > We have more than 32-bits worth of state per TB, so use the
> > tb->cs_base, which is otherwise unused for RISC-V, as the extend flag.
> >
> > Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> > Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> > Signed-off-by: Max Chou <max.chou@sifive.com>
> > ---
> >  include/exec/translation-block.h | 1 +
> >  target/riscv/cpu.h               | 3 +++
> >  target/riscv/tcg/tcg-cpu.c       | 7 ++++++-
> >  3 files changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h
> > index 4f83d5bec9..40cc699031 100644
> > --- a/include/exec/translation-block.h
> > +++ b/include/exec/translation-block.h
> > @@ -65,6 +65,7 @@ struct TranslationBlock {
> >       * arm: an extension of tb->flags,
> >       * s390x: instruction data for EXECUTE,
> >       * sparc: the next pc of the instruction queue (for delay slots).
> > +     * riscv: an extension of tb->flags,
> >       */
> >      uint64_t cs_base;
> >
>

Hi Alistair,

I’m curious to know if you mean adding more details here, such as
specifying the bit width for misa (e.g., 32 bits) or the bit width for
ALTFMT (e.g., 1 bit).
If so, I’ll include these details in the v6 version.

Thanks,
rnax

> We need to update the comment in `struct TranslationBlock` for
> `target_ulong cs_base`
> 
> Alistair
>