[PATCH 0/4] riscv: Add PCIe support for UltraRISC DP1000 SoC

[PATCH 0/4] riscv: Add PCIe support for UltraRISC DP1000 SoC

[Jia Wang]

This patch series adds PCIe controller support for the UltraRISC DP1000 SoC.
The DP1000 is an 8-core 64-bit RISC-V SoC based on UltraRISC C100 cores,
supporting RV64GCBHX ISA with Hardware Virtualization and RISC-V H(v1.0)
Extension.

The PCIe controller is based on Synopsys DesignWare PCIe IP.
This series adds:
- Patch 1 adds the basic SoC family Kconfig support for UltraRISC platforms.
- Patch 2 adds the MAINTAINERS entry for the new driver.
- Patch 3 adds the device tree bindings documentation for the PCIe controller.
- Patch 4 introduces the PCIe host controller driver.

The patches have been tested on UltraRISC DP1000 development board with
various PCIe devices including NVMe SSDs and network cards, verifying
link establishment, enumeration, and basic data transfer.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
Jia Wang (3):
      riscv: add UltraRISC SoC family Kconfig support
      MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding
      dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

Xincheng Zhang (1):
      PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

 .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++
 MAINTAINERS                                        |   8 +
 arch/riscv/Kconfig.socs                            |  10 +
 drivers/pci/controller/dwc/Kconfig                 |  15 ++
 drivers/pci/controller/dwc/Makefile                |   1 +
 drivers/pci/controller/dwc/pcie-designware.h       |  22 +++
 drivers/pci/controller/dwc/pcie-ultrarisc.c        | 202 +++++++++++++++++++++
 7 files changed, 366 insertions(+)
---
base-commit: f338e77383789c0cae23ca3d48adcc5e9e137e3c
change-id: 20260310-ultrarisc-pcie-494998763399

Best regards,
--  
Jia Wang <wangjia@ultrarisc.com>

[PATCH 0/4] riscv: Add PCIe support for UltraRISC DP1000 SoC

[Jia Wang via B4 Relay]

This patch series adds PCIe controller support for the UltraRISC DP1000 SoC.
The DP1000 is an 8-core 64-bit RISC-V SoC based on UltraRISC C100 cores,
supporting RV64GCBHX ISA with Hardware Virtualization and RISC-V H(v1.0)
Extension.

The PCIe controller is based on Synopsys DesignWare PCIe IP.
This series adds:
- Patch 1 adds the basic SoC family Kconfig support for UltraRISC platforms.
- Patch 2 adds the MAINTAINERS entry for the new driver.
- Patch 3 adds the device tree bindings documentation for the PCIe controller.
- Patch 4 introduces the PCIe host controller driver.

The patches have been tested on UltraRISC DP1000 development board with
various PCIe devices including NVMe SSDs and network cards, verifying
link establishment, enumeration, and basic data transfer.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
Jia Wang (3):
      riscv: add UltraRISC SoC family Kconfig support
      MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding
      dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

Xincheng Zhang (1):
      PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

 .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++
 MAINTAINERS                                        |   8 +
 arch/riscv/Kconfig.socs                            |  10 +
 drivers/pci/controller/dwc/Kconfig                 |  15 ++
 drivers/pci/controller/dwc/Makefile                |   1 +
 drivers/pci/controller/dwc/pcie-designware.h       |  22 +++
 drivers/pci/controller/dwc/pcie-ultrarisc.c        | 202 +++++++++++++++++++++
 7 files changed, 366 insertions(+)
---
base-commit: f338e77383789c0cae23ca3d48adcc5e9e137e3c
change-id: 20260310-ultrarisc-pcie-494998763399

Best regards,
--  
Jia Wang <wangjia@ultrarisc.com>



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[PATCH 0/4] riscv: Add PCIe support for UltraRISC DP1000 SoC

[Jia Wang via B4 Relay]

This patch series adds PCIe controller support for the UltraRISC DP1000 SoC.
The DP1000 is an 8-core 64-bit RISC-V SoC based on UltraRISC C100 cores,
supporting RV64GCBHX ISA with Hardware Virtualization and RISC-V H(v1.0)
Extension.

The PCIe controller is based on Synopsys DesignWare PCIe IP.
This series adds:
- Patch 1 adds the basic SoC family Kconfig support for UltraRISC platforms.
- Patch 2 adds the MAINTAINERS entry for the new driver.
- Patch 3 adds the device tree bindings documentation for the PCIe controller.
- Patch 4 introduces the PCIe host controller driver.

The patches have been tested on UltraRISC DP1000 development board with
various PCIe devices including NVMe SSDs and network cards, verifying
link establishment, enumeration, and basic data transfer.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
Jia Wang (3):
      riscv: add UltraRISC SoC family Kconfig support
      MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding
      dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

Xincheng Zhang (1):
      PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

 .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++
 MAINTAINERS                                        |   8 +
 arch/riscv/Kconfig.socs                            |  10 +
 drivers/pci/controller/dwc/Kconfig                 |  15 ++
 drivers/pci/controller/dwc/Makefile                |   1 +
 drivers/pci/controller/dwc/pcie-designware.h       |  22 +++
 drivers/pci/controller/dwc/pcie-ultrarisc.c        | 202 +++++++++++++++++++++
 7 files changed, 366 insertions(+)
---
base-commit: f338e77383789c0cae23ca3d48adcc5e9e137e3c
change-id: 20260310-ultrarisc-pcie-494998763399

Best regards,
--  
Jia Wang <wangjia@ultrarisc.com>

[PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Jia Wang]

The first SoC in the UltraRISC series is UR-DP1000, containing octa
UltraRISC C100 cores.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 arch/riscv/Kconfig.socs | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index d621b85dd63b..f49d3ccaacde 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -84,6 +84,16 @@ config ARCH_THEAD
 	help
 	  This enables support for the RISC-V based T-HEAD SoCs.
 
+config ARCH_ULTRARISC
+	bool "UltraRISC RISC-V SoCs"
+	depends on MMU && !XIP_KERNEL
+	help
+	 This enables support for UltraRISC SoC platform hardware,
+	 including boards based on the UR-DP1000.
+	 UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
+	 the RV64GCBHX ISA. It supports Hardware Virtualization
+	 and RISC-V RV64 ISA H(v1.0) Extension.
+
 config ARCH_VIRT
 	bool "QEMU Virt Machine"
 	select POWER_RESET

-- 
2.34.1

[PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Jia Wang via B4 Relay]

From: Jia Wang <wangjia@ultrarisc.com>

The first SoC in the UltraRISC series is UR-DP1000, containing octa
UltraRISC C100 cores.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 arch/riscv/Kconfig.socs | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index d621b85dd63b..f49d3ccaacde 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -84,6 +84,16 @@ config ARCH_THEAD
 	help
 	  This enables support for the RISC-V based T-HEAD SoCs.
 
+config ARCH_ULTRARISC
+	bool "UltraRISC RISC-V SoCs"
+	depends on MMU && !XIP_KERNEL
+	help
+	 This enables support for UltraRISC SoC platform hardware,
+	 including boards based on the UR-DP1000.
+	 UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
+	 the RV64GCBHX ISA. It supports Hardware Virtualization
+	 and RISC-V RV64 ISA H(v1.0) Extension.
+
 config ARCH_VIRT
 	bool "QEMU Virt Machine"
 	select POWER_RESET

-- 
2.34.1



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[PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Jia Wang via B4 Relay]

From: Jia Wang <wangjia@ultrarisc.com>

The first SoC in the UltraRISC series is UR-DP1000, containing octa
UltraRISC C100 cores.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 arch/riscv/Kconfig.socs | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index d621b85dd63b..f49d3ccaacde 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -84,6 +84,16 @@ config ARCH_THEAD
 	help
 	  This enables support for the RISC-V based T-HEAD SoCs.
 
+config ARCH_ULTRARISC
+	bool "UltraRISC RISC-V SoCs"
+	depends on MMU && !XIP_KERNEL
+	help
+	 This enables support for UltraRISC SoC platform hardware,
+	 including boards based on the UR-DP1000.
+	 UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
+	 the RV64GCBHX ISA. It supports Hardware Virtualization
+	 and RISC-V RV64 ISA H(v1.0) Extension.
+
 config ARCH_VIRT
 	bool "QEMU Virt Machine"
 	select POWER_RESET

-- 
2.34.1

Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1130 bytes --]

On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> The first SoC in the UltraRISC series is UR-DP1000, containing octa
> UltraRISC C100 cores.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  arch/riscv/Kconfig.socs | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index d621b85dd63b..f49d3ccaacde 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -84,6 +84,16 @@ config ARCH_THEAD
>  	help
>  	  This enables support for the RISC-V based T-HEAD SoCs.
>  
> +config ARCH_ULTRARISC
> +	bool "UltraRISC RISC-V SoCs"
> +	depends on MMU && !XIP_KERNEL

Why do you depend on "MMU && !XIP_KERNEL"?

> +	help
> +	 This enables support for UltraRISC SoC platform hardware,
> +	 including boards based on the UR-DP1000.
> +	 UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> +	 the RV64GCBHX ISA. It supports Hardware Virtualization
> +	 and RISC-V RV64 ISA H(v1.0) Extension.
> +
>  config ARCH_VIRT
>  	bool "QEMU Virt Machine"
>  	select POWER_RESET
> 
> -- 
> 2.34.1
> 

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Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1130 bytes --]

On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> The first SoC in the UltraRISC series is UR-DP1000, containing octa
> UltraRISC C100 cores.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  arch/riscv/Kconfig.socs | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index d621b85dd63b..f49d3ccaacde 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -84,6 +84,16 @@ config ARCH_THEAD
>  	help
>  	  This enables support for the RISC-V based T-HEAD SoCs.
>  
> +config ARCH_ULTRARISC
> +	bool "UltraRISC RISC-V SoCs"
> +	depends on MMU && !XIP_KERNEL

Why do you depend on "MMU && !XIP_KERNEL"?

> +	help
> +	 This enables support for UltraRISC SoC platform hardware,
> +	 including boards based on the UR-DP1000.
> +	 UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> +	 the RV64GCBHX ISA. It supports Hardware Virtualization
> +	 and RISC-V RV64 ISA H(v1.0) Extension.
> +
>  config ARCH_VIRT
>  	bool "QEMU Virt Machine"
>  	select POWER_RESET
> 
> -- 
> 2.34.1
> 

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Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Jia Wang]

On 2026-03-16 14:39 +0000, Conor Dooley wrote:
> On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > UltraRISC C100 cores.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  arch/riscv/Kconfig.socs | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index d621b85dd63b..f49d3ccaacde 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -84,6 +84,16 @@ config ARCH_THEAD
> >  	help
> >  	  This enables support for the RISC-V based T-HEAD SoCs.
> >  
> > +config ARCH_ULTRARISC
> > +	bool "UltraRISC RISC-V SoCs"
> > +	depends on MMU && !XIP_KERNEL
> 
> Why do you depend on "MMU && !XIP_KERNEL"?
>
Hi Conor,

Thanks for the review.

The dependency on "MMU" was added conservatively, but the DP1000 hardware
does not strictly require MMU. I will remove this dependency in the
next version of the patch.

The "!XIP_KERNEL" dependency is retained because the platform does not
support executing the kernel directly from storage, so the kernel
must be loaded into RAM before execution.

Best regards,
Jia 
> > +	help
> > +	 This enables support for UltraRISC SoC platform hardware,
> > +	 including boards based on the UR-DP1000.
> > +	 UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> > +	 the RV64GCBHX ISA. It supports Hardware Virtualization
> > +	 and RISC-V RV64 ISA H(v1.0) Extension.
> > +
> >  config ARCH_VIRT
> >  	bool "QEMU Virt Machine"
> >  	select POWER_RESET
> > 
> > -- 
> > 2.34.1
> > 

Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Jia Wang]

On 2026-03-16 14:39 +0000, Conor Dooley wrote:
> On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > UltraRISC C100 cores.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  arch/riscv/Kconfig.socs | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index d621b85dd63b..f49d3ccaacde 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -84,6 +84,16 @@ config ARCH_THEAD
> >  	help
> >  	  This enables support for the RISC-V based T-HEAD SoCs.
> >  
> > +config ARCH_ULTRARISC
> > +	bool "UltraRISC RISC-V SoCs"
> > +	depends on MMU && !XIP_KERNEL
> 
> Why do you depend on "MMU && !XIP_KERNEL"?
>
Hi Conor,

Thanks for the review.

The dependency on "MMU" was added conservatively, but the DP1000 hardware
does not strictly require MMU. I will remove this dependency in the
next version of the patch.

The "!XIP_KERNEL" dependency is retained because the platform does not
support executing the kernel directly from storage, so the kernel
must be loaded into RAM before execution.

Best regards,
Jia 
> > +	help
> > +	 This enables support for UltraRISC SoC platform hardware,
> > +	 including boards based on the UR-DP1000.
> > +	 UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> > +	 the RV64GCBHX ISA. It supports Hardware Virtualization
> > +	 and RISC-V RV64 ISA H(v1.0) Extension.
> > +
> >  config ARCH_VIRT
> >  	bool "QEMU Virt Machine"
> >  	select POWER_RESET
> > 
> > -- 
> > 2.34.1
> > 



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Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1725 bytes --]

On Tue, Mar 17, 2026 at 02:46:24PM +0800, Jia Wang wrote:
> On 2026-03-16 14:39 +0000, Conor Dooley wrote:
> > On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> > > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > > UltraRISC C100 cores.
> > > 
> > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > > ---
> > >  arch/riscv/Kconfig.socs | 10 ++++++++++
> > >  1 file changed, 10 insertions(+)
> > > 
> > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > index d621b85dd63b..f49d3ccaacde 100644
> > > --- a/arch/riscv/Kconfig.socs
> > > +++ b/arch/riscv/Kconfig.socs
> > > @@ -84,6 +84,16 @@ config ARCH_THEAD
> > >  	help
> > >  	  This enables support for the RISC-V based T-HEAD SoCs.
> > >  
> > > +config ARCH_ULTRARISC
> > > +	bool "UltraRISC RISC-V SoCs"
> > > +	depends on MMU && !XIP_KERNEL
> > 
> > Why do you depend on "MMU && !XIP_KERNEL"?
> >
> Hi Conor,
> 
> Thanks for the review.
> 
> The dependency on "MMU" was added conservatively, but the DP1000 hardware
> does not strictly require MMU. I will remove this dependency in the
> next version of the patch.
> 
> The "!XIP_KERNEL" dependency is retained because the platform does not
> support executing the kernel directly from storage, so the kernel
> must be loaded into RAM before execution.

I would imagine the reason these are here is because you copied this
from one of the other entries. They have "depends on MMU && !XIP_KERNEL"
is because they have errata that require alternatives to resolve, and
alternatives require those conditions. IMO you should remove these entirely,
especially since XIP_KERNEL is about to be removed for riscv soon
anyway.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1725 bytes --]

On Tue, Mar 17, 2026 at 02:46:24PM +0800, Jia Wang wrote:
> On 2026-03-16 14:39 +0000, Conor Dooley wrote:
> > On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> > > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > > UltraRISC C100 cores.
> > > 
> > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > > ---
> > >  arch/riscv/Kconfig.socs | 10 ++++++++++
> > >  1 file changed, 10 insertions(+)
> > > 
> > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > index d621b85dd63b..f49d3ccaacde 100644
> > > --- a/arch/riscv/Kconfig.socs
> > > +++ b/arch/riscv/Kconfig.socs
> > > @@ -84,6 +84,16 @@ config ARCH_THEAD
> > >  	help
> > >  	  This enables support for the RISC-V based T-HEAD SoCs.
> > >  
> > > +config ARCH_ULTRARISC
> > > +	bool "UltraRISC RISC-V SoCs"
> > > +	depends on MMU && !XIP_KERNEL
> > 
> > Why do you depend on "MMU && !XIP_KERNEL"?
> >
> Hi Conor,
> 
> Thanks for the review.
> 
> The dependency on "MMU" was added conservatively, but the DP1000 hardware
> does not strictly require MMU. I will remove this dependency in the
> next version of the patch.
> 
> The "!XIP_KERNEL" dependency is retained because the platform does not
> support executing the kernel directly from storage, so the kernel
> must be loaded into RAM before execution.

I would imagine the reason these are here is because you copied this
from one of the other entries. They have "depends on MMU && !XIP_KERNEL"
is because they have errata that require alternatives to resolve, and
alternatives require those conditions. IMO you should remove these entirely,
especially since XIP_KERNEL is about to be removed for riscv soon
anyway.

[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

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Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Jia Wang]

On 2026-03-17 13:02 +0000, Conor Dooley wrote:
> On Tue, Mar 17, 2026 at 02:46:24PM +0800, Jia Wang wrote:
> > On 2026-03-16 14:39 +0000, Conor Dooley wrote:
> > > On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> > > > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > > > UltraRISC C100 cores.
> > > > 
> > > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > > > ---
> > > >  arch/riscv/Kconfig.socs | 10 ++++++++++
> > > >  1 file changed, 10 insertions(+)
> > > > 
> > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > > index d621b85dd63b..f49d3ccaacde 100644
> > > > --- a/arch/riscv/Kconfig.socs
> > > > +++ b/arch/riscv/Kconfig.socs
> > > > @@ -84,6 +84,16 @@ config ARCH_THEAD
> > > >  	help
> > > >  	  This enables support for the RISC-V based T-HEAD SoCs.
> > > >  
> > > > +config ARCH_ULTRARISC
> > > > +	bool "UltraRISC RISC-V SoCs"
> > > > +	depends on MMU && !XIP_KERNEL
> > > 
> > > Why do you depend on "MMU && !XIP_KERNEL"?
> > >
> > Hi Conor,
> > 
> > Thanks for the review.
> > 
> > The dependency on "MMU" was added conservatively, but the DP1000 hardware
> > does not strictly require MMU. I will remove this dependency in the
> > next version of the patch.
> > 
> > The "!XIP_KERNEL" dependency is retained because the platform does not
> > support executing the kernel directly from storage, so the kernel
> > must be loaded into RAM before execution.
> 
> I would imagine the reason these are here is because you copied this
> from one of the other entries. They have "depends on MMU && !XIP_KERNEL"
> is because they have errata that require alternatives to resolve, and
> alternatives require those conditions. IMO you should remove these entirely,
> especially since XIP_KERNEL is about to be removed for riscv soon
> anyway.
Thanks for the clarification.

I will remove the entire "depends on MMU && !XIP_KERNEL" line in the next
revision.

Thanks again for the guidance.

Best regards,
Jia

Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

[Jia Wang]

On 2026-03-17 13:02 +0000, Conor Dooley wrote:
> On Tue, Mar 17, 2026 at 02:46:24PM +0800, Jia Wang wrote:
> > On 2026-03-16 14:39 +0000, Conor Dooley wrote:
> > > On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> > > > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > > > UltraRISC C100 cores.
> > > > 
> > > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > > > ---
> > > >  arch/riscv/Kconfig.socs | 10 ++++++++++
> > > >  1 file changed, 10 insertions(+)
> > > > 
> > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > > index d621b85dd63b..f49d3ccaacde 100644
> > > > --- a/arch/riscv/Kconfig.socs
> > > > +++ b/arch/riscv/Kconfig.socs
> > > > @@ -84,6 +84,16 @@ config ARCH_THEAD
> > > >  	help
> > > >  	  This enables support for the RISC-V based T-HEAD SoCs.
> > > >  
> > > > +config ARCH_ULTRARISC
> > > > +	bool "UltraRISC RISC-V SoCs"
> > > > +	depends on MMU && !XIP_KERNEL
> > > 
> > > Why do you depend on "MMU && !XIP_KERNEL"?
> > >
> > Hi Conor,
> > 
> > Thanks for the review.
> > 
> > The dependency on "MMU" was added conservatively, but the DP1000 hardware
> > does not strictly require MMU. I will remove this dependency in the
> > next version of the patch.
> > 
> > The "!XIP_KERNEL" dependency is retained because the platform does not
> > support executing the kernel directly from storage, so the kernel
> > must be loaded into RAM before execution.
> 
> I would imagine the reason these are here is because you copied this
> from one of the other entries. They have "depends on MMU && !XIP_KERNEL"
> is because they have errata that require alternatives to resolve, and
> alternatives require those conditions. IMO you should remove these entirely,
> especially since XIP_KERNEL is about to be removed for riscv soon
> anyway.
Thanks for the clarification.

I will remove the entire "depends on MMU && !XIP_KERNEL" line in the next
revision.

Thanks again for the guidance.

Best regards,
Jia


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[PATCH 2/4] MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding

[Jia Wang]

Add a MAINTAINERS entry for the UltraRISC DP1000 PCIe host driver and its
DT binding.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96ea84948d76..5caa383fe0ec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20571,6 +20571,14 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
 F:	drivers/pci/controller/plda/pcie-starfive.c
 
+PCIE DRIVER FOR ULTRARISC DP1000
+M:	Xincheng Zhang <zhangxincheng@ultrarisc.com>
+M:	Jia Wang <wangjia@ultrarisc.com>
+L:	linux-pci@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
+F:	drivers/pci/controller/dwc/pcie-ultrarisc.c
+
 PCIE ENDPOINT DRIVER FOR QUALCOMM
 M:	Manivannan Sadhasivam <mani@kernel.org>
 L:	linux-pci@vger.kernel.org

-- 
2.34.1

[PATCH 2/4] MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding

[Jia Wang via B4 Relay]

From: Jia Wang <wangjia@ultrarisc.com>

Add a MAINTAINERS entry for the UltraRISC DP1000 PCIe host driver and its
DT binding.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96ea84948d76..5caa383fe0ec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20571,6 +20571,14 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
 F:	drivers/pci/controller/plda/pcie-starfive.c
 
+PCIE DRIVER FOR ULTRARISC DP1000
+M:	Xincheng Zhang <zhangxincheng@ultrarisc.com>
+M:	Jia Wang <wangjia@ultrarisc.com>
+L:	linux-pci@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
+F:	drivers/pci/controller/dwc/pcie-ultrarisc.c
+
 PCIE ENDPOINT DRIVER FOR QUALCOMM
 M:	Manivannan Sadhasivam <mani@kernel.org>
 L:	linux-pci@vger.kernel.org

-- 
2.34.1



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[PATCH 2/4] MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding

[Jia Wang via B4 Relay]

From: Jia Wang <wangjia@ultrarisc.com>

Add a MAINTAINERS entry for the UltraRISC DP1000 PCIe host driver and its
DT binding.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96ea84948d76..5caa383fe0ec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20571,6 +20571,14 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
 F:	drivers/pci/controller/plda/pcie-starfive.c
 
+PCIE DRIVER FOR ULTRARISC DP1000
+M:	Xincheng Zhang <zhangxincheng@ultrarisc.com>
+M:	Jia Wang <wangjia@ultrarisc.com>
+L:	linux-pci@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
+F:	drivers/pci/controller/dwc/pcie-ultrarisc.c
+
 PCIE ENDPOINT DRIVER FOR QUALCOMM
 M:	Manivannan Sadhasivam <mani@kernel.org>
 L:	linux-pci@vger.kernel.org

-- 
2.34.1

[PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang]

Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
new file mode 100644
index 000000000000..b50ff98dd878
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC DP1000 PCIe Host Controller
+
+description: |
+  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
+  This binding describes the UltraRISC specific extensions to the base DesignWare
+  PCIe binding.
+
+maintainers:
+  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
+  - Jia Wang <wangjia@ultrarisc.com>
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    const: ultrarisc,dp1000-pcie
+
+  reg:
+      - description: Data Bus Interface (DBI) registers.
+      - description: PCIe configuration space region.
+
+  reg-names:
+    items:
+      - const: dbi
+      - const: config
+
+  num-lanes:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Number of lanes to use.
+      Valid values: 4, 16.
+
+  max-link-speed:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    const: 4
+    description:
+      Maximum PCIe link speed supported. 4 for Gen4.
+
+  interrupt-names:
+    items:
+      - const: msi
+      - const: inta
+      - const: intb
+      - const: intc
+      - const: intd
+
+  device_type:
+    const: pci
+
+  dma-coherent:
+    type: boolean
+
+  bus-range:
+    description:
+      PCI bus range associated with this controller.
+
+  interrupt-map-mask:
+    description:
+      PCI interrupt map mask for this controller.
+
+  interrupt-map:
+    description:
+      PCI interrupt map for this controller.
+
+  required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+  - device_type
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    pcie_x16: pcie@21000000 {
+        compatible = "ultrarisc,dp1000-pcie";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        #interrupt-cells = <1>;
+        reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */
+              <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */
+        reg-names = "dbi", "config";
+        device_type = "pci";
+        dma-coherent;
+        bus-range = <0x0 0xff>;
+        num-lanes = <16>;
+        ranges = <0x81000000  0x0 0x4fbf0000  0x0 0x4fbf0000  0x0 0x00400000>, /* io */
+                 <0x82000000  0x0 0x40000000  0x0 0x40000000  0x0 0x0fbf0000>, /* mem32 */
+                 <0xc3000000 0x40 0x00000000 0x40 0x00000000  0xd 0x00000000>; /* mem64 prefetchable */
+        max-link-speed = <4>;
+        interrupt-parent = <&plic>;
+        interrupts = <43>, <44>, <45>, <46>, <47>;
+        interrupt-names = "msi", "inta", "intb", "intc", "intd";
+        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+        interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
+                        <0x0 0x0 0x0 0x2 &plic 45>,
+                        <0x0 0x0 0x0 0x3 &plic 46>,
+                        <0x0 0x0 0x0 0x4 &plic 47>;
+    };

-- 
2.34.1

[PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang via B4 Relay]

From: Jia Wang <wangjia@ultrarisc.com>

Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
new file mode 100644
index 000000000000..b50ff98dd878
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC DP1000 PCIe Host Controller
+
+description: |
+  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
+  This binding describes the UltraRISC specific extensions to the base DesignWare
+  PCIe binding.
+
+maintainers:
+  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
+  - Jia Wang <wangjia@ultrarisc.com>
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    const: ultrarisc,dp1000-pcie
+
+  reg:
+      - description: Data Bus Interface (DBI) registers.
+      - description: PCIe configuration space region.
+
+  reg-names:
+    items:
+      - const: dbi
+      - const: config
+
+  num-lanes:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Number of lanes to use.
+      Valid values: 4, 16.
+
+  max-link-speed:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    const: 4
+    description:
+      Maximum PCIe link speed supported. 4 for Gen4.
+
+  interrupt-names:
+    items:
+      - const: msi
+      - const: inta
+      - const: intb
+      - const: intc
+      - const: intd
+
+  device_type:
+    const: pci
+
+  dma-coherent:
+    type: boolean
+
+  bus-range:
+    description:
+      PCI bus range associated with this controller.
+
+  interrupt-map-mask:
+    description:
+      PCI interrupt map mask for this controller.
+
+  interrupt-map:
+    description:
+      PCI interrupt map for this controller.
+
+  required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+  - device_type
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    pcie_x16: pcie@21000000 {
+        compatible = "ultrarisc,dp1000-pcie";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        #interrupt-cells = <1>;
+        reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */
+              <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */
+        reg-names = "dbi", "config";
+        device_type = "pci";
+        dma-coherent;
+        bus-range = <0x0 0xff>;
+        num-lanes = <16>;
+        ranges = <0x81000000  0x0 0x4fbf0000  0x0 0x4fbf0000  0x0 0x00400000>, /* io */
+                 <0x82000000  0x0 0x40000000  0x0 0x40000000  0x0 0x0fbf0000>, /* mem32 */
+                 <0xc3000000 0x40 0x00000000 0x40 0x00000000  0xd 0x00000000>; /* mem64 prefetchable */
+        max-link-speed = <4>;
+        interrupt-parent = <&plic>;
+        interrupts = <43>, <44>, <45>, <46>, <47>;
+        interrupt-names = "msi", "inta", "intb", "intc", "intd";
+        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+        interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
+                        <0x0 0x0 0x0 0x2 &plic 45>,
+                        <0x0 0x0 0x0 0x3 &plic 46>,
+                        <0x0 0x0 0x0 0x4 &plic 47>;
+    };

-- 
2.34.1



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[PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang via B4 Relay]

From: Jia Wang <wangjia@ultrarisc.com>

Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
new file mode 100644
index 000000000000..b50ff98dd878
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC DP1000 PCIe Host Controller
+
+description: |
+  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
+  This binding describes the UltraRISC specific extensions to the base DesignWare
+  PCIe binding.
+
+maintainers:
+  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
+  - Jia Wang <wangjia@ultrarisc.com>
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    const: ultrarisc,dp1000-pcie
+
+  reg:
+      - description: Data Bus Interface (DBI) registers.
+      - description: PCIe configuration space region.
+
+  reg-names:
+    items:
+      - const: dbi
+      - const: config
+
+  num-lanes:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Number of lanes to use.
+      Valid values: 4, 16.
+
+  max-link-speed:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    const: 4
+    description:
+      Maximum PCIe link speed supported. 4 for Gen4.
+
+  interrupt-names:
+    items:
+      - const: msi
+      - const: inta
+      - const: intb
+      - const: intc
+      - const: intd
+
+  device_type:
+    const: pci
+
+  dma-coherent:
+    type: boolean
+
+  bus-range:
+    description:
+      PCI bus range associated with this controller.
+
+  interrupt-map-mask:
+    description:
+      PCI interrupt map mask for this controller.
+
+  interrupt-map:
+    description:
+      PCI interrupt map for this controller.
+
+  required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+  - device_type
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    pcie_x16: pcie@21000000 {
+        compatible = "ultrarisc,dp1000-pcie";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        #interrupt-cells = <1>;
+        reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */
+              <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */
+        reg-names = "dbi", "config";
+        device_type = "pci";
+        dma-coherent;
+        bus-range = <0x0 0xff>;
+        num-lanes = <16>;
+        ranges = <0x81000000  0x0 0x4fbf0000  0x0 0x4fbf0000  0x0 0x00400000>, /* io */
+                 <0x82000000  0x0 0x40000000  0x0 0x40000000  0x0 0x0fbf0000>, /* mem32 */
+                 <0xc3000000 0x40 0x00000000 0x40 0x00000000  0xd 0x00000000>; /* mem64 prefetchable */
+        max-link-speed = <4>;
+        interrupt-parent = <&plic>;
+        interrupts = <43>, <44>, <45>, <46>, <47>;
+        interrupt-names = "msi", "inta", "intb", "intc", "intd";
+        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+        interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
+                        <0x0 0x0 0x0 0x2 &plic 45>,
+                        <0x0 0x0 0x0 0x3 &plic 46>,
+                        <0x0 0x0 0x0 0x4 &plic 47>;
+    };

-- 
2.34.1

Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Rob Herring (Arm)]

On Mon, 16 Mar 2026 15:06:59 +0800, Jia Wang wrote:
> Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:26:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: [error] syntax error: mapping values are not allowed here (syntax)

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml: ignoring, error parsing file
make[2]: *** Deleting file 'Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts'
Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here
make[2]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts] Error 1
make[2]: *** Waiting for unfinished jobs....
./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1606: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260316-ultrarisc-pcie-v1-3-ef2946ede698@ultrarisc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Rob Herring (Arm)]

On Mon, 16 Mar 2026 15:06:59 +0800, Jia Wang wrote:
> Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:26:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: [error] syntax error: mapping values are not allowed here (syntax)

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml: ignoring, error parsing file
make[2]: *** Deleting file 'Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts'
Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here
make[2]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts] Error 1
make[2]: *** Waiting for unfinished jobs....
./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1606: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260316-ultrarisc-pcie-v1-3-ef2946ede698@ultrarisc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


_______________________________________________
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Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang]

On 2026-03-16 03:21 -0500, Rob Herring (Arm) wrote:
> 
> On Mon, 16 Mar 2026 15:06:59 +0800, Jia Wang wrote:
> > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
> >  1 file changed, 108 insertions(+)
> > 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:26:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
> ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: [error] syntax error: mapping values are not allowed here (syntax)
> 
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml: ignoring, error parsing file
> make[2]: *** Deleting file 'Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts'
> Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here
> make[2]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts] Error 1
> make[2]: *** Waiting for unfinished jobs....
> ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here
> make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1606: dt_binding_check] Error 2
> make: *** [Makefile:248: __sub-make] Error 2
> 
> doc reference errors (make refcheckdocs):
> 
> See https://patchwork.kernel.org/project/devicetree/patch/20260316-ultrarisc-pcie-v1-3-ef2946ede698@ultrarisc.com
> 
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
> 
>
Thanks for the report.

I’ve re-run `make dt_binding_check` locally with updated `yamllint` and
`dtschema`, and I can reproduce the issues you pointed out.

I will fix the indentation and correct the syntax error, re-validate the
schema using the full `dt_binding_check`, and send a v2.

Thanks for the guidance.

Best regards,
Jia 

Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang]

On 2026-03-16 03:21 -0500, Rob Herring (Arm) wrote:
> 
> On Mon, 16 Mar 2026 15:06:59 +0800, Jia Wang wrote:
> > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
> >  1 file changed, 108 insertions(+)
> > 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:26:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
> ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: [error] syntax error: mapping values are not allowed here (syntax)
> 
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml: ignoring, error parsing file
> make[2]: *** Deleting file 'Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts'
> Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here
> make[2]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts] Error 1
> make[2]: *** Waiting for unfinished jobs....
> ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here
> make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1606: dt_binding_check] Error 2
> make: *** [Makefile:248: __sub-make] Error 2
> 
> doc reference errors (make refcheckdocs):
> 
> See https://patchwork.kernel.org/project/devicetree/patch/20260316-ultrarisc-pcie-v1-3-ef2946ede698@ultrarisc.com
> 
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
> 
>
Thanks for the report.

I’ve re-run `make dt_binding_check` locally with updated `yamllint` and
`dtschema`, and I can reproduce the issues you pointed out.

I will fix the indentation and correct the syntax error, re-validate the
schema using the full `dt_binding_check`, and send a v2.

Thanks for the guidance.

Best regards,
Jia 



_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Krzysztof Kozlowski]

On 16/03/2026 08:06, Jia Wang via B4 Relay wrote:
> From: Jia Wang <wangjia@ultrarisc.com>
> 
> Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> new file mode 100644
> index 000000000000..b50ff98dd878
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: UltraRISC DP1000 PCIe Host Controller
> +
> +description: |
> +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
> +  This binding describes the UltraRISC specific extensions to the base DesignWare
> +  PCIe binding.
> +
> +maintainers:
> +  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
> +  - Jia Wang <wangjia@ultrarisc.com>
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    const: ultrarisc,dp1000-pcie
> +
> +  reg:
> +      - description: Data Bus Interface (DBI) registers.
> +      - description: PCIe configuration space region.

Never tested. Test your patches before sending to avoid common mistakes.
Several issues here are just duplicating known issue.

Read also sashiko review of your code.

https://sashiko.dev/#/patchset/20260316-ultrarisc-pcie-v1-0-ef2946ede698%40ultrarisc.com

Best regards,
Krzysztof

Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Krzysztof Kozlowski]

On 16/03/2026 08:06, Jia Wang via B4 Relay wrote:
> From: Jia Wang <wangjia@ultrarisc.com>
> 
> Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> new file mode 100644
> index 000000000000..b50ff98dd878
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: UltraRISC DP1000 PCIe Host Controller
> +
> +description: |
> +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
> +  This binding describes the UltraRISC specific extensions to the base DesignWare
> +  PCIe binding.
> +
> +maintainers:
> +  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
> +  - Jia Wang <wangjia@ultrarisc.com>
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    const: ultrarisc,dp1000-pcie
> +
> +  reg:
> +      - description: Data Bus Interface (DBI) registers.
> +      - description: PCIe configuration space region.

Never tested. Test your patches before sending to avoid common mistakes.
Several issues here are just duplicating known issue.

Read also sashiko review of your code.

https://sashiko.dev/#/patchset/20260316-ultrarisc-pcie-v1-0-ef2946ede698%40ultrarisc.com

Best regards,
Krzysztof

_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang]

On 2026-03-16 11:05 +0100, Krzysztof Kozlowski wrote:
> On 16/03/2026 08:06, Jia Wang via B4 Relay wrote:
> > From: Jia Wang <wangjia@ultrarisc.com>
> > 
> > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
> >  1 file changed, 108 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> > new file mode 100644
> > index 000000000000..b50ff98dd878
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> > @@ -0,0 +1,108 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: UltraRISC DP1000 PCIe Host Controller
> > +
> > +description: |
> > +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
> > +  This binding describes the UltraRISC specific extensions to the base DesignWare
> > +  PCIe binding.
> > +
> > +maintainers:
> > +  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > +  - Jia Wang <wangjia@ultrarisc.com>
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    const: ultrarisc,dp1000-pcie
> > +
> > +  reg:
> > +      - description: Data Bus Interface (DBI) registers.
> > +      - description: PCIe configuration space region.
> 
> Never tested. Test your patches before sending to avoid common mistakes.
> Several issues here are just duplicating known issue.
> 
> Read also sashiko review of your code.
> 
> https://sashiko.dev/#/patchset/20260316-ultrarisc-pcie-v1-0-ef2946ede698%40ultrarisc.com
>

Thanks for the review and the pointer.

I have checked the Sashiko report and will fix all issues in the next version. 

> Best regards,
> Krzysztof
> 

Best regards,
Jia

Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang]

On 2026-03-16 11:05 +0100, Krzysztof Kozlowski wrote:
> On 16/03/2026 08:06, Jia Wang via B4 Relay wrote:
> > From: Jia Wang <wangjia@ultrarisc.com>
> > 
> > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
> >  1 file changed, 108 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> > new file mode 100644
> > index 000000000000..b50ff98dd878
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> > @@ -0,0 +1,108 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: UltraRISC DP1000 PCIe Host Controller
> > +
> > +description: |
> > +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
> > +  This binding describes the UltraRISC specific extensions to the base DesignWare
> > +  PCIe binding.
> > +
> > +maintainers:
> > +  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > +  - Jia Wang <wangjia@ultrarisc.com>
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    const: ultrarisc,dp1000-pcie
> > +
> > +  reg:
> > +      - description: Data Bus Interface (DBI) registers.
> > +      - description: PCIe configuration space region.
> 
> Never tested. Test your patches before sending to avoid common mistakes.
> Several issues here are just duplicating known issue.
> 
> Read also sashiko review of your code.
> 
> https://sashiko.dev/#/patchset/20260316-ultrarisc-pcie-v1-0-ef2946ede698%40ultrarisc.com
>

Thanks for the review and the pointer.

I have checked the Sashiko report and will fix all issues in the next version. 

> Best regards,
> Krzysztof
> 

Best regards,
Jia


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Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Yao Zi]

On Mon, Mar 16, 2026 at 03:06:59PM +0800, Jia Wang via B4 Relay wrote:
> From: Jia Wang <wangjia@ultrarisc.com>
> 
> Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> new file mode 100644
> index 000000000000..b50ff98dd878
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: UltraRISC DP1000 PCIe Host Controller
> +
> +description: |
> +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.

If so, you should probably refer snps,dw-pcie.yaml to avoid
some duplication.

Regards,
Yao Zi

Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Yao Zi]

On Mon, Mar 16, 2026 at 03:06:59PM +0800, Jia Wang via B4 Relay wrote:
> From: Jia Wang <wangjia@ultrarisc.com>
> 
> Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> new file mode 100644
> index 000000000000..b50ff98dd878
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: UltraRISC DP1000 PCIe Host Controller
> +
> +description: |
> +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.

If so, you should probably refer snps,dw-pcie.yaml to avoid
some duplication.

Regards,
Yao Zi

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Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang]

On 2026-03-17 04:56 +0000, Yao Zi wrote:
> On Mon, Mar 16, 2026 at 03:06:59PM +0800, Jia Wang via B4 Relay wrote:
> > From: Jia Wang <wangjia@ultrarisc.com>
> > 
> > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
> >  1 file changed, 108 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> > new file mode 100644
> > index 000000000000..b50ff98dd878
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> > @@ -0,0 +1,108 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: UltraRISC DP1000 PCIe Host Controller
> > +
> > +description: |
> > +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
> 
> If so, you should probably refer snps,dw-pcie.yaml to avoid
> some duplication.

Thanks for the suggestion. I will reference snps,dw-pcie.yaml in v2.

> 
> Regards,
> Yao Zi
>
 
Regards,
Jia

Re: [PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang]

On 2026-03-17 04:56 +0000, Yao Zi wrote:
> On Mon, Mar 16, 2026 at 03:06:59PM +0800, Jia Wang via B4 Relay wrote:
> > From: Jia Wang <wangjia@ultrarisc.com>
> > 
> > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
> >  1 file changed, 108 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> > new file mode 100644
> > index 000000000000..b50ff98dd878
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> > @@ -0,0 +1,108 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: UltraRISC DP1000 PCIe Host Controller
> > +
> > +description: |
> > +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
> 
> If so, you should probably refer snps,dw-pcie.yaml to avoid
> some duplication.

Thanks for the suggestion. I will reference snps,dw-pcie.yaml in v2.

> 
> Regards,
> Yao Zi
>
 
Regards,
Jia



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http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Jia Wang]

From: Xincheng Zhang <zhangxincheng@ultrarisc.com>

Add DP1000 soc PCIe rc driver.

Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 drivers/pci/controller/dwc/Kconfig           |  15 ++
 drivers/pci/controller/dwc/Makefile          |   1 +
 drivers/pci/controller/dwc/pcie-designware.h |  22 +++
 drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
 4 files changed, 240 insertions(+)

diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index d0aa031397fa..0a33891bf7ef 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
 	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
 	  This driver supports TMPV7708 SoC.
 
+config PCIE_ULTRARISC
+	bool "UltraRISC PCIe host controller"
+	depends on ARCH_ULTRARISC || COMPILE_TEST
+	select PCIE_DW_HOST
+	select PCI_MSI
+	default y if ARCH_ULTRARISC
+	help
+	  Enables support for the PCIe controller in the UltraRISC SoC.
+	  This driver supports UR-DP1000 SoC. When selected, it automatically
+	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
+	  for MSI-based interrupt handling in the PCIe controller.
+	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
+	  requiring no further configuration on that platform.
+
+
 endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 67ba59c02038..884c46b78e01 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
 obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
 obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
 obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
+obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o
 
 # The following drivers are for devices that use the generic ACPI
 # pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ae6389dd9caa..8f2ed86cb5c5 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -69,6 +69,8 @@
 
 /* Synopsys-specific PCIe configuration registers */
 #define PCIE_PORT_FORCE			0x708
+/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
+#define PORT_LINK_NUM_MASK		GENMASK(7, 0)
 #define PORT_FORCE_DO_DESKEW_FOR_SRIS	BIT(23)
 
 #define PCIE_PORT_AFR			0x70C
@@ -96,6 +98,26 @@
 #define PCIE_PORT_LANE_SKEW		0x714
 #define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)
 
+/*
+ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number Register.
+ * This register holds the ack frequency, latency, replay, fast link scaling timers,
+ * and max function number values.
+ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.
+ *   0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us).
+ *     When the LTSSM is in Config or L12 Entry State, 1ms
+ *     timer is 2us, 2ms timer is 4us and 3ms timer is 6us.
+ *   0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)
+ *   0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
+ *   0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
+ */
+#define PCIE_TIMER_CTRL_MAX_FUNC_NUM    0x718
+#define PORT_FLT_SF_MASK    GENMASK(30, 29)
+#define PORT_FLT_SF(n)      FIELD_PREP(PORT_FLT_SF_MASK, n)
+#define PORT_FLT_SF_1024    PORT_FLT_SF(0x0)
+#define PORT_FLT_SF_256     PORT_FLT_SF(0x1)
+#define PORT_FLT_SF_64      PORT_FLT_SF(0x2)
+#define PORT_FLT_SF_16      PORT_FLT_SF(0x3)
+
 #define PCIE_PORT_DEBUG0		0x728
 #define PORT_LOGIC_LTSSM_STATE_MASK	0x3f
 #define PORT_LOGIC_LTSSM_STATE_L0	0x11
diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
new file mode 100644
index 000000000000..64cbf16d3ff7
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DWC PCIe RC driver for UltraRISC DP1000 SoC
+ *
+ * Copyright (C) 2023 UltraRISC
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/types.h>
+#include <linux/regmap.h>
+
+#include "pcie-designware.h"
+
+#define PCIE_CUS_CORE          0x400000
+
+#define LTSSM_ENABLE           BIT(7)
+#define FAST_LINK_MODE         BIT(12)
+#define HOLD_PHY_RST           BIT(14)
+#define L1SUB_DISABLE          BIT(15)
+
+struct ultrarisc_pcie {
+	struct dw_pcie  *pci;
+	u32 irq_mask[MAX_MSI_CTRLS];
+};
+
+static const struct of_device_id ultrarisc_pcie_of_match[];
+
+static struct pci_ops ultrarisc_pci_ops = {
+	.map_bus = dw_pcie_own_conf_map_bus,
+	.read = pci_generic_config_read32,
+	.write = pci_generic_config_write32,
+};
+
+static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
+{
+	struct pci_host_bridge *bridge = pp->bridge;
+
+	/* Set the bus ops */
+	bridge->ops = &ultrarisc_pci_ops;
+
+	return 0;
+}
+
+static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {
+	.init = ultrarisc_pcie_host_init,
+};
+
+static int ultrarisc_pcie_establish_link(struct dw_pcie *pci)
+{
+	u32 val;
+	u8 cap_exp;
+
+	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
+	val &= ~FAST_LINK_MODE;
+	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
+	val &= ~PORT_FLT_SF_MASK;
+	val |= PORT_FLT_SF_64;
+	dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
+
+	cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
+	val &= ~PCI_EXP_LNKCTL2_TLS;
+	val |= PCI_EXP_LNKCTL2_TLS_16_0GT;
+	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
+	val &= ~PORT_LINK_NUM_MASK;
+	dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
+
+	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
+	val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
+	val |= 0x6;
+	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
+	val &= ~(HOLD_PHY_RST | L1SUB_DISABLE);
+	val |= LTSSM_ENABLE;
+	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
+
+	return 0;
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+	.start_link = ultrarisc_pcie_establish_link,
+};
+
+static int ultrarisc_pcie_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ultrarisc_pcie *ultrarisc_pcie;
+	struct dw_pcie *pci;
+	struct dw_pcie_rp *pp;
+	int ret;
+
+	ultrarisc_pcie = devm_kzalloc(dev, sizeof(*ultrarisc_pcie), GFP_KERNEL);
+	if (!ultrarisc_pcie)
+		return -ENOMEM;
+
+	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+	if (!pci)
+		return -ENOMEM;
+
+	pci->dev = dev;
+	pci->ops = &dw_pcie_ops;
+
+	/* Set a default value suitable for at most 16 in and 16 out windows */
+	pci->atu_size = SZ_8K;
+
+	ultrarisc_pcie->pci = pci;
+
+	pp = &pci->pp;
+
+	platform_set_drvdata(pdev, ultrarisc_pcie);
+
+	pp->irq = platform_get_irq(pdev, 1);
+	if (pp->irq < 0)
+		return pp->irq;
+
+	pp->num_vectors = MAX_MSI_IRQS;
+	pp->ops = &ultrarisc_pcie_host_ops;
+
+	ret = dw_pcie_host_init(pp);
+	if (ret) {
+		dev_err(dev, "Failed to initialize host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int ultrarisc_pcie_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
+	struct dw_pcie *pci = ultrarisc_pcie->pci;
+	struct dw_pcie_rp *pp = &pci->pp;
+	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+	unsigned long flags;
+	int ctrl;
+
+	raw_spin_lock_irqsave(&pp->lock, flags);
+
+	for (ctrl = 0; ctrl < num_ctrls; ctrl++)
+		ultrarisc_pcie->irq_mask[ctrl] = pp->irq_mask[ctrl];
+
+	raw_spin_unlock_irqrestore(&pp->lock, flags);
+
+	return 0;
+}
+
+static int ultrarisc_pcie_resume(struct platform_device *pdev)
+{
+	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
+	struct dw_pcie *pci = ultrarisc_pcie->pci;
+	struct dw_pcie_rp *pp = &pci->pp;
+	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+	unsigned long flags;
+	int ctrl;
+
+	raw_spin_lock_irqsave(&pp->lock, flags);
+
+	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
+		pp->irq_mask[ctrl] = ultrarisc_pcie->irq_mask[ctrl];
+		dw_pcie_writel_dbi(pci,
+				   PCIE_MSI_INTR0_MASK +
+				   ctrl * MSI_REG_CTRL_BLOCK_SIZE,
+				   pp->irq_mask[ctrl]);
+	}
+
+	raw_spin_unlock_irqrestore(&pp->lock, flags);
+
+	return 0;
+}
+
+static const struct of_device_id ultrarisc_pcie_of_match[] = {
+	{
+		.compatible = "ultrarisc,dp1000-pcie",
+	},
+	{},
+};
+
+static struct platform_driver ultrarisc_pcie_driver = {
+	.driver = {
+		.name	= "ultrarisc-pcie",
+		.of_match_table = ultrarisc_pcie_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = ultrarisc_pcie_probe,
+	.suspend = ultrarisc_pcie_suspend,
+	.resume = ultrarisc_pcie_resume,
+};
+builtin_platform_driver(ultrarisc_pcie_driver);

-- 
2.34.1

[PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Jia Wang via B4 Relay]

From: Xincheng Zhang <zhangxincheng@ultrarisc.com>

Add DP1000 soc PCIe rc driver.

Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 drivers/pci/controller/dwc/Kconfig           |  15 ++
 drivers/pci/controller/dwc/Makefile          |   1 +
 drivers/pci/controller/dwc/pcie-designware.h |  22 +++
 drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
 4 files changed, 240 insertions(+)

diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index d0aa031397fa..0a33891bf7ef 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
 	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
 	  This driver supports TMPV7708 SoC.
 
+config PCIE_ULTRARISC
+	bool "UltraRISC PCIe host controller"
+	depends on ARCH_ULTRARISC || COMPILE_TEST
+	select PCIE_DW_HOST
+	select PCI_MSI
+	default y if ARCH_ULTRARISC
+	help
+	  Enables support for the PCIe controller in the UltraRISC SoC.
+	  This driver supports UR-DP1000 SoC. When selected, it automatically
+	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
+	  for MSI-based interrupt handling in the PCIe controller.
+	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
+	  requiring no further configuration on that platform.
+
+
 endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 67ba59c02038..884c46b78e01 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
 obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
 obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
 obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
+obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o
 
 # The following drivers are for devices that use the generic ACPI
 # pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ae6389dd9caa..8f2ed86cb5c5 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -69,6 +69,8 @@
 
 /* Synopsys-specific PCIe configuration registers */
 #define PCIE_PORT_FORCE			0x708
+/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
+#define PORT_LINK_NUM_MASK		GENMASK(7, 0)
 #define PORT_FORCE_DO_DESKEW_FOR_SRIS	BIT(23)
 
 #define PCIE_PORT_AFR			0x70C
@@ -96,6 +98,26 @@
 #define PCIE_PORT_LANE_SKEW		0x714
 #define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)
 
+/*
+ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number Register.
+ * This register holds the ack frequency, latency, replay, fast link scaling timers,
+ * and max function number values.
+ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.
+ *   0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us).
+ *     When the LTSSM is in Config or L12 Entry State, 1ms
+ *     timer is 2us, 2ms timer is 4us and 3ms timer is 6us.
+ *   0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)
+ *   0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
+ *   0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
+ */
+#define PCIE_TIMER_CTRL_MAX_FUNC_NUM    0x718
+#define PORT_FLT_SF_MASK    GENMASK(30, 29)
+#define PORT_FLT_SF(n)      FIELD_PREP(PORT_FLT_SF_MASK, n)
+#define PORT_FLT_SF_1024    PORT_FLT_SF(0x0)
+#define PORT_FLT_SF_256     PORT_FLT_SF(0x1)
+#define PORT_FLT_SF_64      PORT_FLT_SF(0x2)
+#define PORT_FLT_SF_16      PORT_FLT_SF(0x3)
+
 #define PCIE_PORT_DEBUG0		0x728
 #define PORT_LOGIC_LTSSM_STATE_MASK	0x3f
 #define PORT_LOGIC_LTSSM_STATE_L0	0x11
diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
new file mode 100644
index 000000000000..64cbf16d3ff7
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DWC PCIe RC driver for UltraRISC DP1000 SoC
+ *
+ * Copyright (C) 2023 UltraRISC
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/types.h>
+#include <linux/regmap.h>
+
+#include "pcie-designware.h"
+
+#define PCIE_CUS_CORE          0x400000
+
+#define LTSSM_ENABLE           BIT(7)
+#define FAST_LINK_MODE         BIT(12)
+#define HOLD_PHY_RST           BIT(14)
+#define L1SUB_DISABLE          BIT(15)
+
+struct ultrarisc_pcie {
+	struct dw_pcie  *pci;
+	u32 irq_mask[MAX_MSI_CTRLS];
+};
+
+static const struct of_device_id ultrarisc_pcie_of_match[];
+
+static struct pci_ops ultrarisc_pci_ops = {
+	.map_bus = dw_pcie_own_conf_map_bus,
+	.read = pci_generic_config_read32,
+	.write = pci_generic_config_write32,
+};
+
+static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
+{
+	struct pci_host_bridge *bridge = pp->bridge;
+
+	/* Set the bus ops */
+	bridge->ops = &ultrarisc_pci_ops;
+
+	return 0;
+}
+
+static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {
+	.init = ultrarisc_pcie_host_init,
+};
+
+static int ultrarisc_pcie_establish_link(struct dw_pcie *pci)
+{
+	u32 val;
+	u8 cap_exp;
+
+	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
+	val &= ~FAST_LINK_MODE;
+	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
+	val &= ~PORT_FLT_SF_MASK;
+	val |= PORT_FLT_SF_64;
+	dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
+
+	cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
+	val &= ~PCI_EXP_LNKCTL2_TLS;
+	val |= PCI_EXP_LNKCTL2_TLS_16_0GT;
+	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
+	val &= ~PORT_LINK_NUM_MASK;
+	dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
+
+	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
+	val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
+	val |= 0x6;
+	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
+	val &= ~(HOLD_PHY_RST | L1SUB_DISABLE);
+	val |= LTSSM_ENABLE;
+	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
+
+	return 0;
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+	.start_link = ultrarisc_pcie_establish_link,
+};
+
+static int ultrarisc_pcie_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ultrarisc_pcie *ultrarisc_pcie;
+	struct dw_pcie *pci;
+	struct dw_pcie_rp *pp;
+	int ret;
+
+	ultrarisc_pcie = devm_kzalloc(dev, sizeof(*ultrarisc_pcie), GFP_KERNEL);
+	if (!ultrarisc_pcie)
+		return -ENOMEM;
+
+	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+	if (!pci)
+		return -ENOMEM;
+
+	pci->dev = dev;
+	pci->ops = &dw_pcie_ops;
+
+	/* Set a default value suitable for at most 16 in and 16 out windows */
+	pci->atu_size = SZ_8K;
+
+	ultrarisc_pcie->pci = pci;
+
+	pp = &pci->pp;
+
+	platform_set_drvdata(pdev, ultrarisc_pcie);
+
+	pp->irq = platform_get_irq(pdev, 1);
+	if (pp->irq < 0)
+		return pp->irq;
+
+	pp->num_vectors = MAX_MSI_IRQS;
+	pp->ops = &ultrarisc_pcie_host_ops;
+
+	ret = dw_pcie_host_init(pp);
+	if (ret) {
+		dev_err(dev, "Failed to initialize host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int ultrarisc_pcie_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
+	struct dw_pcie *pci = ultrarisc_pcie->pci;
+	struct dw_pcie_rp *pp = &pci->pp;
+	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+	unsigned long flags;
+	int ctrl;
+
+	raw_spin_lock_irqsave(&pp->lock, flags);
+
+	for (ctrl = 0; ctrl < num_ctrls; ctrl++)
+		ultrarisc_pcie->irq_mask[ctrl] = pp->irq_mask[ctrl];
+
+	raw_spin_unlock_irqrestore(&pp->lock, flags);
+
+	return 0;
+}
+
+static int ultrarisc_pcie_resume(struct platform_device *pdev)
+{
+	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
+	struct dw_pcie *pci = ultrarisc_pcie->pci;
+	struct dw_pcie_rp *pp = &pci->pp;
+	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+	unsigned long flags;
+	int ctrl;
+
+	raw_spin_lock_irqsave(&pp->lock, flags);
+
+	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
+		pp->irq_mask[ctrl] = ultrarisc_pcie->irq_mask[ctrl];
+		dw_pcie_writel_dbi(pci,
+				   PCIE_MSI_INTR0_MASK +
+				   ctrl * MSI_REG_CTRL_BLOCK_SIZE,
+				   pp->irq_mask[ctrl]);
+	}
+
+	raw_spin_unlock_irqrestore(&pp->lock, flags);
+
+	return 0;
+}
+
+static const struct of_device_id ultrarisc_pcie_of_match[] = {
+	{
+		.compatible = "ultrarisc,dp1000-pcie",
+	},
+	{},
+};
+
+static struct platform_driver ultrarisc_pcie_driver = {
+	.driver = {
+		.name	= "ultrarisc-pcie",
+		.of_match_table = ultrarisc_pcie_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = ultrarisc_pcie_probe,
+	.suspend = ultrarisc_pcie_suspend,
+	.resume = ultrarisc_pcie_resume,
+};
+builtin_platform_driver(ultrarisc_pcie_driver);

-- 
2.34.1



_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Jia Wang via B4 Relay]

From: Xincheng Zhang <zhangxincheng@ultrarisc.com>

Add DP1000 soc PCIe rc driver.

Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 drivers/pci/controller/dwc/Kconfig           |  15 ++
 drivers/pci/controller/dwc/Makefile          |   1 +
 drivers/pci/controller/dwc/pcie-designware.h |  22 +++
 drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
 4 files changed, 240 insertions(+)

diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index d0aa031397fa..0a33891bf7ef 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
 	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
 	  This driver supports TMPV7708 SoC.
 
+config PCIE_ULTRARISC
+	bool "UltraRISC PCIe host controller"
+	depends on ARCH_ULTRARISC || COMPILE_TEST
+	select PCIE_DW_HOST
+	select PCI_MSI
+	default y if ARCH_ULTRARISC
+	help
+	  Enables support for the PCIe controller in the UltraRISC SoC.
+	  This driver supports UR-DP1000 SoC. When selected, it automatically
+	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
+	  for MSI-based interrupt handling in the PCIe controller.
+	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
+	  requiring no further configuration on that platform.
+
+
 endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 67ba59c02038..884c46b78e01 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
 obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
 obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
 obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
+obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o
 
 # The following drivers are for devices that use the generic ACPI
 # pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ae6389dd9caa..8f2ed86cb5c5 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -69,6 +69,8 @@
 
 /* Synopsys-specific PCIe configuration registers */
 #define PCIE_PORT_FORCE			0x708
+/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
+#define PORT_LINK_NUM_MASK		GENMASK(7, 0)
 #define PORT_FORCE_DO_DESKEW_FOR_SRIS	BIT(23)
 
 #define PCIE_PORT_AFR			0x70C
@@ -96,6 +98,26 @@
 #define PCIE_PORT_LANE_SKEW		0x714
 #define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)
 
+/*
+ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number Register.
+ * This register holds the ack frequency, latency, replay, fast link scaling timers,
+ * and max function number values.
+ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.
+ *   0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us).
+ *     When the LTSSM is in Config or L12 Entry State, 1ms
+ *     timer is 2us, 2ms timer is 4us and 3ms timer is 6us.
+ *   0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)
+ *   0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
+ *   0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
+ */
+#define PCIE_TIMER_CTRL_MAX_FUNC_NUM    0x718
+#define PORT_FLT_SF_MASK    GENMASK(30, 29)
+#define PORT_FLT_SF(n)      FIELD_PREP(PORT_FLT_SF_MASK, n)
+#define PORT_FLT_SF_1024    PORT_FLT_SF(0x0)
+#define PORT_FLT_SF_256     PORT_FLT_SF(0x1)
+#define PORT_FLT_SF_64      PORT_FLT_SF(0x2)
+#define PORT_FLT_SF_16      PORT_FLT_SF(0x3)
+
 #define PCIE_PORT_DEBUG0		0x728
 #define PORT_LOGIC_LTSSM_STATE_MASK	0x3f
 #define PORT_LOGIC_LTSSM_STATE_L0	0x11
diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
new file mode 100644
index 000000000000..64cbf16d3ff7
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DWC PCIe RC driver for UltraRISC DP1000 SoC
+ *
+ * Copyright (C) 2023 UltraRISC
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/types.h>
+#include <linux/regmap.h>
+
+#include "pcie-designware.h"
+
+#define PCIE_CUS_CORE          0x400000
+
+#define LTSSM_ENABLE           BIT(7)
+#define FAST_LINK_MODE         BIT(12)
+#define HOLD_PHY_RST           BIT(14)
+#define L1SUB_DISABLE          BIT(15)
+
+struct ultrarisc_pcie {
+	struct dw_pcie  *pci;
+	u32 irq_mask[MAX_MSI_CTRLS];
+};
+
+static const struct of_device_id ultrarisc_pcie_of_match[];
+
+static struct pci_ops ultrarisc_pci_ops = {
+	.map_bus = dw_pcie_own_conf_map_bus,
+	.read = pci_generic_config_read32,
+	.write = pci_generic_config_write32,
+};
+
+static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
+{
+	struct pci_host_bridge *bridge = pp->bridge;
+
+	/* Set the bus ops */
+	bridge->ops = &ultrarisc_pci_ops;
+
+	return 0;
+}
+
+static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {
+	.init = ultrarisc_pcie_host_init,
+};
+
+static int ultrarisc_pcie_establish_link(struct dw_pcie *pci)
+{
+	u32 val;
+	u8 cap_exp;
+
+	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
+	val &= ~FAST_LINK_MODE;
+	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
+	val &= ~PORT_FLT_SF_MASK;
+	val |= PORT_FLT_SF_64;
+	dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
+
+	cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
+	val &= ~PCI_EXP_LNKCTL2_TLS;
+	val |= PCI_EXP_LNKCTL2_TLS_16_0GT;
+	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
+	val &= ~PORT_LINK_NUM_MASK;
+	dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
+
+	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
+	val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
+	val |= 0x6;
+	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
+	val &= ~(HOLD_PHY_RST | L1SUB_DISABLE);
+	val |= LTSSM_ENABLE;
+	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
+
+	return 0;
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+	.start_link = ultrarisc_pcie_establish_link,
+};
+
+static int ultrarisc_pcie_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ultrarisc_pcie *ultrarisc_pcie;
+	struct dw_pcie *pci;
+	struct dw_pcie_rp *pp;
+	int ret;
+
+	ultrarisc_pcie = devm_kzalloc(dev, sizeof(*ultrarisc_pcie), GFP_KERNEL);
+	if (!ultrarisc_pcie)
+		return -ENOMEM;
+
+	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+	if (!pci)
+		return -ENOMEM;
+
+	pci->dev = dev;
+	pci->ops = &dw_pcie_ops;
+
+	/* Set a default value suitable for at most 16 in and 16 out windows */
+	pci->atu_size = SZ_8K;
+
+	ultrarisc_pcie->pci = pci;
+
+	pp = &pci->pp;
+
+	platform_set_drvdata(pdev, ultrarisc_pcie);
+
+	pp->irq = platform_get_irq(pdev, 1);
+	if (pp->irq < 0)
+		return pp->irq;
+
+	pp->num_vectors = MAX_MSI_IRQS;
+	pp->ops = &ultrarisc_pcie_host_ops;
+
+	ret = dw_pcie_host_init(pp);
+	if (ret) {
+		dev_err(dev, "Failed to initialize host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int ultrarisc_pcie_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
+	struct dw_pcie *pci = ultrarisc_pcie->pci;
+	struct dw_pcie_rp *pp = &pci->pp;
+	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+	unsigned long flags;
+	int ctrl;
+
+	raw_spin_lock_irqsave(&pp->lock, flags);
+
+	for (ctrl = 0; ctrl < num_ctrls; ctrl++)
+		ultrarisc_pcie->irq_mask[ctrl] = pp->irq_mask[ctrl];
+
+	raw_spin_unlock_irqrestore(&pp->lock, flags);
+
+	return 0;
+}
+
+static int ultrarisc_pcie_resume(struct platform_device *pdev)
+{
+	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
+	struct dw_pcie *pci = ultrarisc_pcie->pci;
+	struct dw_pcie_rp *pp = &pci->pp;
+	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+	unsigned long flags;
+	int ctrl;
+
+	raw_spin_lock_irqsave(&pp->lock, flags);
+
+	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
+		pp->irq_mask[ctrl] = ultrarisc_pcie->irq_mask[ctrl];
+		dw_pcie_writel_dbi(pci,
+				   PCIE_MSI_INTR0_MASK +
+				   ctrl * MSI_REG_CTRL_BLOCK_SIZE,
+				   pp->irq_mask[ctrl]);
+	}
+
+	raw_spin_unlock_irqrestore(&pp->lock, flags);
+
+	return 0;
+}
+
+static const struct of_device_id ultrarisc_pcie_of_match[] = {
+	{
+		.compatible = "ultrarisc,dp1000-pcie",
+	},
+	{},
+};
+
+static struct platform_driver ultrarisc_pcie_driver = {
+	.driver = {
+		.name	= "ultrarisc-pcie",
+		.of_match_table = ultrarisc_pcie_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = ultrarisc_pcie_probe,
+	.suspend = ultrarisc_pcie_suspend,
+	.resume = ultrarisc_pcie_resume,
+};
+builtin_platform_driver(ultrarisc_pcie_driver);

-- 
2.34.1

Re: [PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Bjorn Helgaas]

In subject, s/dwc/ultrarisc/ or whatever tag we're going to use for
this driver, e.g.,

  PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver

On Mon, Mar 16, 2026 at 03:07:00PM +0800, Jia Wang via B4 Relay wrote:
> From: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> 
> Add DP1000 soc PCIe rc driver.

s/soc/SoC/
s/rc/RC/ or Root Complex (also in subject)

> Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  drivers/pci/controller/dwc/Kconfig           |  15 ++
>  drivers/pci/controller/dwc/Makefile          |   1 +
>  drivers/pci/controller/dwc/pcie-designware.h |  22 +++
>  drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
>  4 files changed, 240 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index d0aa031397fa..0a33891bf7ef 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
>  	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
>  	  This driver supports TMPV7708 SoC.
>  
> +config PCIE_ULTRARISC
> +	bool "UltraRISC PCIe host controller"
> +	depends on ARCH_ULTRARISC || COMPILE_TEST
> +	select PCIE_DW_HOST
> +	select PCI_MSI
> +	default y if ARCH_ULTRARISC
> +	help
> +	  Enables support for the PCIe controller in the UltraRISC SoC.
> +	  This driver supports UR-DP1000 SoC. When selected, it automatically
> +	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
> +	  for MSI-based interrupt handling in the PCIe controller.

I don't think the PCIE_DW_HOST and PCI_MSI explanation is relevant for
Kconfig help.

> +	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
> +	  requiring no further configuration on that platform.
> +
> +

Remove spurious blank line.

>  endmenu
> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> index 67ba59c02038..884c46b78e01 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
>  obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
>  obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
>  obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
> +obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o
>  
>  # The following drivers are for devices that use the generic ACPI
>  # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index ae6389dd9caa..8f2ed86cb5c5 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -69,6 +69,8 @@
>  
>  /* Synopsys-specific PCIe configuration registers */
>  #define PCIE_PORT_FORCE			0x708
> +/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
> +#define PORT_LINK_NUM_MASK		GENMASK(7, 0)
>  #define PORT_FORCE_DO_DESKEW_FOR_SRIS	BIT(23)
>  
>  #define PCIE_PORT_AFR			0x70C
> @@ -96,6 +98,26 @@
>  #define PCIE_PORT_LANE_SKEW		0x714
>  #define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)
>  
> +/*
> + * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number Register.
> + * This register holds the ack frequency, latency, replay, fast link scaling timers,
> + * and max function number values.

Wrap to fit in 80 columns like the rest of the file.

> + * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.
> + *   0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us).
> + *     When the LTSSM is in Config or L12 Entry State, 1ms
> + *     timer is 2us, 2ms timer is 4us and 3ms timer is 6us.
> + *   0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)
> + *   0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
> + *   0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
> + */
> +#define PCIE_TIMER_CTRL_MAX_FUNC_NUM    0x718
> +#define PORT_FLT_SF_MASK    GENMASK(30, 29)
> +#define PORT_FLT_SF(n)      FIELD_PREP(PORT_FLT_SF_MASK, n)
> +#define PORT_FLT_SF_1024    PORT_FLT_SF(0x0)
> +#define PORT_FLT_SF_256     PORT_FLT_SF(0x1)
> +#define PORT_FLT_SF_64      PORT_FLT_SF(0x2)
> +#define PORT_FLT_SF_16      PORT_FLT_SF(0x3)
> +
>  #define PCIE_PORT_DEBUG0		0x728
>  #define PORT_LOGIC_LTSSM_STATE_MASK	0x3f
>  #define PORT_LOGIC_LTSSM_STATE_L0	0x11
> diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
> new file mode 100644
> index 000000000000..64cbf16d3ff7
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
> @@ -0,0 +1,202 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * DWC PCIe RC driver for UltraRISC DP1000 SoC
> + *
> + * Copyright (C) 2023 UltraRISC
> + *

Remove spurious blank line.  Maybe you want "(C) 2026"?

> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/of_device.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/resource.h>
> +#include <linux/types.h>
> +#include <linux/regmap.h>

Order alphabetically.

> +#include "pcie-designware.h"
> +
> +#define PCIE_CUS_CORE          0x400000
> +
> +#define LTSSM_ENABLE           BIT(7)
> +#define FAST_LINK_MODE         BIT(12)
> +#define HOLD_PHY_RST           BIT(14)
> +#define L1SUB_DISABLE          BIT(15)
> +
> +struct ultrarisc_pcie {
> +	struct dw_pcie  *pci;

s/dw_pcie  /dw_pcie / (single space to match irq_mask below)

> +	u32 irq_mask[MAX_MSI_CTRLS];
> +};
> +
> +static const struct of_device_id ultrarisc_pcie_of_match[];

This declaration looks unnecessary.

> +static struct pci_ops ultrarisc_pci_ops = {
> +	.map_bus = dw_pcie_own_conf_map_bus,
> +	.read = pci_generic_config_read32,
> +	.write = pci_generic_config_write32,

I guess this hardware has the defect that it can only do 32-bit
writes?

> +};
> +
> +static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
> +{
> +	struct pci_host_bridge *bridge = pp->bridge;
> +
> +	/* Set the bus ops */

Drop spurious comment.

> +	bridge->ops = &ultrarisc_pci_ops;
> +
> +	return 0;
> +}
> +
> +static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {
> +	.init = ultrarisc_pcie_host_init,
> +};
> +
> +static int ultrarisc_pcie_establish_link(struct dw_pcie *pci)
> +{
> +	u32 val;
> +	u8 cap_exp;
> +
> +	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
> +	val &= ~FAST_LINK_MODE;
> +	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
> +
> +	val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
> +	val &= ~PORT_FLT_SF_MASK;
> +	val |= PORT_FLT_SF_64;

FIELD_MODIFY() here and below.

> +	dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
> +
> +	cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
> +	val &= ~PCI_EXP_LNKCTL2_TLS;
> +	val |= PCI_EXP_LNKCTL2_TLS_16_0GT;
> +	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
> +
> +	val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
> +	val &= ~PORT_LINK_NUM_MASK;
> +	dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
> +
> +	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
> +	val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
> +	val |= 0x6;
> +	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);
> +
> +	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
> +	val &= ~(HOLD_PHY_RST | L1SUB_DISABLE);
> +	val |= LTSSM_ENABLE;
> +	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
> +
> +	return 0;
> +}
> +
> +static const struct dw_pcie_ops dw_pcie_ops = {
> +	.start_link = ultrarisc_pcie_establish_link,

s/ultrarisc_pcie_establish_link/ultrarisc_pcie_start_link/
to match member name and other drivers.

> +};
> +
> +static int ultrarisc_pcie_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct ultrarisc_pcie *ultrarisc_pcie;

"ultrarisc_pcie" is a pretty long name that will be used for
parameters when you add more functionality.  Several drivers just use
"pcie", some use the equivalent of "ultrarisc", etc.

> +	struct dw_pcie *pci;
> +	struct dw_pcie_rp *pp;
> +	int ret;
> +
> +	ultrarisc_pcie = devm_kzalloc(dev, sizeof(*ultrarisc_pcie), GFP_KERNEL);
> +	if (!ultrarisc_pcie)
> +		return -ENOMEM;
> +
> +	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> +	if (!pci)
> +		return -ENOMEM;
> +
> +	pci->dev = dev;
> +	pci->ops = &dw_pcie_ops;
> +
> +	/* Set a default value suitable for at most 16 in and 16 out windows */
> +	pci->atu_size = SZ_8K;
> +
> +	ultrarisc_pcie->pci = pci;
> +
> +	pp = &pci->pp;
> +
> +	platform_set_drvdata(pdev, ultrarisc_pcie);
> +
> +	pp->irq = platform_get_irq(pdev, 1);
> +	if (pp->irq < 0)
> +		return pp->irq;
> +
> +	pp->num_vectors = MAX_MSI_IRQS;
> +	pp->ops = &ultrarisc_pcie_host_ops;
> +
> +	ret = dw_pcie_host_init(pp);
> +	if (ret) {
> +		dev_err(dev, "Failed to initialize host\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int ultrarisc_pcie_suspend(struct platform_device *pdev, pm_message_t state)

If you use generic power management, this will be:

  static int ultrarisc_pcie_suspend(struct device *dev)

> +{
> +	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
> +	struct dw_pcie *pci = ultrarisc_pcie->pci;
> +	struct dw_pcie_rp *pp = &pci->pp;
> +	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> +	unsigned long flags;
> +	int ctrl;
> +
> +	raw_spin_lock_irqsave(&pp->lock, flags);
> +
> +	for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> +		ultrarisc_pcie->irq_mask[ctrl] = pp->irq_mask[ctrl];
> +
> +	raw_spin_unlock_irqrestore(&pp->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int ultrarisc_pcie_resume(struct platform_device *pdev)
> +{
> +	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
> +	struct dw_pcie *pci = ultrarisc_pcie->pci;
> +	struct dw_pcie_rp *pp = &pci->pp;
> +	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> +	unsigned long flags;
> +	int ctrl;
> +
> +	raw_spin_lock_irqsave(&pp->lock, flags);
> +
> +	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
> +		pp->irq_mask[ctrl] = ultrarisc_pcie->irq_mask[ctrl];
> +		dw_pcie_writel_dbi(pci,
> +				   PCIE_MSI_INTR0_MASK +
> +				   ctrl * MSI_REG_CTRL_BLOCK_SIZE,
> +				   pp->irq_mask[ctrl]);
> +	}
> +
> +	raw_spin_unlock_irqrestore(&pp->lock, flags);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id ultrarisc_pcie_of_match[] = {
> +	{
> +		.compatible = "ultrarisc,dp1000-pcie",
> +	},
> +	{},
> +};
> +
> +static struct platform_driver ultrarisc_pcie_driver = {
> +	.driver = {
> +		.name	= "ultrarisc-pcie",
> +		.of_match_table = ultrarisc_pcie_of_match,
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe = ultrarisc_pcie_probe,
> +	.suspend = ultrarisc_pcie_suspend,
> +	.resume = ultrarisc_pcie_resume,

Use generic driver PM instead of the platform_driver.suspend/resume.

> +};
> +builtin_platform_driver(ultrarisc_pcie_driver);
> 
> -- 
> 2.34.1
> 
> 

Re: [PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Bjorn Helgaas]

In subject, s/dwc/ultrarisc/ or whatever tag we're going to use for
this driver, e.g.,

  PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver

On Mon, Mar 16, 2026 at 03:07:00PM +0800, Jia Wang via B4 Relay wrote:
> From: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> 
> Add DP1000 soc PCIe rc driver.

s/soc/SoC/
s/rc/RC/ or Root Complex (also in subject)

> Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  drivers/pci/controller/dwc/Kconfig           |  15 ++
>  drivers/pci/controller/dwc/Makefile          |   1 +
>  drivers/pci/controller/dwc/pcie-designware.h |  22 +++
>  drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
>  4 files changed, 240 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index d0aa031397fa..0a33891bf7ef 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
>  	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
>  	  This driver supports TMPV7708 SoC.
>  
> +config PCIE_ULTRARISC
> +	bool "UltraRISC PCIe host controller"
> +	depends on ARCH_ULTRARISC || COMPILE_TEST
> +	select PCIE_DW_HOST
> +	select PCI_MSI
> +	default y if ARCH_ULTRARISC
> +	help
> +	  Enables support for the PCIe controller in the UltraRISC SoC.
> +	  This driver supports UR-DP1000 SoC. When selected, it automatically
> +	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
> +	  for MSI-based interrupt handling in the PCIe controller.

I don't think the PCIE_DW_HOST and PCI_MSI explanation is relevant for
Kconfig help.

> +	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
> +	  requiring no further configuration on that platform.
> +
> +

Remove spurious blank line.

>  endmenu
> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> index 67ba59c02038..884c46b78e01 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
>  obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
>  obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
>  obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
> +obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o
>  
>  # The following drivers are for devices that use the generic ACPI
>  # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index ae6389dd9caa..8f2ed86cb5c5 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -69,6 +69,8 @@
>  
>  /* Synopsys-specific PCIe configuration registers */
>  #define PCIE_PORT_FORCE			0x708
> +/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
> +#define PORT_LINK_NUM_MASK		GENMASK(7, 0)
>  #define PORT_FORCE_DO_DESKEW_FOR_SRIS	BIT(23)
>  
>  #define PCIE_PORT_AFR			0x70C
> @@ -96,6 +98,26 @@
>  #define PCIE_PORT_LANE_SKEW		0x714
>  #define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)
>  
> +/*
> + * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number Register.
> + * This register holds the ack frequency, latency, replay, fast link scaling timers,
> + * and max function number values.

Wrap to fit in 80 columns like the rest of the file.

> + * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.
> + *   0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us).
> + *     When the LTSSM is in Config or L12 Entry State, 1ms
> + *     timer is 2us, 2ms timer is 4us and 3ms timer is 6us.
> + *   0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)
> + *   0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
> + *   0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
> + */
> +#define PCIE_TIMER_CTRL_MAX_FUNC_NUM    0x718
> +#define PORT_FLT_SF_MASK    GENMASK(30, 29)
> +#define PORT_FLT_SF(n)      FIELD_PREP(PORT_FLT_SF_MASK, n)
> +#define PORT_FLT_SF_1024    PORT_FLT_SF(0x0)
> +#define PORT_FLT_SF_256     PORT_FLT_SF(0x1)
> +#define PORT_FLT_SF_64      PORT_FLT_SF(0x2)
> +#define PORT_FLT_SF_16      PORT_FLT_SF(0x3)
> +
>  #define PCIE_PORT_DEBUG0		0x728
>  #define PORT_LOGIC_LTSSM_STATE_MASK	0x3f
>  #define PORT_LOGIC_LTSSM_STATE_L0	0x11
> diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
> new file mode 100644
> index 000000000000..64cbf16d3ff7
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
> @@ -0,0 +1,202 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * DWC PCIe RC driver for UltraRISC DP1000 SoC
> + *
> + * Copyright (C) 2023 UltraRISC
> + *

Remove spurious blank line.  Maybe you want "(C) 2026"?

> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/of_device.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/resource.h>
> +#include <linux/types.h>
> +#include <linux/regmap.h>

Order alphabetically.

> +#include "pcie-designware.h"
> +
> +#define PCIE_CUS_CORE          0x400000
> +
> +#define LTSSM_ENABLE           BIT(7)
> +#define FAST_LINK_MODE         BIT(12)
> +#define HOLD_PHY_RST           BIT(14)
> +#define L1SUB_DISABLE          BIT(15)
> +
> +struct ultrarisc_pcie {
> +	struct dw_pcie  *pci;

s/dw_pcie  /dw_pcie / (single space to match irq_mask below)

> +	u32 irq_mask[MAX_MSI_CTRLS];
> +};
> +
> +static const struct of_device_id ultrarisc_pcie_of_match[];

This declaration looks unnecessary.

> +static struct pci_ops ultrarisc_pci_ops = {
> +	.map_bus = dw_pcie_own_conf_map_bus,
> +	.read = pci_generic_config_read32,
> +	.write = pci_generic_config_write32,

I guess this hardware has the defect that it can only do 32-bit
writes?

> +};
> +
> +static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
> +{
> +	struct pci_host_bridge *bridge = pp->bridge;
> +
> +	/* Set the bus ops */

Drop spurious comment.

> +	bridge->ops = &ultrarisc_pci_ops;
> +
> +	return 0;
> +}
> +
> +static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {
> +	.init = ultrarisc_pcie_host_init,
> +};
> +
> +static int ultrarisc_pcie_establish_link(struct dw_pcie *pci)
> +{
> +	u32 val;
> +	u8 cap_exp;
> +
> +	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
> +	val &= ~FAST_LINK_MODE;
> +	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
> +
> +	val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
> +	val &= ~PORT_FLT_SF_MASK;
> +	val |= PORT_FLT_SF_64;

FIELD_MODIFY() here and below.

> +	dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
> +
> +	cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
> +	val &= ~PCI_EXP_LNKCTL2_TLS;
> +	val |= PCI_EXP_LNKCTL2_TLS_16_0GT;
> +	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
> +
> +	val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
> +	val &= ~PORT_LINK_NUM_MASK;
> +	dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
> +
> +	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
> +	val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
> +	val |= 0x6;
> +	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);
> +
> +	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
> +	val &= ~(HOLD_PHY_RST | L1SUB_DISABLE);
> +	val |= LTSSM_ENABLE;
> +	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
> +
> +	return 0;
> +}
> +
> +static const struct dw_pcie_ops dw_pcie_ops = {
> +	.start_link = ultrarisc_pcie_establish_link,

s/ultrarisc_pcie_establish_link/ultrarisc_pcie_start_link/
to match member name and other drivers.

> +};
> +
> +static int ultrarisc_pcie_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct ultrarisc_pcie *ultrarisc_pcie;

"ultrarisc_pcie" is a pretty long name that will be used for
parameters when you add more functionality.  Several drivers just use
"pcie", some use the equivalent of "ultrarisc", etc.

> +	struct dw_pcie *pci;
> +	struct dw_pcie_rp *pp;
> +	int ret;
> +
> +	ultrarisc_pcie = devm_kzalloc(dev, sizeof(*ultrarisc_pcie), GFP_KERNEL);
> +	if (!ultrarisc_pcie)
> +		return -ENOMEM;
> +
> +	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> +	if (!pci)
> +		return -ENOMEM;
> +
> +	pci->dev = dev;
> +	pci->ops = &dw_pcie_ops;
> +
> +	/* Set a default value suitable for at most 16 in and 16 out windows */
> +	pci->atu_size = SZ_8K;
> +
> +	ultrarisc_pcie->pci = pci;
> +
> +	pp = &pci->pp;
> +
> +	platform_set_drvdata(pdev, ultrarisc_pcie);
> +
> +	pp->irq = platform_get_irq(pdev, 1);
> +	if (pp->irq < 0)
> +		return pp->irq;
> +
> +	pp->num_vectors = MAX_MSI_IRQS;
> +	pp->ops = &ultrarisc_pcie_host_ops;
> +
> +	ret = dw_pcie_host_init(pp);
> +	if (ret) {
> +		dev_err(dev, "Failed to initialize host\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int ultrarisc_pcie_suspend(struct platform_device *pdev, pm_message_t state)

If you use generic power management, this will be:

  static int ultrarisc_pcie_suspend(struct device *dev)

> +{
> +	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
> +	struct dw_pcie *pci = ultrarisc_pcie->pci;
> +	struct dw_pcie_rp *pp = &pci->pp;
> +	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> +	unsigned long flags;
> +	int ctrl;
> +
> +	raw_spin_lock_irqsave(&pp->lock, flags);
> +
> +	for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> +		ultrarisc_pcie->irq_mask[ctrl] = pp->irq_mask[ctrl];
> +
> +	raw_spin_unlock_irqrestore(&pp->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int ultrarisc_pcie_resume(struct platform_device *pdev)
> +{
> +	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
> +	struct dw_pcie *pci = ultrarisc_pcie->pci;
> +	struct dw_pcie_rp *pp = &pci->pp;
> +	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> +	unsigned long flags;
> +	int ctrl;
> +
> +	raw_spin_lock_irqsave(&pp->lock, flags);
> +
> +	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
> +		pp->irq_mask[ctrl] = ultrarisc_pcie->irq_mask[ctrl];
> +		dw_pcie_writel_dbi(pci,
> +				   PCIE_MSI_INTR0_MASK +
> +				   ctrl * MSI_REG_CTRL_BLOCK_SIZE,
> +				   pp->irq_mask[ctrl]);
> +	}
> +
> +	raw_spin_unlock_irqrestore(&pp->lock, flags);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id ultrarisc_pcie_of_match[] = {
> +	{
> +		.compatible = "ultrarisc,dp1000-pcie",
> +	},
> +	{},
> +};
> +
> +static struct platform_driver ultrarisc_pcie_driver = {
> +	.driver = {
> +		.name	= "ultrarisc-pcie",
> +		.of_match_table = ultrarisc_pcie_of_match,
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe = ultrarisc_pcie_probe,
> +	.suspend = ultrarisc_pcie_suspend,
> +	.resume = ultrarisc_pcie_resume,

Use generic driver PM instead of the platform_driver.suspend/resume.

> +};
> +builtin_platform_driver(ultrarisc_pcie_driver);
> 
> -- 
> 2.34.1
> 
> 

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Re: [PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Jia Wang]

On 2026-03-16 15:49 -0500, Bjorn Helgaas wrote:
> In subject, s/dwc/ultrarisc/ or whatever tag we're going to use for
> this driver, e.g.,
> 
>   PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver
> 
> On Mon, Mar 16, 2026 at 03:07:00PM +0800, Jia Wang via B4 Relay wrote:
> > From: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > 
> > Add DP1000 soc PCIe rc driver.
> 
> s/soc/SoC/
> s/rc/RC/ or Root Complex (also in subject)
>

Thanks for the review.

I will update the subject and commit message accordingly.
 
> > Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  drivers/pci/controller/dwc/Kconfig           |  15 ++
> >  drivers/pci/controller/dwc/Makefile          |   1 +
> >  drivers/pci/controller/dwc/pcie-designware.h |  22 +++
> >  drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
> >  4 files changed, 240 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > index d0aa031397fa..0a33891bf7ef 100644
> > --- a/drivers/pci/controller/dwc/Kconfig
> > +++ b/drivers/pci/controller/dwc/Kconfig
> > @@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
> >  	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> >  	  This driver supports TMPV7708 SoC.
> >  
> > +config PCIE_ULTRARISC
> > +	bool "UltraRISC PCIe host controller"
> > +	depends on ARCH_ULTRARISC || COMPILE_TEST
> > +	select PCIE_DW_HOST
> > +	select PCI_MSI
> > +	default y if ARCH_ULTRARISC
> > +	help
> > +	  Enables support for the PCIe controller in the UltraRISC SoC.
> > +	  This driver supports UR-DP1000 SoC. When selected, it automatically
> > +	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
> > +	  for MSI-based interrupt handling in the PCIe controller.
> 
> I don't think the PCIE_DW_HOST and PCI_MSI explanation is relevant for
> Kconfig help.
>

I’ll remove the explanation about PCIE_DW_HOST and PCI_MSI from the
Kconfig help.
 
> > +	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
> > +	  requiring no further configuration on that platform.
> > +
> > +
> 
> Remove spurious blank line.
> 
> >  endmenu
> > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> > index 67ba59c02038..884c46b78e01 100644
> > --- a/drivers/pci/controller/dwc/Makefile
> > +++ b/drivers/pci/controller/dwc/Makefile
> > @@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
> >  obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
> >  obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
> >  obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
> > +obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o
> >  
> >  # The following drivers are for devices that use the generic ACPI
> >  # pci_root.c driver but don't support standard ECAM config access.
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index ae6389dd9caa..8f2ed86cb5c5 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -69,6 +69,8 @@
> >  
> >  /* Synopsys-specific PCIe configuration registers */
> >  #define PCIE_PORT_FORCE			0x708
> > +/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
> > +#define PORT_LINK_NUM_MASK		GENMASK(7, 0)
> >  #define PORT_FORCE_DO_DESKEW_FOR_SRIS	BIT(23)
> >  
> >  #define PCIE_PORT_AFR			0x70C
> > @@ -96,6 +98,26 @@
> >  #define PCIE_PORT_LANE_SKEW		0x714
> >  #define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)
> >  
> > +/*
> > + * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number Register.
> > + * This register holds the ack frequency, latency, replay, fast link scaling timers,
> > + * and max function number values.
> 
> Wrap to fit in 80 columns like the rest of the file.
> 
> > + * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.
> > + *   0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us).
> > + *     When the LTSSM is in Config or L12 Entry State, 1ms
> > + *     timer is 2us, 2ms timer is 4us and 3ms timer is 6us.
> > + *   0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)
> > + *   0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
> > + *   0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
> > + */
> > +#define PCIE_TIMER_CTRL_MAX_FUNC_NUM    0x718
> > +#define PORT_FLT_SF_MASK    GENMASK(30, 29)
> > +#define PORT_FLT_SF(n)      FIELD_PREP(PORT_FLT_SF_MASK, n)
> > +#define PORT_FLT_SF_1024    PORT_FLT_SF(0x0)
> > +#define PORT_FLT_SF_256     PORT_FLT_SF(0x1)
> > +#define PORT_FLT_SF_64      PORT_FLT_SF(0x2)
> > +#define PORT_FLT_SF_16      PORT_FLT_SF(0x3)
> > +
> >  #define PCIE_PORT_DEBUG0		0x728
> >  #define PORT_LOGIC_LTSSM_STATE_MASK	0x3f
> >  #define PORT_LOGIC_LTSSM_STATE_L0	0x11
> > diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
> > new file mode 100644
> > index 000000000000..64cbf16d3ff7
> > --- /dev/null
> > +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
> > @@ -0,0 +1,202 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * DWC PCIe RC driver for UltraRISC DP1000 SoC
> > + *
> > + * Copyright (C) 2023 UltraRISC
> > + *
> 
> Remove spurious blank line.  Maybe you want "(C) 2026"?
>

I’ll update the copyright year to 2026 as suggested.
 
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/kernel.h>
> > +#include <linux/init.h>
> > +#include <linux/of_device.h>
> > +#include <linux/pci.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/resource.h>
> > +#include <linux/types.h>
> > +#include <linux/regmap.h>
> 
> Order alphabetically.
> 
> > +#include "pcie-designware.h"
> > +
> > +#define PCIE_CUS_CORE          0x400000
> > +
> > +#define LTSSM_ENABLE           BIT(7)
> > +#define FAST_LINK_MODE         BIT(12)
> > +#define HOLD_PHY_RST           BIT(14)
> > +#define L1SUB_DISABLE          BIT(15)
> > +
> > +struct ultrarisc_pcie {
> > +	struct dw_pcie  *pci;
> 
> s/dw_pcie  /dw_pcie / (single space to match irq_mask below)
> 
> > +	u32 irq_mask[MAX_MSI_CTRLS];
> > +};
> > +
> > +static const struct of_device_id ultrarisc_pcie_of_match[];
> 
> This declaration looks unnecessary.
> 
> > +static struct pci_ops ultrarisc_pci_ops = {
> > +	.map_bus = dw_pcie_own_conf_map_bus,
> > +	.read = pci_generic_config_read32,
> > +	.write = pci_generic_config_write32,
> 
> I guess this hardware has the defect that it can only do 32-bit
> writes?
>
 
Yes, that's correct.

> > +};
> > +
> > +static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
> > +{
> > +	struct pci_host_bridge *bridge = pp->bridge;
> > +
> > +	/* Set the bus ops */
> 
> Drop spurious comment.
> 
> > +	bridge->ops = &ultrarisc_pci_ops;
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {
> > +	.init = ultrarisc_pcie_host_init,
> > +};
> > +
> > +static int ultrarisc_pcie_establish_link(struct dw_pcie *pci)
> > +{
> > +	u32 val;
> > +	u8 cap_exp;
> > +
> > +	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
> > +	val &= ~FAST_LINK_MODE;
> > +	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
> > +
> > +	val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
> > +	val &= ~PORT_FLT_SF_MASK;
> > +	val |= PORT_FLT_SF_64;
> 
> FIELD_MODIFY() here and below.
>

I'll update to FIELD_MODIFY().
 
> > +	dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
> > +
> > +	cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > +	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
> > +	val &= ~PCI_EXP_LNKCTL2_TLS;
> > +	val |= PCI_EXP_LNKCTL2_TLS_16_0GT;
> > +	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
> > +
> > +	val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
> > +	val &= ~PORT_LINK_NUM_MASK;
> > +	dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
> > +
> > +	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
> > +	val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
> > +	val |= 0x6;
> > +	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);
> > +
> > +	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
> > +	val &= ~(HOLD_PHY_RST | L1SUB_DISABLE);
> > +	val |= LTSSM_ENABLE;
> > +	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct dw_pcie_ops dw_pcie_ops = {
> > +	.start_link = ultrarisc_pcie_establish_link,
> 
> s/ultrarisc_pcie_establish_link/ultrarisc_pcie_start_link/
> to match member name and other drivers.
> 
> > +};
> > +
> > +static int ultrarisc_pcie_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct ultrarisc_pcie *ultrarisc_pcie;
> 
> "ultrarisc_pcie" is a pretty long name that will be used for
> parameters when you add more functionality.  Several drivers just use
> "pcie", some use the equivalent of "ultrarisc", etc.
>

I’ll rename the function to ultrarisc_pcie_start_link and shorten
the local variable to pcie.
 
> > +	struct dw_pcie *pci;
> > +	struct dw_pcie_rp *pp;
> > +	int ret;
> > +
> > +	ultrarisc_pcie = devm_kzalloc(dev, sizeof(*ultrarisc_pcie), GFP_KERNEL);
> > +	if (!ultrarisc_pcie)
> > +		return -ENOMEM;
> > +
> > +	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> > +	if (!pci)
> > +		return -ENOMEM;
> > +
> > +	pci->dev = dev;
> > +	pci->ops = &dw_pcie_ops;
> > +
> > +	/* Set a default value suitable for at most 16 in and 16 out windows */
> > +	pci->atu_size = SZ_8K;
> > +
> > +	ultrarisc_pcie->pci = pci;
> > +
> > +	pp = &pci->pp;
> > +
> > +	platform_set_drvdata(pdev, ultrarisc_pcie);
> > +
> > +	pp->irq = platform_get_irq(pdev, 1);
> > +	if (pp->irq < 0)
> > +		return pp->irq;
> > +
> > +	pp->num_vectors = MAX_MSI_IRQS;
> > +	pp->ops = &ultrarisc_pcie_host_ops;
> > +
> > +	ret = dw_pcie_host_init(pp);
> > +	if (ret) {
> > +		dev_err(dev, "Failed to initialize host\n");
> > +		return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int ultrarisc_pcie_suspend(struct platform_device *pdev, pm_message_t state)
> 
> If you use generic power management, this will be:
> 
>   static int ultrarisc_pcie_suspend(struct device *dev)
> 
> > +{
> > +	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
> > +	struct dw_pcie *pci = ultrarisc_pcie->pci;
> > +	struct dw_pcie_rp *pp = &pci->pp;
> > +	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> > +	unsigned long flags;
> > +	int ctrl;
> > +
> > +	raw_spin_lock_irqsave(&pp->lock, flags);
> > +
> > +	for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> > +		ultrarisc_pcie->irq_mask[ctrl] = pp->irq_mask[ctrl];
> > +
> > +	raw_spin_unlock_irqrestore(&pp->lock, flags);
> > +
> > +	return 0;
> > +}
> > +
> > +static int ultrarisc_pcie_resume(struct platform_device *pdev)
> > +{
> > +	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
> > +	struct dw_pcie *pci = ultrarisc_pcie->pci;
> > +	struct dw_pcie_rp *pp = &pci->pp;
> > +	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> > +	unsigned long flags;
> > +	int ctrl;
> > +
> > +	raw_spin_lock_irqsave(&pp->lock, flags);
> > +
> > +	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
> > +		pp->irq_mask[ctrl] = ultrarisc_pcie->irq_mask[ctrl];
> > +		dw_pcie_writel_dbi(pci,
> > +				   PCIE_MSI_INTR0_MASK +
> > +				   ctrl * MSI_REG_CTRL_BLOCK_SIZE,
> > +				   pp->irq_mask[ctrl]);
> > +	}
> > +
> > +	raw_spin_unlock_irqrestore(&pp->lock, flags);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id ultrarisc_pcie_of_match[] = {
> > +	{
> > +		.compatible = "ultrarisc,dp1000-pcie",
> > +	},
> > +	{},
> > +};
> > +
> > +static struct platform_driver ultrarisc_pcie_driver = {
> > +	.driver = {
> > +		.name	= "ultrarisc-pcie",
> > +		.of_match_table = ultrarisc_pcie_of_match,
> > +		.suppress_bind_attrs = true,
> > +	},
> > +	.probe = ultrarisc_pcie_probe,
> > +	.suspend = ultrarisc_pcie_suspend,
> > +	.resume = ultrarisc_pcie_resume,
> 
> Use generic driver PM instead of the platform_driver.suspend/resume.
>

I’ll switch to generic driver PM, and also fix the
Kconfig and formatting issues.

> > +};
> > +builtin_platform_driver(ultrarisc_pcie_driver);
> > 
> > -- 
> > 2.34.1
> > 
> > 
> 

Best regards,
Jia
 

Re: [PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Jia Wang]

On 2026-03-16 15:49 -0500, Bjorn Helgaas wrote:
> In subject, s/dwc/ultrarisc/ or whatever tag we're going to use for
> this driver, e.g.,
> 
>   PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver
> 
> On Mon, Mar 16, 2026 at 03:07:00PM +0800, Jia Wang via B4 Relay wrote:
> > From: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > 
> > Add DP1000 soc PCIe rc driver.
> 
> s/soc/SoC/
> s/rc/RC/ or Root Complex (also in subject)
>

Thanks for the review.

I will update the subject and commit message accordingly.
 
> > Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  drivers/pci/controller/dwc/Kconfig           |  15 ++
> >  drivers/pci/controller/dwc/Makefile          |   1 +
> >  drivers/pci/controller/dwc/pcie-designware.h |  22 +++
> >  drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
> >  4 files changed, 240 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > index d0aa031397fa..0a33891bf7ef 100644
> > --- a/drivers/pci/controller/dwc/Kconfig
> > +++ b/drivers/pci/controller/dwc/Kconfig
> > @@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
> >  	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> >  	  This driver supports TMPV7708 SoC.
> >  
> > +config PCIE_ULTRARISC
> > +	bool "UltraRISC PCIe host controller"
> > +	depends on ARCH_ULTRARISC || COMPILE_TEST
> > +	select PCIE_DW_HOST
> > +	select PCI_MSI
> > +	default y if ARCH_ULTRARISC
> > +	help
> > +	  Enables support for the PCIe controller in the UltraRISC SoC.
> > +	  This driver supports UR-DP1000 SoC. When selected, it automatically
> > +	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
> > +	  for MSI-based interrupt handling in the PCIe controller.
> 
> I don't think the PCIE_DW_HOST and PCI_MSI explanation is relevant for
> Kconfig help.
>

I’ll remove the explanation about PCIE_DW_HOST and PCI_MSI from the
Kconfig help.
 
> > +	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
> > +	  requiring no further configuration on that platform.
> > +
> > +
> 
> Remove spurious blank line.
> 
> >  endmenu
> > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> > index 67ba59c02038..884c46b78e01 100644
> > --- a/drivers/pci/controller/dwc/Makefile
> > +++ b/drivers/pci/controller/dwc/Makefile
> > @@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
> >  obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
> >  obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
> >  obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
> > +obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o
> >  
> >  # The following drivers are for devices that use the generic ACPI
> >  # pci_root.c driver but don't support standard ECAM config access.
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index ae6389dd9caa..8f2ed86cb5c5 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -69,6 +69,8 @@
> >  
> >  /* Synopsys-specific PCIe configuration registers */
> >  #define PCIE_PORT_FORCE			0x708
> > +/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
> > +#define PORT_LINK_NUM_MASK		GENMASK(7, 0)
> >  #define PORT_FORCE_DO_DESKEW_FOR_SRIS	BIT(23)
> >  
> >  #define PCIE_PORT_AFR			0x70C
> > @@ -96,6 +98,26 @@
> >  #define PCIE_PORT_LANE_SKEW		0x714
> >  #define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)
> >  
> > +/*
> > + * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number Register.
> > + * This register holds the ack frequency, latency, replay, fast link scaling timers,
> > + * and max function number values.
> 
> Wrap to fit in 80 columns like the rest of the file.
> 
> > + * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.
> > + *   0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us).
> > + *     When the LTSSM is in Config or L12 Entry State, 1ms
> > + *     timer is 2us, 2ms timer is 4us and 3ms timer is 6us.
> > + *   0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)
> > + *   0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
> > + *   0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
> > + */
> > +#define PCIE_TIMER_CTRL_MAX_FUNC_NUM    0x718
> > +#define PORT_FLT_SF_MASK    GENMASK(30, 29)
> > +#define PORT_FLT_SF(n)      FIELD_PREP(PORT_FLT_SF_MASK, n)
> > +#define PORT_FLT_SF_1024    PORT_FLT_SF(0x0)
> > +#define PORT_FLT_SF_256     PORT_FLT_SF(0x1)
> > +#define PORT_FLT_SF_64      PORT_FLT_SF(0x2)
> > +#define PORT_FLT_SF_16      PORT_FLT_SF(0x3)
> > +
> >  #define PCIE_PORT_DEBUG0		0x728
> >  #define PORT_LOGIC_LTSSM_STATE_MASK	0x3f
> >  #define PORT_LOGIC_LTSSM_STATE_L0	0x11
> > diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
> > new file mode 100644
> > index 000000000000..64cbf16d3ff7
> > --- /dev/null
> > +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
> > @@ -0,0 +1,202 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * DWC PCIe RC driver for UltraRISC DP1000 SoC
> > + *
> > + * Copyright (C) 2023 UltraRISC
> > + *
> 
> Remove spurious blank line.  Maybe you want "(C) 2026"?
>

I’ll update the copyright year to 2026 as suggested.
 
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/kernel.h>
> > +#include <linux/init.h>
> > +#include <linux/of_device.h>
> > +#include <linux/pci.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/resource.h>
> > +#include <linux/types.h>
> > +#include <linux/regmap.h>
> 
> Order alphabetically.
> 
> > +#include "pcie-designware.h"
> > +
> > +#define PCIE_CUS_CORE          0x400000
> > +
> > +#define LTSSM_ENABLE           BIT(7)
> > +#define FAST_LINK_MODE         BIT(12)
> > +#define HOLD_PHY_RST           BIT(14)
> > +#define L1SUB_DISABLE          BIT(15)
> > +
> > +struct ultrarisc_pcie {
> > +	struct dw_pcie  *pci;
> 
> s/dw_pcie  /dw_pcie / (single space to match irq_mask below)
> 
> > +	u32 irq_mask[MAX_MSI_CTRLS];
> > +};
> > +
> > +static const struct of_device_id ultrarisc_pcie_of_match[];
> 
> This declaration looks unnecessary.
> 
> > +static struct pci_ops ultrarisc_pci_ops = {
> > +	.map_bus = dw_pcie_own_conf_map_bus,
> > +	.read = pci_generic_config_read32,
> > +	.write = pci_generic_config_write32,
> 
> I guess this hardware has the defect that it can only do 32-bit
> writes?
>
 
Yes, that's correct.

> > +};
> > +
> > +static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
> > +{
> > +	struct pci_host_bridge *bridge = pp->bridge;
> > +
> > +	/* Set the bus ops */
> 
> Drop spurious comment.
> 
> > +	bridge->ops = &ultrarisc_pci_ops;
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {
> > +	.init = ultrarisc_pcie_host_init,
> > +};
> > +
> > +static int ultrarisc_pcie_establish_link(struct dw_pcie *pci)
> > +{
> > +	u32 val;
> > +	u8 cap_exp;
> > +
> > +	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
> > +	val &= ~FAST_LINK_MODE;
> > +	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
> > +
> > +	val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
> > +	val &= ~PORT_FLT_SF_MASK;
> > +	val |= PORT_FLT_SF_64;
> 
> FIELD_MODIFY() here and below.
>

I'll update to FIELD_MODIFY().
 
> > +	dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
> > +
> > +	cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > +	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
> > +	val &= ~PCI_EXP_LNKCTL2_TLS;
> > +	val |= PCI_EXP_LNKCTL2_TLS_16_0GT;
> > +	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
> > +
> > +	val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
> > +	val &= ~PORT_LINK_NUM_MASK;
> > +	dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
> > +
> > +	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
> > +	val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
> > +	val |= 0x6;
> > +	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);
> > +
> > +	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
> > +	val &= ~(HOLD_PHY_RST | L1SUB_DISABLE);
> > +	val |= LTSSM_ENABLE;
> > +	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct dw_pcie_ops dw_pcie_ops = {
> > +	.start_link = ultrarisc_pcie_establish_link,
> 
> s/ultrarisc_pcie_establish_link/ultrarisc_pcie_start_link/
> to match member name and other drivers.
> 
> > +};
> > +
> > +static int ultrarisc_pcie_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct ultrarisc_pcie *ultrarisc_pcie;
> 
> "ultrarisc_pcie" is a pretty long name that will be used for
> parameters when you add more functionality.  Several drivers just use
> "pcie", some use the equivalent of "ultrarisc", etc.
>

I’ll rename the function to ultrarisc_pcie_start_link and shorten
the local variable to pcie.
 
> > +	struct dw_pcie *pci;
> > +	struct dw_pcie_rp *pp;
> > +	int ret;
> > +
> > +	ultrarisc_pcie = devm_kzalloc(dev, sizeof(*ultrarisc_pcie), GFP_KERNEL);
> > +	if (!ultrarisc_pcie)
> > +		return -ENOMEM;
> > +
> > +	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> > +	if (!pci)
> > +		return -ENOMEM;
> > +
> > +	pci->dev = dev;
> > +	pci->ops = &dw_pcie_ops;
> > +
> > +	/* Set a default value suitable for at most 16 in and 16 out windows */
> > +	pci->atu_size = SZ_8K;
> > +
> > +	ultrarisc_pcie->pci = pci;
> > +
> > +	pp = &pci->pp;
> > +
> > +	platform_set_drvdata(pdev, ultrarisc_pcie);
> > +
> > +	pp->irq = platform_get_irq(pdev, 1);
> > +	if (pp->irq < 0)
> > +		return pp->irq;
> > +
> > +	pp->num_vectors = MAX_MSI_IRQS;
> > +	pp->ops = &ultrarisc_pcie_host_ops;
> > +
> > +	ret = dw_pcie_host_init(pp);
> > +	if (ret) {
> > +		dev_err(dev, "Failed to initialize host\n");
> > +		return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int ultrarisc_pcie_suspend(struct platform_device *pdev, pm_message_t state)
> 
> If you use generic power management, this will be:
> 
>   static int ultrarisc_pcie_suspend(struct device *dev)
> 
> > +{
> > +	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
> > +	struct dw_pcie *pci = ultrarisc_pcie->pci;
> > +	struct dw_pcie_rp *pp = &pci->pp;
> > +	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> > +	unsigned long flags;
> > +	int ctrl;
> > +
> > +	raw_spin_lock_irqsave(&pp->lock, flags);
> > +
> > +	for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> > +		ultrarisc_pcie->irq_mask[ctrl] = pp->irq_mask[ctrl];
> > +
> > +	raw_spin_unlock_irqrestore(&pp->lock, flags);
> > +
> > +	return 0;
> > +}
> > +
> > +static int ultrarisc_pcie_resume(struct platform_device *pdev)
> > +{
> > +	struct ultrarisc_pcie *ultrarisc_pcie = platform_get_drvdata(pdev);
> > +	struct dw_pcie *pci = ultrarisc_pcie->pci;
> > +	struct dw_pcie_rp *pp = &pci->pp;
> > +	int num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> > +	unsigned long flags;
> > +	int ctrl;
> > +
> > +	raw_spin_lock_irqsave(&pp->lock, flags);
> > +
> > +	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
> > +		pp->irq_mask[ctrl] = ultrarisc_pcie->irq_mask[ctrl];
> > +		dw_pcie_writel_dbi(pci,
> > +				   PCIE_MSI_INTR0_MASK +
> > +				   ctrl * MSI_REG_CTRL_BLOCK_SIZE,
> > +				   pp->irq_mask[ctrl]);
> > +	}
> > +
> > +	raw_spin_unlock_irqrestore(&pp->lock, flags);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id ultrarisc_pcie_of_match[] = {
> > +	{
> > +		.compatible = "ultrarisc,dp1000-pcie",
> > +	},
> > +	{},
> > +};
> > +
> > +static struct platform_driver ultrarisc_pcie_driver = {
> > +	.driver = {
> > +		.name	= "ultrarisc-pcie",
> > +		.of_match_table = ultrarisc_pcie_of_match,
> > +		.suppress_bind_attrs = true,
> > +	},
> > +	.probe = ultrarisc_pcie_probe,
> > +	.suspend = ultrarisc_pcie_suspend,
> > +	.resume = ultrarisc_pcie_resume,
> 
> Use generic driver PM instead of the platform_driver.suspend/resume.
>

I’ll switch to generic driver PM, and also fix the
Kconfig and formatting issues.

> > +};
> > +builtin_platform_driver(ultrarisc_pcie_driver);
> > 
> > -- 
> > 2.34.1
> > 
> > 
> 

Best regards,
Jia
 


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Re: [PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Yao Zi]

On Mon, Mar 16, 2026 at 03:07:00PM +0800, Jia Wang via B4 Relay wrote:
> From: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> 
> Add DP1000 soc PCIe rc driver.
> 
> Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  drivers/pci/controller/dwc/Kconfig           |  15 ++
>  drivers/pci/controller/dwc/Makefile          |   1 +
>  drivers/pci/controller/dwc/pcie-designware.h |  22 +++
>  drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
>  4 files changed, 240 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index d0aa031397fa..0a33891bf7ef 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
>  	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
>  	  This driver supports TMPV7708 SoC.
>  
> +config PCIE_ULTRARISC
> +	bool "UltraRISC PCIe host controller"

Is there any reason preventing the driver being built as a module? If
no, it would be better to change it to "tristate", to allow distribution
to customize the configuration for image sizes, etc.

> +	depends on ARCH_ULTRARISC || COMPILE_TEST
> +	select PCIE_DW_HOST
> +	select PCI_MSI
> +	default y if ARCH_ULTRARISC
> +	help
> +	  Enables support for the PCIe controller in the UltraRISC SoC.
> +	  This driver supports UR-DP1000 SoC. When selected, it automatically
> +	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
> +	  for MSI-based interrupt handling in the PCIe controller.
> +	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
> +	  requiring no further configuration on that platform.
> +
> +
>  endmenu
>  #define PORT_LOGIC_LTSSM_STATE_L0	0x11

Best regards,
Yao Zi

Re: [PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Yao Zi]

On Mon, Mar 16, 2026 at 03:07:00PM +0800, Jia Wang via B4 Relay wrote:
> From: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> 
> Add DP1000 soc PCIe rc driver.
> 
> Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  drivers/pci/controller/dwc/Kconfig           |  15 ++
>  drivers/pci/controller/dwc/Makefile          |   1 +
>  drivers/pci/controller/dwc/pcie-designware.h |  22 +++
>  drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
>  4 files changed, 240 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index d0aa031397fa..0a33891bf7ef 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
>  	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
>  	  This driver supports TMPV7708 SoC.
>  
> +config PCIE_ULTRARISC
> +	bool "UltraRISC PCIe host controller"

Is there any reason preventing the driver being built as a module? If
no, it would be better to change it to "tristate", to allow distribution
to customize the configuration for image sizes, etc.

> +	depends on ARCH_ULTRARISC || COMPILE_TEST
> +	select PCIE_DW_HOST
> +	select PCI_MSI
> +	default y if ARCH_ULTRARISC
> +	help
> +	  Enables support for the PCIe controller in the UltraRISC SoC.
> +	  This driver supports UR-DP1000 SoC. When selected, it automatically
> +	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
> +	  for MSI-based interrupt handling in the PCIe controller.
> +	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
> +	  requiring no further configuration on that platform.
> +
> +
>  endmenu
>  #define PORT_LOGIC_LTSSM_STATE_L0	0x11

Best regards,
Yao Zi

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Re: [PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Jia Wang]

On 2026-03-17 05:32 +0000, Yao Zi wrote:
> On Mon, Mar 16, 2026 at 03:07:00PM +0800, Jia Wang via B4 Relay wrote:
> > From: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > 
> > Add DP1000 soc PCIe rc driver.
> > 
> > Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  drivers/pci/controller/dwc/Kconfig           |  15 ++
> >  drivers/pci/controller/dwc/Makefile          |   1 +
> >  drivers/pci/controller/dwc/pcie-designware.h |  22 +++
> >  drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
> >  4 files changed, 240 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > index d0aa031397fa..0a33891bf7ef 100644
> > --- a/drivers/pci/controller/dwc/Kconfig
> > +++ b/drivers/pci/controller/dwc/Kconfig
> > @@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
> >  	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> >  	  This driver supports TMPV7708 SoC.
> >  
> > +config PCIE_ULTRARISC
> > +	bool "UltraRISC PCIe host controller"
> 
> Is there any reason preventing the driver being built as a module? If
> no, it would be better to change it to "tristate", to allow distribution
> to customize the configuration for image sizes, etc.
>

Thanks for the suggestion. I will update PCIE_ULTRARISC to tristate.
 
> > +	depends on ARCH_ULTRARISC || COMPILE_TEST
> > +	select PCIE_DW_HOST
> > +	select PCI_MSI
> > +	default y if ARCH_ULTRARISC
> > +	help
> > +	  Enables support for the PCIe controller in the UltraRISC SoC.
> > +	  This driver supports UR-DP1000 SoC. When selected, it automatically
> > +	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
> > +	  for MSI-based interrupt handling in the PCIe controller.
> > +	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
> > +	  requiring no further configuration on that platform.
> > +
> > +
> >  endmenu
> >  #define PORT_LOGIC_LTSSM_STATE_L0	0x11
> 
> Best regards,
> Yao Zi
>

Best regards,
Jia 

Re: [PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver

[Jia Wang]

On 2026-03-17 05:32 +0000, Yao Zi wrote:
> On Mon, Mar 16, 2026 at 03:07:00PM +0800, Jia Wang via B4 Relay wrote:
> > From: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > 
> > Add DP1000 soc PCIe rc driver.
> > 
> > Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  drivers/pci/controller/dwc/Kconfig           |  15 ++
> >  drivers/pci/controller/dwc/Makefile          |   1 +
> >  drivers/pci/controller/dwc/pcie-designware.h |  22 +++
> >  drivers/pci/controller/dwc/pcie-ultrarisc.c  | 202 +++++++++++++++++++++++++++
> >  4 files changed, 240 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > index d0aa031397fa..0a33891bf7ef 100644
> > --- a/drivers/pci/controller/dwc/Kconfig
> > +++ b/drivers/pci/controller/dwc/Kconfig
> > @@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST
> >  	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> >  	  This driver supports TMPV7708 SoC.
> >  
> > +config PCIE_ULTRARISC
> > +	bool "UltraRISC PCIe host controller"
> 
> Is there any reason preventing the driver being built as a module? If
> no, it would be better to change it to "tristate", to allow distribution
> to customize the configuration for image sizes, etc.
>

Thanks for the suggestion. I will update PCIE_ULTRARISC to tristate.
 
> > +	depends on ARCH_ULTRARISC || COMPILE_TEST
> > +	select PCIE_DW_HOST
> > +	select PCI_MSI
> > +	default y if ARCH_ULTRARISC
> > +	help
> > +	  Enables support for the PCIe controller in the UltraRISC SoC.
> > +	  This driver supports UR-DP1000 SoC. When selected, it automatically
> > +	  enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support
> > +	  for MSI-based interrupt handling in the PCIe controller.
> > +	  By default, this symbol is enabled when `ARCH_ULTRARISC` is active,
> > +	  requiring no further configuration on that platform.
> > +
> > +
> >  endmenu
> >  #define PORT_LOGIC_LTSSM_STATE_L0	0x11
> 
> Best regards,
> Yao Zi
>

Best regards,
Jia 



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