Re: [PATCH v3 10/13] hw/riscv/atlantis: Add PCIe controller

[Nicholas Piggin <npiggin@gmail.com>]

On Tue, Apr 21, 2026 at 07:59:32AM +0200, Philippe Mathieu-Daudé wrote:
> On 21/4/26 07:31, Joel Stanley wrote:
> > From: Nicholas Piggin <npiggin@gmail.com>
> > 
> > tt-atlantis is likely to use a generic ECAM compatible PCIe memory map,
> > so gpex is not far off the OS programming model
> > 
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> > Signed-off-by: Joel Stanley <joel@jms.id.au>
> > ---
> > v3: Avoid leaks in the dt string allocation
> > ---
> >   include/hw/riscv/tt_atlantis.h |   2 +
> >   hw/riscv/tt_atlantis.c         | 225 ++++++++++++++++++++++++++++++++-
> >   hw/riscv/Kconfig               |   2 +
> >   3 files changed, 228 insertions(+), 1 deletion(-)
> 
> 
> > +static void create_fdt_pcie(void *fdt,
> > +                            const MemMapEntry *mem_ecam,
> > +                            const MemMapEntry *mem_pio,
> > +                            const MemMapEntry *mem_mmio32,
> > +                            const MemMapEntry *mem_mmio64,
> > +                            int legacy_irq,
> > +                            uint32_t aplic_s_phandle,
> > +                            uint32_t imsic_s_phandle)
> > +{
> > +    g_autofree char *name = g_strdup_printf("/soc/pci@%"HWADDR_PRIX,
> > +                                            mem_ecam->base);
> > +
> > +    qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
> > +    qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
> > +    qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
> > +    qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
> > +    qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
> > +    qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
> > +                           mem_ecam->size / PCIE_MMCFG_SIZE_MIN - 1);
> > +    qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
> > +    qemu_fdt_setprop_cell(fdt, name, "msi-parent", imsic_s_phandle);
> > +
> > +    qemu_fdt_setprop_sized_cells(fdt, name, "reg",
> > +                                 2, mem_ecam->base,
> > +                                 2, mem_ecam->size);
> > +    if (!(mem_mmio32->base & 0xffffffffUL)) {
> > +        /* XXX: this is a silly hack because it would collide with PIO */
> 
> Could you explain a bit more?

Ah this is a bit incomplete sorry I didn't catch it earlier. Before the
mapping was finalised I just added this hacky way to determining PCIe IO
address based on the physical address.

This should just go away and the IO addresses come from a different table.

> 
> > +        error_report("mmio32 base must not be 0 mod 2^32");
> > +        exit(1);
> > +    }
> > +    uint32_t flags = FDT_PCI_RANGE_MMIO_64BIT | FDT_PCI_RANGE_PREFETCHABLE;
> > +    qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
> > +                                 1, FDT_PCI_RANGE_IOPORT,
> > +                                 2, 0x0,
> > +                                 2, mem_pio->base,
> > +                                 2, mem_pio->size,
> > +                                 1, FDT_PCI_RANGE_MMIO,
> > +                                 2, (mem_mmio32->base & 0xffffffffUL),
> > +                                 2, mem_mmio32->base,
> > +                                 2, mem_mmio32->size,
> > +                                 1, flags,
> > +                                 2, mem_mmio64->base,
> > +                                 2, mem_mmio64->base,
> > +                                 2, mem_mmio64->size);
> > +
> > +    create_pcie_irq_map(fdt, name, legacy_irq, aplic_s_phandle);
> > +}
> 
> 
> > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> > index 0601ae1a7494..2ddee591eb90 100644
> > --- a/hw/riscv/Kconfig
> > +++ b/hw/riscv/Kconfig
> > @@ -129,6 +129,8 @@ config TENSTORRENT
> >       select DEVICE_TREE
> >       select RISCV_NUMA
> >       select PVPANIC_MMIO
> > +    select PCI
> 
> Do not select PCI explicitly, let the bridge (below) do it.
> Rationale is this machine does not expose a PCI bus directly,
> the bridge device does.

Good to know, thank you.

Thanks,
Nick