[PATCH v2 0/7] Add UFS clock support for Qualcomm SoCs

[PATCH v2 0/7] Add UFS clock support for Qualcomm SoCs

[Balaji Selvanathan]

This series adds UFS clock support for QCS615, SA8775P SoCs and
enables U-Boot to initialize UFS clocks independently.

Previously, U-Boot depended on earlier bootloader stages to
initialize UFS clocks. When these bootloaders failed to do so,
UFS registers became inaccessible, preventing UFS initialization.
This series removes that dependency by adding clock infrastructure
and enabling U-Boot to configure UFS clocks directly.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
Changes in v2:
- Sort compatibles in drivers/clk/clk-stub.c alphabetically 
- Remove duplicate sc7280 compatible which was already there
- Remove ufs_qcom_init_clks function and move the clock enabling and
  rate set codes to ufs_qcom_init
- Remove ufs_qcom_setup_clocks POST_CHANGE duplicate call
- Link to v1: https://lore.kernel.org/u-boot/20260319-ufs_probe_clk-v1-0-08c085d6b15d@oss.qualcomm.com/

---
Balaji Selvanathan (7):
      clk: stub: Sort compatible strings alphabetically
      clk: qcom: clk-stub: Add compatibles for QCS615/SA8775P
      clk: qcom: sa8775p: Add UFS clock support
      clk: qcom: qcs615: Add UFS clock support
      clk: qcom: sc7280: Add UFS clock support
      drivers: ufs: qcom: Initialize and enable clocks before hardware access
      ufs: qcom: Remove redundant POST_CHANGE clock setup call

 drivers/clk/clk-stub.c           |  6 ++--
 drivers/clk/qcom/clock-qcs615.c  | 63 +++++++++++++++++++++++++++++++++++++++-
 drivers/clk/qcom/clock-sa8775p.c | 63 ++++++++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/clock-sc7280.c  | 52 +++++++++++++++++++++++++++++++++
 drivers/ufs/ufs-qcom.c           | 54 ++++++++++++++++++++++------------
 5 files changed, 217 insertions(+), 21 deletions(-)
---
base-commit: 9f61fd5b80a43ae20ba115e3a2933d47d720ab82
change-id: 20260427-ufs_clk-49c917afbc6f

Best regards,
-- 
Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>

[PATCH v2 1/7] clk: stub: Sort compatible strings alphabetically

[Balaji Selvanathan]

Reorder compatible strings in stub_clk_ids to maintain alphabetical
order for easier maintenance.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
Changes in v2:
- Newly added in v2
---
 drivers/clk/clk-stub.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
index 117266ac778..ddcaaa00d91 100644
--- a/drivers/clk/clk-stub.c
+++ b/drivers/clk/clk-stub.c
@@ -50,10 +50,10 @@ static struct clk_ops stub_clk_ops = {
 
 static const struct udevice_id stub_clk_ids[] = {
 	{ .compatible = "qcom,rpmcc" },
-	{ .compatible = "qcom,sdm670-rpmh-clk" },
-	{ .compatible = "qcom,sdm845-rpmh-clk" },
 	{ .compatible = "qcom,sc7180-rpmh-clk" },
 	{ .compatible = "qcom,sc7280-rpmh-clk" },
+	{ .compatible = "qcom,sdm670-rpmh-clk" },
+	{ .compatible = "qcom,sdm845-rpmh-clk" },
 	{ .compatible = "qcom,sm6350-rpmh-clk" },
 	{ .compatible = "qcom,sm8150-rpmh-clk" },
 	{ .compatible = "qcom,sm8250-rpmh-clk" },

-- 
2.34.1

[PATCH v2 2/7] clk: qcom: clk-stub: Add compatibles for QCS615/SA8775P

[Balaji Selvanathan]

Add RPMH clock compatible strings for QCS615 and SA8775P
SoCs to enable clock framework support on these platforms.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
Changes in v2:
- Removed sc7280 compatible which was already there
---
 drivers/clk/clk-stub.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
index ddcaaa00d91..4a6c71016da 100644
--- a/drivers/clk/clk-stub.c
+++ b/drivers/clk/clk-stub.c
@@ -49,7 +49,9 @@ static struct clk_ops stub_clk_ops = {
 };
 
 static const struct udevice_id stub_clk_ids[] = {
+	{ .compatible = "qcom,qcs615-rpmh-clk" },
 	{ .compatible = "qcom,rpmcc" },
+	{ .compatible = "qcom,sa8775p-rpmh-clk" },
 	{ .compatible = "qcom,sc7180-rpmh-clk" },
 	{ .compatible = "qcom,sc7280-rpmh-clk" },
 	{ .compatible = "qcom,sdm670-rpmh-clk" },

-- 
2.34.1

[PATCH v2 3/7] clk: qcom: sa8775p: Add UFS clock support

[Balaji Selvanathan]

Add UFS clock support for SA8775P including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
Changes in v2:
- No changes
---
 drivers/clk/qcom/clock-sa8775p.c | 63 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
index 4957abf6f58..7eec4aeae48 100644
--- a/drivers/clk/qcom/clock-sa8775p.c
+++ b/drivers/clk/qcom/clock-sa8775p.c
@@ -19,6 +19,11 @@
 #define USB30_PRIM_MASTER_CLK_CMD_RCGR		0x1b028
 #define USB3_PRIM_PHY_AUX_CMD_RCGR		0x1b06c
 
+#define UFS_PHY_AXI_CLK_CMD_RCGR		0x8302c
+#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR		0x83074
+#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR		0x830a8
+#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR	0x8308c
+
 #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
 #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
 #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)
@@ -44,9 +49,35 @@
 
 #define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25)
 
+/* UFS AXI clock frequency table */
+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
+	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
+	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
+	{ }
+};
+
+/* UFS ICE CORE clock frequency table */
+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
+	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
+	{ }
+};
+
+/* UFS UNIPRO CORE clock frequency table */
+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
+	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
+	{ }
+};
+
 static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct freq_tbl *freq;
 
 	if (clk->id < priv->data->num_clks)
 		debug("%s: %s, requested rate=%ld\n", __func__,
@@ -63,6 +94,24 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
 				     5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
 		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
 		return rate;
+	case GCC_UFS_PHY_AXI_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_UFS_PHY_UNIPRO_CORE_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_UFS_PHY_ICE_CORE_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_UFS_PHY_PHY_AUX_CLK:
+		clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
+		return 19200000;
 	default:
 		return 0;
 	}
@@ -106,6 +155,20 @@ static const struct gate_clk sa8775p_clks[] = {
 
 	/* QUP Wrapper 3 clocks */
 	GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT),
+
+	/* UFS PHY clocks */
+	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1),
+	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1),
+	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1),
+	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1),
+	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, 1),
+	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, 1),
+	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, 1),
+	GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, 1),
+	GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, 1),
+
+	/* EDP reference clock (used by UFS PHY) */
+	GATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, 1),
 };
 
 static int sa8775p_enable(struct clk *clk)

-- 
2.34.1

[PATCH v2 4/7] clk: qcom: qcs615: Add UFS clock support

[Balaji Selvanathan]

Add UFS clock support for qcs615 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
Changes in v2:
- No changes
---
 drivers/clk/qcom/clock-qcs615.c | 63 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
index 2087fc38f63..7b3fe49de9c 100644
--- a/drivers/clk/qcom/clock-qcs615.c
+++ b/drivers/clk/qcom/clock-qcs615.c
@@ -19,6 +19,11 @@
 #define USB30_PRIM_MASTER_CLK_CMD_RCGR		0xf01c
 #define USB3_PRIM_PHY_AUX_CMD_RCGR		0xf060
 
+#define UFS_PHY_AXI_CLK_CMD_RCGR		0x77020
+#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR		0x77048
+#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR	0x77060
+#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR		0x7707c
+
 #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
 #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
 #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)
@@ -33,9 +38,37 @@
 #define GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT BIT(26)
 #define GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT BIT(27)
 
+/* UFS PHY AXI clock frequency table */
+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
+	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+	F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+	F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
+	F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+	{ }
+};
+
+/* UFS PHY ICE CORE clock frequency table */
+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
+	F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
+	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
+	{ }
+};
+
+/* UFS PHY UNIPRO CORE clock frequency table */
+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
+	F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
+	F(75000000, CFG_CLK_SRC_GPLL0, 8, 0, 0),
+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
+	{ }
+};
+
 static ulong qcs615_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct freq_tbl *freq;
 
 	if (clk->id < priv->data->num_clks)
 		debug("%s: %s, requested rate=%ld\n", __func__,
@@ -52,6 +85,24 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)
 				     5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
 		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
 		return rate;
+	case GCC_UFS_PHY_AXI_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_UFS_PHY_UNIPRO_CORE_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_UFS_PHY_ICE_CORE_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_UFS_PHY_PHY_AUX_CLK:
+		clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
+		return 19200000;
 	default:
 		return 0;
 	}
@@ -81,7 +132,17 @@ static const struct gate_clk qcs615_clks[] = {
 	GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT),
 	GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT),
 	GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)),
-	GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0))
+	GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)),
+	/* UFS clocks */
+	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
+	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0)),
+	GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)),
 };
 
 static int qcs615_enable(struct clk *clk)

-- 
2.34.1

[PATCH v2 5/7] clk: qcom: sc7280: Add UFS clock support

[Balaji Selvanathan]

Add UFS clock support for sc7280 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
Changes in v2:
- No changes
---
 drivers/clk/qcom/clock-sc7280.c | 52 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 7b6ed826023..2c73c26484f 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -23,6 +23,10 @@
 #define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058
 #define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c
 #define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054
+#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77024
+#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x7706c
+#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x770a0
+#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77084
 
 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
 	F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
@@ -54,6 +58,33 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
 	{ }
 };
 
+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
+	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),
+	F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),
+	F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),
+	F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),
+	{ }
+};
+
 static ulong sc7280_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -103,6 +134,26 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)
 	case GCC_PCIE1_PHY_RCHNG_CLK:
 		clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);
 		return 100000000;
+	case GCC_UFS_PHY_AXI_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_UFS_PHY_ICE_CORE_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_UFS_PHY_PHY_AUX_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_phy_aux_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_UFS_PHY_UNIPRO_CORE_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
 	default:
 		return rate;
 	}
@@ -147,6 +198,7 @@ static const struct gate_clk sc7280_clks[] = {
 	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
 	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)),
 	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0)),
 	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)),
 	GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)),
 	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)),

-- 
2.34.1

[PATCH v2 6/7] drivers: ufs: qcom: Initialize and enable clocks before hardware access

[Balaji Selvanathan]

Move UFS clock initialization and enabling before hardware setup
to ensure clocks are running when accessing UFS registers.

Previously, U-Boot depended on earlier bootloader stages to
initialize UFS clocks. When these bootloaders failed to do so,
UFS registers became inaccessible, causing initialization to fail.
This change makes U-Boot initialize and enable UFS clocks early
in the init sequence, removing the dependency on previous
bootloaders.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
Changes in v2:
- Remove ufs_qcom_init_clks function and move the clock enabling and
      rate set codes to ufs_qcom_init
- Add clk_release_bulk if ufs_qcom_enable_clks fails
---
 drivers/ufs/ufs-qcom.c | 53 ++++++++++++++++++++++++++++++++++----------------
 1 file changed, 36 insertions(+), 17 deletions(-)

diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c
index dc40ee62daf..ae33f62fbee 100644
--- a/drivers/ufs/ufs-qcom.c
+++ b/drivers/ufs/ufs-qcom.c
@@ -30,6 +30,7 @@
 #define UFS_CPU_MAX_BANDWIDTH	819200
 
 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable);
+static u32 ufs_qcom_get_core_clk_unipro_max_freq(struct ufs_hba *hba);
 
 static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv)
 {
@@ -47,17 +48,6 @@ static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv)
 	return 0;
 }
 
-static int ufs_qcom_init_clks(struct ufs_qcom_priv *priv)
-{
-	int err;
-	struct udevice *dev = priv->hba->dev;
-
-	err = clk_get_bulk(dev, &priv->clks);
-	if (err)
-		return err;
-
-	return 0;
-}
 
 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
 {
@@ -557,10 +547,45 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable)
 static int ufs_qcom_init(struct ufs_hba *hba)
 {
 	struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
+	struct udevice *dev = hba->dev;
+	struct clk clk;
+	u32 max_freq;
+	long rate;
 	int err;
 
 	priv->hba = hba;
 
+	/* Get maximum frequency for core_clk_unipro from device tree */
+	max_freq = ufs_qcom_get_core_clk_unipro_max_freq(hba);
+
+	/* Get and configure core_clk_unipro */
+	err = clk_get_by_name(dev, "core_clk_unipro", &clk);
+	if (err) {
+		dev_err(dev, "Failed to get core_clk_unipro: %d\n", err);
+		return err;
+	}
+
+	rate = clk_set_rate(&clk, max_freq);
+	if (rate < 0) {
+		dev_err(dev, "Failed to set core_clk_unipro rate to %u Hz: %ld\n",
+			max_freq, rate);
+	}
+
+	/* Get all clocks */
+	err = clk_get_bulk(dev, &priv->clks);
+	if (err) {
+		dev_err(dev, "clk_get_bulk failed: %d\n", err);
+		return err;
+	}
+
+	/* Enable clocks */
+	err = ufs_qcom_enable_clks(priv);
+	if (err) {
+		dev_err(dev, "failed to enable clocks: %d\n", err);
+		clk_release_bulk(&priv->clks);
+		return err;
+	}
+
 	/* setup clocks */
 	ufs_qcom_setup_clocks(hba, true, PRE_CHANGE);
 
@@ -579,12 +604,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
 		 priv->hw_ver.minor,
 		 priv->hw_ver.step);
 
-	err = ufs_qcom_init_clks(priv);
-	if (err) {
-		dev_err(hba->dev, "failed to initialize clocks, err:%d\n", err);
-		return err;
-	}
-
 	ufs_qcom_advertise_quirks(hba);
 	ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
 

-- 
2.34.1

[PATCH v2 7/7] ufs: qcom: Remove redundant POST_CHANGE clock setup call

[Balaji Selvanathan]

The ufs_qcom_init() function was calling ufs_qcom_setup_clocks() with
POST_CHANGE twice. The first call after setting PA_TXHSADAPTTYPE
correctly enables the device reference clock. The second call after
ufs_qcom_advertise_quirks() is redundant as the clock is already
enabled.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
Changes in v2:
- Newly added in v2
---
 drivers/ufs/ufs-qcom.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c
index ae33f62fbee..f5f5a6eb110 100644
--- a/drivers/ufs/ufs-qcom.c
+++ b/drivers/ufs/ufs-qcom.c
@@ -605,7 +605,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
 		 priv->hw_ver.step);
 
 	ufs_qcom_advertise_quirks(hba);
-	ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
 
 	return 0;
 }

-- 
2.34.1

Re: [PATCH v2 1/7] clk: stub: Sort compatible strings alphabetically

[Sumit Garg]

On Mon, Apr 27, 2026 at 02:56:05PM +0530, Balaji Selvanathan wrote:
> Reorder compatible strings in stub_clk_ids to maintain alphabetical
> order for easier maintenance.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
> Changes in v2:
> - Newly added in v2
> ---
>  drivers/clk/clk-stub.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

> 
> diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
> index 117266ac778..ddcaaa00d91 100644
> --- a/drivers/clk/clk-stub.c
> +++ b/drivers/clk/clk-stub.c
> @@ -50,10 +50,10 @@ static struct clk_ops stub_clk_ops = {
>  
>  static const struct udevice_id stub_clk_ids[] = {
>  	{ .compatible = "qcom,rpmcc" },
> -	{ .compatible = "qcom,sdm670-rpmh-clk" },
> -	{ .compatible = "qcom,sdm845-rpmh-clk" },
>  	{ .compatible = "qcom,sc7180-rpmh-clk" },
>  	{ .compatible = "qcom,sc7280-rpmh-clk" },
> +	{ .compatible = "qcom,sdm670-rpmh-clk" },
> +	{ .compatible = "qcom,sdm845-rpmh-clk" },
>  	{ .compatible = "qcom,sm6350-rpmh-clk" },
>  	{ .compatible = "qcom,sm8150-rpmh-clk" },
>  	{ .compatible = "qcom,sm8250-rpmh-clk" },
> 
> -- 
> 2.34.1
> 

Re: [PATCH v2 2/7] clk: qcom: clk-stub: Add compatibles for QCS615/SA8775P

[Sumit Garg]

On Mon, Apr 27, 2026 at 02:56:06PM +0530, Balaji Selvanathan wrote:
> Add RPMH clock compatible strings for QCS615 and SA8775P
> SoCs to enable clock framework support on these platforms.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
> Changes in v2:
> - Removed sc7280 compatible which was already there
> ---
>  drivers/clk/clk-stub.c | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

> 
> diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
> index ddcaaa00d91..4a6c71016da 100644
> --- a/drivers/clk/clk-stub.c
> +++ b/drivers/clk/clk-stub.c
> @@ -49,7 +49,9 @@ static struct clk_ops stub_clk_ops = {
>  };
>  
>  static const struct udevice_id stub_clk_ids[] = {
> +	{ .compatible = "qcom,qcs615-rpmh-clk" },
>  	{ .compatible = "qcom,rpmcc" },
> +	{ .compatible = "qcom,sa8775p-rpmh-clk" },
>  	{ .compatible = "qcom,sc7180-rpmh-clk" },
>  	{ .compatible = "qcom,sc7280-rpmh-clk" },
>  	{ .compatible = "qcom,sdm670-rpmh-clk" },
> 
> -- 
> 2.34.1
> 

Re: [PATCH v2 6/7] drivers: ufs: qcom: Initialize and enable clocks before hardware access

[Sumit Garg]

On Mon, Apr 27, 2026 at 02:56:10PM +0530, Balaji Selvanathan wrote:
> Move UFS clock initialization and enabling before hardware setup
> to ensure clocks are running when accessing UFS registers.
> 
> Previously, U-Boot depended on earlier bootloader stages to
> initialize UFS clocks. When these bootloaders failed to do so,
> UFS registers became inaccessible, causing initialization to fail.
> This change makes U-Boot initialize and enable UFS clocks early
> in the init sequence, removing the dependency on previous
> bootloaders.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
> Changes in v2:
> - Remove ufs_qcom_init_clks function and move the clock enabling and
>       rate set codes to ufs_qcom_init
> - Add clk_release_bulk if ufs_qcom_enable_clks fails
> ---
>  drivers/ufs/ufs-qcom.c | 53 ++++++++++++++++++++++++++++++++++----------------
>  1 file changed, 36 insertions(+), 17 deletions(-)

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

> 
> diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c
> index dc40ee62daf..ae33f62fbee 100644
> --- a/drivers/ufs/ufs-qcom.c
> +++ b/drivers/ufs/ufs-qcom.c
> @@ -30,6 +30,7 @@
>  #define UFS_CPU_MAX_BANDWIDTH	819200
>  
>  static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable);
> +static u32 ufs_qcom_get_core_clk_unipro_max_freq(struct ufs_hba *hba);
>  
>  static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv)
>  {
> @@ -47,17 +48,6 @@ static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv)
>  	return 0;
>  }
>  
> -static int ufs_qcom_init_clks(struct ufs_qcom_priv *priv)
> -{
> -	int err;
> -	struct udevice *dev = priv->hba->dev;
> -
> -	err = clk_get_bulk(dev, &priv->clks);
> -	if (err)
> -		return err;
> -
> -	return 0;
> -}
>  
>  static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
>  {
> @@ -557,10 +547,45 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable)
>  static int ufs_qcom_init(struct ufs_hba *hba)
>  {
>  	struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
> +	struct udevice *dev = hba->dev;
> +	struct clk clk;
> +	u32 max_freq;
> +	long rate;
>  	int err;
>  
>  	priv->hba = hba;
>  
> +	/* Get maximum frequency for core_clk_unipro from device tree */
> +	max_freq = ufs_qcom_get_core_clk_unipro_max_freq(hba);
> +
> +	/* Get and configure core_clk_unipro */
> +	err = clk_get_by_name(dev, "core_clk_unipro", &clk);
> +	if (err) {
> +		dev_err(dev, "Failed to get core_clk_unipro: %d\n", err);
> +		return err;
> +	}
> +
> +	rate = clk_set_rate(&clk, max_freq);
> +	if (rate < 0) {
> +		dev_err(dev, "Failed to set core_clk_unipro rate to %u Hz: %ld\n",
> +			max_freq, rate);
> +	}
> +
> +	/* Get all clocks */
> +	err = clk_get_bulk(dev, &priv->clks);
> +	if (err) {
> +		dev_err(dev, "clk_get_bulk failed: %d\n", err);
> +		return err;
> +	}
> +
> +	/* Enable clocks */
> +	err = ufs_qcom_enable_clks(priv);
> +	if (err) {
> +		dev_err(dev, "failed to enable clocks: %d\n", err);
> +		clk_release_bulk(&priv->clks);
> +		return err;
> +	}
> +
>  	/* setup clocks */
>  	ufs_qcom_setup_clocks(hba, true, PRE_CHANGE);
>  
> @@ -579,12 +604,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>  		 priv->hw_ver.minor,
>  		 priv->hw_ver.step);
>  
> -	err = ufs_qcom_init_clks(priv);
> -	if (err) {
> -		dev_err(hba->dev, "failed to initialize clocks, err:%d\n", err);
> -		return err;
> -	}
> -
>  	ufs_qcom_advertise_quirks(hba);
>  	ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
>  
> 
> -- 
> 2.34.1
> 

Re: [PATCH v2 7/7] ufs: qcom: Remove redundant POST_CHANGE clock setup call

[Sumit Garg]

On Mon, Apr 27, 2026 at 02:56:11PM +0530, Balaji Selvanathan wrote:
> The ufs_qcom_init() function was calling ufs_qcom_setup_clocks() with
> POST_CHANGE twice. The first call after setting PA_TXHSADAPTTYPE
> correctly enables the device reference clock. The second call after
> ufs_qcom_advertise_quirks() is redundant as the clock is already
> enabled.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
> Changes in v2:
> - Newly added in v2
> ---
>  drivers/ufs/ufs-qcom.c | 1 -
>  1 file changed, 1 deletion(-)
>

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

> diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c
> index ae33f62fbee..f5f5a6eb110 100644
> --- a/drivers/ufs/ufs-qcom.c
> +++ b/drivers/ufs/ufs-qcom.c
> @@ -605,7 +605,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>  		 priv->hw_ver.step);
>  
>  	ufs_qcom_advertise_quirks(hba);
> -	ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
>  
>  	return 0;
>  }
> 
> -- 
> 2.34.1
> 

Re: [PATCH v2 6/7] drivers: ufs: qcom: Initialize and enable clocks before hardware access

[Neha Malcom Francis]

On Mon, 27 Apr 2026 14:56:10 +0530, Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> wrote:
> diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c
> index dc40ee62daf..ae33f62fbee 100644
> --- a/drivers/ufs/ufs-qcom.c
> +++ b/drivers/ufs/ufs-qcom.c
> @@ -557,10 +547,45 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable)
> [ ... skip 20 lines ... ]
> +
> +	rate = clk_set_rate(&clk, max_freq);
> +	if (rate < 0) {
> +		dev_err(dev, "Failed to set core_clk_unipro rate to %u Hz: %ld\n",
> +			max_freq, rate);
> +	}

Was it intentional to proceed with init despite core clock set_rate failure?

-- 
Neha Malcom Francis <n-francis@ti.com>

Re: [PATCH v2 7/7] ufs: qcom: Remove redundant POST_CHANGE clock setup call

[Neha Malcom Francis]

On Mon, 27 Apr 2026 14:56:11 +0530, Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> wrote:
> The ufs_qcom_init() function was calling ufs_qcom_setup_clocks() with
> POST_CHANGE twice. The first call after setting PA_TXHSADAPTTYPE
> correctly enables the device reference clock. The second call after
> ufs_qcom_advertise_quirks() is redundant as the clock is already
> enabled.
> 
> 
> [...]

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>

-- 
Neha Malcom Francis <n-francis@ti.com>

Re: [PATCH v2 6/7] drivers: ufs: qcom: Initialize and enable clocks before hardware access

[Casey Connolly]

On 04/05/2026 13:07, Neha Malcom Francis wrote:
> On Mon, 27 Apr 2026 14:56:10 +0530, Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> wrote:
>> diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c
>> index dc40ee62daf..ae33f62fbee 100644
>> --- a/drivers/ufs/ufs-qcom.c
>> +++ b/drivers/ufs/ufs-qcom.c
>> @@ -557,10 +547,45 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable)
>> [ ... skip 20 lines ... ]
>> +
>> +	rate = clk_set_rate(&clk, max_freq);
>> +	if (rate < 0) {
>> +		dev_err(dev, "Failed to set core_clk_unipro rate to %u Hz: %ld\n",
>> +			max_freq, rate);
>> +	}
> 
> Was it intentional to proceed with init despite core clock set_rate failure?

I think for now it's kept because some platform clock drivers don't
properly support this clock since it's often already configured
properly. If it is required then the error still provides a useful
pointer and the driver will fail later on.

> 

-- 
// Casey (she/her)

Re: [PATCH v2 0/7] Add UFS clock support for Qualcomm SoCs

[Casey Connolly]

On 27/04/2026 11:26, Balaji Selvanathan wrote:
> This series adds UFS clock support for QCS615, SA8775P SoCs and
> enables U-Boot to initialize UFS clocks independently.
> 
> Previously, U-Boot depended on earlier bootloader stages to
> initialize UFS clocks. When these bootloaders failed to do so,
> UFS registers became inaccessible, preventing UFS initialization.
> This series removes that dependency by adding clock infrastructure
> and enabling U-Boot to configure UFS clocks directly.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>

> ---
> Changes in v2:
> - Sort compatibles in drivers/clk/clk-stub.c alphabetically 
> - Remove duplicate sc7280 compatible which was already there
> - Remove ufs_qcom_init_clks function and move the clock enabling and
>   rate set codes to ufs_qcom_init
> - Remove ufs_qcom_setup_clocks POST_CHANGE duplicate call
> - Link to v1: https://lore.kernel.org/u-boot/20260319-ufs_probe_clk-v1-0-08c085d6b15d@oss.qualcomm.com/
> 
> ---
> Balaji Selvanathan (7):
>       clk: stub: Sort compatible strings alphabetically
>       clk: qcom: clk-stub: Add compatibles for QCS615/SA8775P
>       clk: qcom: sa8775p: Add UFS clock support
>       clk: qcom: qcs615: Add UFS clock support
>       clk: qcom: sc7280: Add UFS clock support
>       drivers: ufs: qcom: Initialize and enable clocks before hardware access
>       ufs: qcom: Remove redundant POST_CHANGE clock setup call
> 
>  drivers/clk/clk-stub.c           |  6 ++--
>  drivers/clk/qcom/clock-qcs615.c  | 63 +++++++++++++++++++++++++++++++++++++++-
>  drivers/clk/qcom/clock-sa8775p.c | 63 ++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/qcom/clock-sc7280.c  | 52 +++++++++++++++++++++++++++++++++
>  drivers/ufs/ufs-qcom.c           | 54 ++++++++++++++++++++++------------
>  5 files changed, 217 insertions(+), 21 deletions(-)
> ---
> base-commit: 9f61fd5b80a43ae20ba115e3a2933d47d720ab82
> change-id: 20260427-ufs_clk-49c917afbc6f
> 
> Best regards,

-- 
// Casey (she/her)

Re: [PATCH v2 0/7] Add UFS clock support for Qualcomm SoCs

[Casey Connolly]

On Mon, 27 Apr 2026 14:56:04 +0530, Balaji Selvanathan wrote:
> This series adds UFS clock support for QCS615, SA8775P SoCs and
> enables U-Boot to initialize UFS clocks independently.
> 
> Previously, U-Boot depended on earlier bootloader stages to
> initialize UFS clocks. When these bootloaders failed to do so,
> UFS registers became inaccessible, preventing UFS initialization.
> This series removes that dependency by adding clock infrastructure
> and enabling U-Boot to configure UFS clocks directly.
> 
> [...]

Applied, thanks!

[1/7] clk: stub: Sort compatible strings alphabetically
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/fdc6db475148
[2/7] clk: qcom: clk-stub: Add compatibles for QCS615/SA8775P
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/aa5d2d38194f
[3/7] clk: qcom: sa8775p: Add UFS clock support
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/aef9cdcda59d
[4/7] clk: qcom: qcs615: Add UFS clock support
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/f94e4cfee4aa
[5/7] clk: qcom: sc7280: Add UFS clock support
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/79bc2718d137
[6/7] drivers: ufs: qcom: Initialize and enable clocks before hardware access
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/0f9d0c9620ee
[7/7] ufs: qcom: Remove redundant POST_CHANGE clock setup call
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/c026f721d27f

Best regards,
-- 
// Casey (she/they)

Re: [PATCH v2 0/7] Add UFS clock support for Qualcomm SoCs

[Neha Malcom Francis]

On Mon, 27 Apr 2026 14:56:04 +0530, Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> wrote:
> Add UFS clock support for Qualcomm SoCs
> 
> This series adds UFS clock support for QCS615, SA8775P SoCs and
> enables U-Boot to initialize UFS clocks independently.
> 
> Previously, U-Boot depended on earlier bootloader stages to
> initialize UFS clocks. When these bootloaders failed to do so,
> UFS registers became inaccessible, preventing UFS initialization.
> This series removes that dependency by adding clock infrastructure
> and enabling U-Boot to configure UFS clocks directly.
> 
> [...]

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>

-- 
Neha Malcom Francis <n-francis@ti.com>