From: Nicholas Piggin <npiggin@gmail.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: Joel Stanley <joel@jms.id.au>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
Chao Liu <chao.liu.zevorn@gmail.com>,
Michael Ellerman <mpe@kernel.org>,
Joel Stanley <jms@oss.tenstorrent.com>,
Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>,
Portia Stephens <portias@oss.tenstorrent.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v4 03/13] hw/riscv/boot: Account for discontiguous memory when loading firmware
Date: Tue, 5 May 2026 09:45:24 +1000 [thread overview]
Message-ID: <afkuWiSIaP1Otvom@lima-default> (raw)
In-Reply-To: <CAKmqyKPY0oxFzOXxZG5Mgj9qUdFiNg8wMxnCa5V0f0-Oc_sJBQ@mail.gmail.com>
On Thu, Apr 30, 2026 at 09:34:24AM +1000, Alistair Francis wrote:
> On Sat, Apr 25, 2026 at 11:20 PM Joel Stanley <joel@jms.id.au> wrote:
> >
> > From: Nicholas Piggin <npiggin@gmail.com>
> >
> > This loads firmware into the first (low) memory range,
> > accounting for machines having discontiguous memory regions.
> >
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> > Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> > Signed-off-by: Joel Stanley <joel@jms.id.au>
> > ---
> > v4: Make RISCVBootInfo *info const in riscv_load_firmware
> > v3: Call riscv_boot_info_init before riscv_find_and_load_firmware in
> > sifive_u
> > ---
> > include/hw/riscv/boot.h | 5 ++++-
> > hw/riscv/boot.c | 18 ++++++++++++------
> > hw/riscv/microchip_pfsoc.c | 6 ++++--
> > hw/riscv/opentitan.c | 6 ++++--
> > hw/riscv/shakti_c.c | 6 +++++-
> > hw/riscv/sifive_u.c | 6 ++++--
> > hw/riscv/spike.c | 6 ++++--
> > hw/riscv/virt.c | 7 ++++---
> > hw/riscv/xiangshan_kmh.c | 6 +++++-
> > 9 files changed, 46 insertions(+), 20 deletions(-)
> >
> > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> > index 115e3222174f..b2ef64fb1d14 100644
> > --- a/include/hw/riscv/boot.h
> > +++ b/include/hw/riscv/boot.h
> > @@ -53,13 +53,16 @@ void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,
> > vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,
> > hwaddr firmware_end_addr);
> > hwaddr riscv_find_and_load_firmware(MachineState *machine,
> > + RISCVBootInfo *info,
> > const char *default_machine_firmware,
> > hwaddr *firmware_load_addr,
> > symbol_fn_t sym_cb);
> > const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
> > char *riscv_find_firmware(const char *firmware_filename,
> > const char *default_machine_firmware);
> > -hwaddr riscv_load_firmware(const char *firmware_filename,
> > +hwaddr riscv_load_firmware(MachineState *machine,
> > + const RISCVBootInfo *info,
> > + const char *firmware_filename,
> > hwaddr *firmware_load_addr,
> > symbol_fn_t sym_cb);
> > void riscv_load_kernel(MachineState *machine,
> > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> > index 5c9547429a36..4fbc778263cf 100644
> > --- a/hw/riscv/boot.c
> > +++ b/hw/riscv/boot.c
> > @@ -145,6 +145,7 @@ char *riscv_find_firmware(const char *firmware_filename,
> > }
> >
> > hwaddr riscv_find_and_load_firmware(MachineState *machine,
> > + RISCVBootInfo *info,
> > const char *default_machine_firmware,
> > hwaddr *firmware_load_addr,
> > symbol_fn_t sym_cb)
> > @@ -157,7 +158,8 @@ hwaddr riscv_find_and_load_firmware(MachineState *machine,
> >
> > if (firmware_filename) {
> > /* If not "none" load the firmware */
> > - firmware_end_addr = riscv_load_firmware(firmware_filename,
> > + firmware_end_addr = riscv_load_firmware(machine, info,
> > + firmware_filename,
> > firmware_load_addr, sym_cb);
> > g_free(firmware_filename);
> > }
> > @@ -165,10 +167,13 @@ hwaddr riscv_find_and_load_firmware(MachineState *machine,
> > return firmware_end_addr;
> > }
> >
> > -hwaddr riscv_load_firmware(const char *firmware_filename,
> > +hwaddr riscv_load_firmware(MachineState *machine,
> > + const RISCVBootInfo *info,
> > + const char *firmware_filename,
> > hwaddr *firmware_load_addr,
> > symbol_fn_t sym_cb)
> > {
> > + uint64_t mem_size = info->ram_low_size ?: machine->ram_size;
> > uint64_t firmware_entry, firmware_end;
> > ssize_t firmware_size;
> >
> > @@ -197,7 +202,7 @@ hwaddr riscv_load_firmware(const char *firmware_filename,
> >
> > firmware_size = load_image_targphys_as(firmware_filename,
> > *firmware_load_addr,
> > - current_machine->ram_size, NULL,
> > + mem_size, NULL,
> > NULL);
> >
> > if (firmware_size > 0) {
> > @@ -212,7 +217,7 @@ hwaddr riscv_load_firmware(const char *firmware_filename,
> > static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)
> > {
> > const char *filename = machine->initrd_filename;
> > - uint64_t mem_size = machine->ram_size;
> > + uint64_t mem_size = info->ram_low_size ?: machine->ram_size;
> > void *fdt = machine->fdt;
> > hwaddr start, end;
> > ssize_t size;
> > @@ -258,6 +263,7 @@ void riscv_load_kernel(MachineState *machine,
> > bool load_initrd,
> > symbol_fn_t sym_cb)
> > {
> > + uint64_t mem_size = info->ram_low_size ?: machine->ram_size;
> > const char *kernel_filename = machine->kernel_filename;
> > ssize_t kernel_size;
> > void *fdt = machine->fdt;
> > @@ -289,7 +295,7 @@ void riscv_load_kernel(MachineState *machine,
> > }
> >
> > kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr,
> > - current_machine->ram_size, NULL, NULL);
> > + mem_size, NULL, NULL);
> > if (kernel_size > 0) {
> > info->kernel_size = kernel_size;
> > info->image_low_addr = kernel_start_addr;
> > @@ -385,7 +391,7 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
> > dtb_start = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
> >
> > if (dtb_start_limit && (dtb_start < dtb_start_limit)) {
> > - error_report("No enough memory to place DTB after kernel/initrd");
> > + error_report("Not enough memory to place DTB after kernel/initrd");
> > exit(1);
> > }
> >
> > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> > index 743f31f00578..1d1ddb05a882 100644
> > --- a/hw/riscv/microchip_pfsoc.c
> > +++ b/hw/riscv/microchip_pfsoc.c
> > @@ -618,18 +618,20 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> > firmware_load_addr = RESET_VECTOR;
> > }
> >
> > + riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
>
> We should be able to use the new riscv_boot_info_init_discontig_mem() here
Good catch, something like this.
riscv_boot_info_init_discontig_mem(&boot_info, &s->soc.u_cpus,
memmap[MICROCHIP_PFSOC_DRAM_LO].base,
mem_low_size);
I'll change that.
Thanks,
Nick
next prev parent reply other threads:[~2026-05-04 23:46 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-25 13:17 [PATCH v4 00/13] hw/riscv: Add the Tenstorrent Atlantis machine Joel Stanley
2026-04-25 13:17 ` [PATCH v4 01/13] hw/i2c: Add designware i2c controller Joel Stanley
2026-04-30 3:53 ` Alistair Francis
2026-05-05 6:20 ` Nicholas Piggin
2026-05-05 7:36 ` Philippe Mathieu-Daudé
2026-05-06 5:58 ` Nicholas Piggin
2026-05-06 8:59 ` Philippe Mathieu-Daudé
2026-05-05 7:57 ` Philippe Mathieu-Daudé
2026-05-06 5:53 ` Nicholas Piggin
2026-05-06 8:55 ` Philippe Mathieu-Daudé
2026-04-25 13:17 ` [PATCH v4 02/13] hw/riscv/boot: Describe discontiguous memory in boot_info Joel Stanley
2026-04-25 13:17 ` [PATCH v4 03/13] hw/riscv/boot: Account for discontiguous memory when loading firmware Joel Stanley
2026-04-29 23:34 ` Alistair Francis
2026-05-04 23:45 ` Nicholas Piggin [this message]
2026-04-25 13:17 ` [PATCH v4 04/13] hw/riscv/boot: Provide a simple halting payload Joel Stanley
2026-04-29 23:35 ` Alistair Francis
2026-05-04 23:52 ` Nicholas Piggin
2026-05-05 8:06 ` Philippe Mathieu-Daudé
2026-05-07 1:53 ` Nicholas Piggin
2026-04-25 13:17 ` [PATCH v4 05/13] hw/riscv/virt: Move AIA initialisation to helper file Joel Stanley
2026-04-25 13:17 ` [PATCH v4 06/13] hw/riscv/aia: Provide number of irq sources Joel Stanley
2026-04-25 13:17 ` [PATCH v4 07/13] target/riscv: tt-ascalon: Enable Zkr extension Joel Stanley
2026-04-29 23:36 ` Alistair Francis
2026-05-05 0:06 ` Nicholas Piggin
2026-04-25 13:17 ` [PATCH v4 08/13] target/riscv: tt-ascalon: Enable Svadu by removing Svade Joel Stanley
2026-04-29 23:41 ` Alistair Francis
2026-04-25 13:17 ` [PATCH v4 09/13] hw/riscv: Add Tenstorrent Atlantis machine Joel Stanley
2026-04-29 23:57 ` Alistair Francis
2026-05-05 1:04 ` Nicholas Piggin
2026-05-05 4:34 ` Alistair Francis
2026-05-05 6:00 ` Nicholas Piggin
2026-05-05 7:31 ` Philippe Mathieu-Daudé
2026-05-06 3:14 ` Alistair Francis
2026-05-07 1:50 ` Nicholas Piggin
2026-05-07 2:53 ` Alistair Francis
2026-05-05 2:00 ` Nicholas Piggin
2026-05-05 4:36 ` Alistair Francis
2026-05-05 6:01 ` Nicholas Piggin
2026-04-25 13:17 ` [PATCH v4 10/13] hw/riscv/atlantis: Add PCIe controller Joel Stanley
2026-04-30 0:04 ` Alistair Francis
2026-05-05 1:38 ` Nicholas Piggin
2026-04-25 13:17 ` [PATCH v4 11/13] tests/functional/riscv64: Add tt-atlantis tests Joel Stanley
2026-04-25 13:17 ` [PATCH v4 12/13] hw/riscv/atlantis: Integrate i2c buses Joel Stanley
2026-04-25 13:17 ` [PATCH v4 13/13] hw/riscv/atlantis: Add some i2c peripherals Joel Stanley
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