Re: [PATCH v4 09/13] hw/riscv: Add Tenstorrent Atlantis machine

[Nicholas Piggin <npiggin@gmail.com>]

On Tue, May 05, 2026 at 02:36:23PM +1000, Alistair Francis wrote:
> On Tue, May 5, 2026 at 12:00 PM Nicholas Piggin <npiggin@gmail.com> wrote:
> >
> > On Thu, Apr 30, 2026 at 09:57:34AM +1000, Alistair Francis wrote:
> > > On Sat, Apr 25, 2026 at 11:20 PM Joel Stanley <joel@jms.id.au> wrote:
> >
> > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > index e1942a86eba5..635a380945fd 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -1760,6 +1760,17 @@ F: hw/*/*sifive*.c
> > > >  F: include/hw/*/*sifive*.h
> > > >  F: tests/functional/test_riscv64_sifive_u.py
> > > >
> > > > +Tenstorrent Machines
> > > > +M: Joel Stanley <joel@jms.id.au>
> > > > +R: Nicholas Piggin <npiggin@gmail.com>
> > > > +R: Michael Ellerman <mpe@kernel.org>
> > > > +L: qemu-riscv@nongnu.org
> > > > +S: Supported
> > > > +F: docs/system/riscv/tt_*.rst
> > > > +F: hw/riscv/tt_*.c
> > > > +F: hw/riscv/aia.[ch]
> > >
> > > AIA?
> >
> > Oh it must be because checkpatch complained about patch 5.
> >
> > It is covered by RISC-V TCG CPUs though, so no change needed to
> > MAINTAINERS for AIA AFAIKS?
> 
> If it's already covered then that should be fine. Also, if you are
> covering it, MAINTAINERS should be updated with patch 5 and not here

Agree on both counts. I think it was in the wrong patch, but also
unnecessary. I've just dropped it.

Thanks,
Nick