Re: [PATCH v4 20/31] hw/arm/tegra241-cmdqv: Use mmap'd VINTF page0 as VCMDQ backing

[Nicolin Chen <nicolinc@nvidia.com>]

On Tue, May 05, 2026 at 08:13:40AM -0700, Shameer Kolothum Thodi wrote:
> > From: Nicolin Chen <nicolinc@nvidia.com>
> > On Wed, Apr 15, 2026 at 11:55:41AM +0100, Shameer Kolothum wrote:
> > > The pre-to-post-alloc transition is triggered by the BASE register
> > > write that initiates IOMMU_HW_QUEUE_ALLOC. No cache-to-hardware
> > > synchronisation is needed at transition time. The hardware mandated
> > > init sequence requires BASE to be written first; PROD_INDX, CONS_INDX
> > > and CONFIG.CMDQ_EN are programmed only after BASE and are therefore
> > always post-alloc.
> > >
> > > Any pre-alloc writes to those registers update only the register
> > > cache, which is discarded at the transition.
> > 
> > Is "discard" the correct action?
> > 
> > Guest OS might expect HW (VM) to retain what it writes to those
> > page0 registers?
> 
> As explained above, I reached that conclusion based on spec p.174/175:
> 
> Under "Enabling the Virtual CMDQ" it specifies the init order as below:
> 
> - Program the VIRT_CMDQ_BASE 
> - Init the PROD_INDX/ CONS_INDX to 0 or a consistent value
> - Program the VIRT_CMDQ_CONFIG to enable the CMDQ
> 
> Since we set up the HW QUEUE on BASE write, a spec compliant guest is
> expected to program the Page0 registers as above after that, and we pass
> those writes directly to the VINTF Page0. There are no GERRORN writes
> before HW queue setup either.

I don't think we can make an assumption that guest would follow
what spec suggests.

Could this be a case:
 - Write the PROD_INDX/ CONS_INDX with a consistent value (0xf)
 - Program the VIRT_CMDQ_BASE 
 - Read the PROD_INDX/CONS_INDX, expecting 0xf
 - Write the PROD_INDX/ CONS_INDX with 0x0
 - Program the VIRT_CMDQ_CONFIG to enable the CMDQ
?

Nicolin