Re: [PATCH v3 07/14] target/riscv: Replace TYPE_RISCV_CPU_BASE

[Chao Liu <chao.liu.zevorn@gmail.com>]

On Wed, May 20, 2026 at 03:12:59PM +0800, Anton Johansson via wrote:
> TYPE_RISCV_CPU_BASE is used only to initialize the correct default
> machine for 3 machines. Replace it with a runtime check.
> 
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

> ---
>  include/hw/riscv/machines-qom.h | 12 ++++++++++++
>  target/riscv/cpu.h              |  6 ------
>  hw/riscv/microblaze-v-generic.c |  2 +-
>  hw/riscv/spike.c                |  2 +-
>  hw/riscv/virt.c                 |  2 +-
>  5 files changed, 15 insertions(+), 9 deletions(-)
> 
> diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
> index 3459437d84..8396155373 100644
> --- a/include/hw/riscv/machines-qom.h
> +++ b/include/hw/riscv/machines-qom.h
> @@ -9,7 +9,9 @@
>  #ifndef HW_RISCV_MACHINES_QOM_H
>  #define HW_RISCV_MACHINES_QOM_H
>  
> +#include "qemu/target-info.h"
>  #include "hw/core/boards.h"
> +#include "target/riscv/cpu-qom.h"
>  
>  #define TYPE_TARGET_RISCV32_MACHINE \
>          "target-info-riscv32-machine"
> @@ -43,4 +45,14 @@ extern InterfaceInfo riscv32_64_machine_interfaces[];
>          DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
>                                              riscv32_64_machine_interfaces)
>  
> +/* Default CPU type inferred from target info */
> +static inline const char *riscv_default_cpu_type(void)
> +{
> +    if (target_riscv64()) {
> +        return TYPE_RISCV_CPU_BASE64;
> +    } else {
> +        return TYPE_RISCV_CPU_BASE32;
> +    }
> +}
> +
>  #endif
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fb44f0485d..f521686c43 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -39,12 +39,6 @@ typedef struct CPUArchState CPURISCVState;
>  
>  #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
>  
> -#if defined(TARGET_RISCV32)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
> -#elif defined(TARGET_RISCV64)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
> -#endif
> -
>  /*
>   * b0: Whether a instruction always raise a store AMO or not.
>   */
> diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
> index d33ac39a68..386c5dce9c 100644
> --- a/hw/riscv/microblaze-v-generic.c
> +++ b/hw/riscv/microblaze-v-generic.c
> @@ -183,7 +183,7 @@ static void mb_v_generic_machine_init(MachineClass *mc)
>      mc->init = mb_v_generic_init;
>      mc->min_cpus = 1;
>      mc->max_cpus = 1;
> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +    mc->default_cpu_type = riscv_default_cpu_type();
>      mc->default_cpus = 1;
>  }
>  
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 08ef291b6b..b937cf0fa6 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -343,7 +343,7 @@ static void spike_machine_class_init(ObjectClass *oc, const void *data)
>      mc->init = spike_board_init;
>      mc->max_cpus = SPIKE_CPUS_MAX;
>      mc->is_default = true;
> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +    mc->default_cpu_type = riscv_default_cpu_type();
>      mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
>      mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
>      mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 39caf37c01..e108e29f63 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1933,7 +1933,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
>      mc->desc = "RISC-V VirtIO board";
>      mc->init = virt_machine_init;
>      mc->max_cpus = VIRT_CPUS_MAX;
> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +    mc->default_cpu_type = riscv_default_cpu_type();
>      mc->block_default_type = IF_VIRTIO;
>      mc->no_cdrom = 1;
>      mc->pci_allow_0_address = true;
> 
> -- 
> 2.52.0
> 
>