[PATCH v3 00/14] single-binary: Compile hw/riscv once

[PATCH v3 00/14] single-binary: Compile hw/riscv once

[Anton Johansson via qemu development]

Compiles hw/riscv a single time for both qemu-system-riscv32 and
qemu-system-riscv64 by adopting the TargetInfo API and by moving
machine definitions to generic QOM interfaces. This is the same approach
as taken by Philippe in

    "single-binary: Make hw/arm/ common"
    (20251021205741.57109-1-philmd@linaro.org).

All in all, the number of compilation when building both
riscv[32|64]-softmmu is reduced by 11, and the binary size of
qemu-system-riscv[32|64] is increased by 0.11% and 0.026% respectively
(corresponding to 65k and 14k bytes).

This patchset is based on:

    "single-binary: Make riscv cpu.h target independent"
    (20260520125406.28693-1-anjo@rev.ng).

Branch passing CI can be found here:

  https://gitlab.com/AntonJohansson/qemu/-/pipelines/2215536778

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
Changes in v3:
- Dropped merged prequisite patchsets.
- patch 5/14 "configs/target: Implement per-binary TargetInfo structure
  for riscv": Use new target_info_init() TargetInfo registration.
- patch 7/14 "target/riscv: Replace TYPE_RISCV_CPU_BASE": Rename
  virt_default_cpu_type() -> riscv_default_cpu_type() and define in
  machines-qom.h.
- Dropped patch "[PATCH v2 11/14] target/riscv: Make pmu.h target-agnostic":
  This patch replaced target_ulongs with privilege_mode_t and has been folded
  into the prerequisite patchset introducing the typedef. 
- Added patch 12/14 "target/riscv: Move target_long.h inclusion
  away from cpu.h": Moves target_long.h inclusion to target specific
  header. 
- Link to v2: https://lore.kernel.org/qemu-devel/20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng

Changes in v2:
- Inlined sifive_cpu.h runtime functions and removed header (Philippe);
- Moved IRQ_LOCAL_GUEST_MAX macro to field in RISCVCPUDef (Philippe);
- Added reviewed-bys;
- Link to v1: https://lore.kernel.org/qemu-devel/20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng.

---
Anton Johansson (14):
      hw/riscv: Register generic riscv[32|64] QOM interfaces
      hw/riscv: Add macros and globals for simplifying machine definitions
      hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries
      hw/core: Add riscv[32|64] to "none" machine
      configs/target: Implement per-binary TargetInfo structure for riscv
      target-info: Add target_riscv64()
      target/riscv: Replace TYPE_RISCV_CPU_BASE
      target/riscv: Remove ifdefs in cpu.h
      target/riscv: Replace TARGET_LONG_BITS in header exposed to common code
      target/riscv: Move riscv_pmu_read_ctr() to internal csr.h header
      target/riscv: Stub out kvm functions
      target/riscv: Move target_long.h inclusion away from cpu.h
      hw/riscv: Define SiFive E/U CPUs using runtime conditions
      hw/riscv: Compile once

 include/hw/riscv/machines-qom.h   | 58 +++++++++++++++++++++++++++++++++++++++
 include/hw/riscv/sifive_cpu.h     | 31 ---------------------
 include/hw/riscv/sifive_e.h       |  1 -
 include/hw/riscv/sifive_u.h       |  1 -
 include/qemu/target-info.h        |  7 +++++
 target/riscv/cpu.h                | 44 ++++++-----------------------
 target/riscv/cpu_bits.h           |  2 --
 target/riscv/csr.h                |  3 ++
 target/riscv/internals.h          |  1 +
 target/riscv/pmu.h                |  2 --
 configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++
 configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++
 hw/core/null-machine.c            |  3 ++
 hw/intc/riscv_imsic.c             |  4 ++-
 hw/riscv/boston-aia.c             |  3 +-
 hw/riscv/microblaze-v-generic.c   |  5 ++--
 hw/riscv/microchip_pfsoc.c        |  2 ++
 hw/riscv/opentitan.c              |  2 ++
 hw/riscv/shakti_c.c               |  2 ++
 hw/riscv/sifive_e.c               |  5 +++-
 hw/riscv/sifive_u.c               |  9 ++++--
 hw/riscv/spike.c                  |  4 ++-
 hw/riscv/virt.c                   |  5 +++-
 hw/riscv/xiangshan_kmh.c          |  2 ++
 target-info-qom.c                 |  9 ++++++
 target-info.c                     |  5 ++++
 target/riscv/cpu.c                | 14 ++++++++--
 target/riscv/kvm/kvm-stub.c       | 23 ++++++++++++++++
 target/riscv/machine.c            | 17 ++++++++++++
 target/riscv/pmu.c                |  1 +
 configs/targets/meson.build       |  1 +
 hw/riscv/meson.build              | 36 ++++++++++++------------
 target/riscv/kvm/meson.build      |  1 +
 33 files changed, 254 insertions(+), 101 deletions(-)

[PATCH v3 01/14] hw/riscv: Register generic riscv[32|64] QOM interfaces

[Anton Johansson via qemu development]

Defines generic 32- and 64-bit riscv machine interfaces for machines to
implement.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 include/hw/riscv/machines-qom.h | 20 ++++++++++++++++++++
 target-info-qom.c               |  9 +++++++++
 2 files changed, 29 insertions(+)

diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
new file mode 100644
index 0000000000..69fcf61fd7
--- /dev/null
+++ b/include/hw/riscv/machines-qom.h
@@ -0,0 +1,20 @@
+/*
+ * QOM type definitions for riscv32 / riscv64 machines
+ *
+ *  Copyright (c) rev.ng Labs Srl.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_RISCV_MACHINES_QOM_H
+#define HW_RISCV_MACHINES_QOM_H
+
+#include "hw/core/boards.h"
+
+#define TYPE_TARGET_RISCV32_MACHINE \
+        "target-info-riscv32-machine"
+
+#define TYPE_TARGET_RISCV64_MACHINE \
+        "target-info-riscv64-machine"
+
+#endif
diff --git a/target-info-qom.c b/target-info-qom.c
index b48714cc77..7958a5cc68 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -13,6 +13,7 @@
 #include "qemu/target-info-init.h"
 #include "qemu/target-info-qom.h"
 #include "hw/arm/machines-qom.h"
+#include "hw/riscv/machines-qom.h"
 
 static const TypeInfo target_info_types[] = {
     {
@@ -23,6 +24,14 @@ static const TypeInfo target_info_types[] = {
         .name           = TYPE_TARGET_AARCH64_MACHINE,
         .parent         = TYPE_INTERFACE,
     },
+    {
+        .name           = TYPE_TARGET_RISCV32_MACHINE,
+        .parent         = TYPE_INTERFACE,
+    },
+    {
+        .name           = TYPE_TARGET_RISCV64_MACHINE,
+        .parent         = TYPE_INTERFACE,
+    },
 };
 
 DEFINE_TYPES(target_info_types)

-- 
2.52.0

[PATCH v3 02/14] hw/riscv: Add macros and globals for simplifying machine definitions

[Anton Johansson via qemu development]

Adds macros and global interfaces for defining machines available only
in qemu-system-riscv32, qemu-system-riscv64, or both.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 include/hw/riscv/machines-qom.h | 26 ++++++++++++++++++++++++++
 target/riscv/machine.c          | 17 +++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index 69fcf61fd7..3459437d84 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -17,4 +17,30 @@
 #define TYPE_TARGET_RISCV64_MACHINE \
         "target-info-riscv64-machine"
 
+/*
+ * Interfaces specifying whether a given QOM object is available in
+ * qemu-system-riscv32, qemu-system-riscv64, or both.
+ */
+
+extern InterfaceInfo riscv32_machine_interfaces[];
+extern InterfaceInfo riscv64_machine_interfaces[];
+extern InterfaceInfo riscv32_64_machine_interfaces[];
+
+/*
+ * Helper macros for defining machines available in qemu-system-riscv32,
+ * qemu-system-riscv64, or both.
+ */
+
+#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \
+        DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
+                                            riscv32_machine_interfaces)
+
+#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \
+        DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
+                                            riscv64_machine_interfaces)
+
+#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \
+        DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
+                                            riscv32_64_machine_interfaces)
+
 #endif
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 13eb292c4a..3d2e3968fd 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -23,6 +23,7 @@
 #include "migration/cpu.h"
 #include "exec/icount.h"
 #include "target/riscv/debug.h"
+#include "hw/riscv/machines-qom.h"
 
 static bool pmp_needed(void *opaque)
 {
@@ -503,3 +504,19 @@ const VMStateDescription vmstate_riscv_cpu = {
         NULL
     }
 };
+
+InterfaceInfo riscv32_machine_interfaces[] = {
+    { TYPE_TARGET_RISCV32_MACHINE },
+    { }
+};
+
+InterfaceInfo riscv64_machine_interfaces[] = {
+    { TYPE_TARGET_RISCV64_MACHINE },
+    { }
+};
+
+InterfaceInfo riscv32_64_machine_interfaces[] = {
+    { TYPE_TARGET_RISCV32_MACHINE },
+    { TYPE_TARGET_RISCV64_MACHINE },
+    { }
+};

-- 
2.52.0

[PATCH v3 03/14] hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries

[Anton Johansson via qemu development]

Register machines able to run in qemu-system-riscv32,
qemu-system-riscv64, or both.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 hw/riscv/boston-aia.c           | 3 ++-
 hw/riscv/microblaze-v-generic.c | 3 ++-
 hw/riscv/microchip_pfsoc.c      | 2 ++
 hw/riscv/opentitan.c            | 2 ++
 hw/riscv/shakti_c.c             | 2 ++
 hw/riscv/sifive_e.c             | 2 ++
 hw/riscv/sifive_u.c             | 2 ++
 hw/riscv/spike.c                | 2 ++
 hw/riscv/virt.c                 | 3 +++
 hw/riscv/xiangshan_kmh.c        | 2 ++
 10 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c
index b90da096ea..965d0f5699 100644
--- a/hw/riscv/boston-aia.c
+++ b/hw/riscv/boston-aia.c
@@ -18,6 +18,7 @@
 #include "hw/ide/ahci-pci.h"
 #include "hw/core/loader.h"
 #include "hw/riscv/cps.h"
+#include "hw/riscv/machines-qom.h"
 #include "hw/pci-host/xilinx-pcie.h"
 #include "hw/core/qdev-properties.h"
 #include "qapi/error.h"
@@ -473,4 +474,4 @@ static void boston_mach_class_init(MachineClass *mc)
     mc->default_cpu_type = TYPE_RISCV_CPU_MIPS_P8700;
 }
 
-DEFINE_MACHINE("boston-aia", boston_mach_class_init)
+DEFINE_MACHINE_RISCV64("boston-aia", boston_mach_class_init)
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index b0494b1ac5..d33ac39a68 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -25,6 +25,7 @@
 #include "system/address-spaces.h"
 #include "hw/char/xilinx_uartlite.h"
 #include "hw/misc/unimp.h"
+#include "hw/riscv/machines-qom.h"
 
 #define LMB_BRAM_SIZE (128 * KiB)
 #define MEMORY_BASEADDR 0x80000000
@@ -186,4 +187,4 @@ static void mb_v_generic_machine_init(MachineClass *mc)
     mc->default_cpus = 1;
 }
 
-DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init)
+DEFINE_MACHINE_RISCV32_64("amd-microblaze-v-generic", mb_v_generic_machine_init)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 743f31f005..5e48a29708 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -49,6 +49,7 @@
 #include "hw/misc/unimp.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/machines-qom.h"
 #include "hw/riscv/microchip_pfsoc.h"
 #include "hw/intc/riscv_aclint.h"
 #include "hw/intc/sifive_plic.h"
@@ -751,6 +752,7 @@ static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
     .class_init = microchip_icicle_kit_machine_class_init,
     .instance_init = microchip_icicle_kit_machine_instance_init,
     .instance_size = sizeof(MicrochipIcicleKitState),
+    .interfaces = riscv64_machine_interfaces,
 };
 
 static void microchip_icicle_kit_machine_init_register_types(void)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 309125e854..c8b2f028f2 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -26,6 +26,7 @@
 #include "hw/core/boards.h"
 #include "hw/misc/unimp.h"
 #include "hw/riscv/boot.h"
+#include "hw/riscv/machines-qom.h"
 #include "qemu/units.h"
 #include "system/system.h"
 #include "system/address-spaces.h"
@@ -335,6 +336,7 @@ static const TypeInfo open_titan_types[] = {
         .parent         = TYPE_MACHINE,
         .instance_size  = sizeof(OpenTitanState),
         .class_init     = opentitan_machine_class_init,
+        .interfaces     = riscv32_machine_interfaces,
     }
 };
 
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 49a39b3021..64207c8d00 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -19,6 +19,7 @@
 #include "qemu/osdep.h"
 #include "hw/core/boards.h"
 #include "hw/riscv/shakti_c.h"
+#include "hw/riscv/machines-qom.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "hw/intc/sifive_plic.h"
@@ -92,6 +93,7 @@ static const TypeInfo shakti_c_machine_type_info = {
     .class_init = shakti_c_machine_class_init,
     .instance_init = shakti_c_machine_instance_init,
     .instance_size = sizeof(ShaktiCMachineState),
+    .interfaces = riscv64_machine_interfaces,
 };
 
 static void shakti_c_machine_type_info_register(void)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 1acfea4966..71925583bd 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -40,6 +40,7 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_e.h"
 #include "hw/riscv/boot.h"
+#include "hw/riscv/machines-qom.h"
 #include "hw/char/sifive_uart.h"
 #include "hw/intc/riscv_aclint.h"
 #include "hw/intc/sifive_plic.h"
@@ -167,6 +168,7 @@ static const TypeInfo sifive_e_machine_typeinfo = {
     .class_init = sifive_e_machine_class_init,
     .instance_init = sifive_e_machine_instance_init,
     .instance_size = sizeof(SiFiveEState),
+    .interfaces = riscv32_64_machine_interfaces,
 };
 
 static void sifive_e_machine_init_register_types(void)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7ec67b2565..6a637e3b86 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -51,6 +51,7 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
+#include "hw/riscv/machines-qom.h"
 #include "hw/char/sifive_uart.h"
 #include "hw/intc/riscv_aclint.h"
 #include "hw/intc/sifive_plic.h"
@@ -742,6 +743,7 @@ static const TypeInfo sifive_u_machine_typeinfo = {
     .class_init = sifive_u_machine_class_init,
     .instance_init = sifive_u_machine_instance_init,
     .instance_size = sizeof(SiFiveUState),
+    .interfaces = riscv32_64_machine_interfaces,
 };
 
 static void sifive_u_machine_init_register_types(void)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 35c696f891..08ef291b6b 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -33,6 +33,7 @@
 #include "hw/riscv/spike.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "hw/riscv/machines-qom.h"
 #include "hw/char/riscv_htif.h"
 #include "hw/intc/riscv_aclint.h"
 #include "chardev/char.h"
@@ -366,6 +367,7 @@ static const TypeInfo spike_machine_typeinfo = {
     .class_init = spike_machine_class_init,
     .instance_init = spike_machine_instance_init,
     .instance_size = sizeof(SpikeState),
+    .interfaces = riscv32_64_machine_interfaces,
 };
 
 static void spike_machine_init_register_types(void)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 315049bc86..39caf37c01 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -36,6 +36,7 @@
 #include "hw/riscv/riscv-iommu-bits.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
+#include "hw/riscv/machines-qom.h"
 #include "hw/riscv/numa.h"
 #include "kvm/kvm_riscv.h"
 #include "hw/firmware/smbios.h"
@@ -2001,6 +2002,8 @@ static const TypeInfo virt_machine_typeinfo = {
     .instance_size = sizeof(RISCVVirtState),
     .interfaces = (const InterfaceInfo[]) {
          { TYPE_HOTPLUG_HANDLER },
+         { TYPE_TARGET_RISCV32_MACHINE },
+         { TYPE_TARGET_RISCV64_MACHINE },
          { }
     },
 };
diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
index 436e51c1c5..76417ba7ab 100644
--- a/hw/riscv/xiangshan_kmh.c
+++ b/hw/riscv/xiangshan_kmh.c
@@ -41,6 +41,7 @@
 #include "hw/riscv/boot.h"
 #include "hw/riscv/xiangshan_kmh.h"
 #include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/machines-qom.h"
 #include "system/system.h"
 
 static const MemMapEntry xiangshan_kmh_memmap[] = {
@@ -211,6 +212,7 @@ static const TypeInfo xiangshan_kmh_machine_info = {
     .parent = TYPE_MACHINE,
     .instance_size = sizeof(XiangshanKmhState),
     .class_init = xiangshan_kmh_machine_class_init,
+    .interfaces = riscv64_machine_interfaces,
 };
 
 static void xiangshan_kmh_machine_register_types(void)

-- 
2.52.0

[PATCH v3 04/14] hw/core: Add riscv[32|64] to "none" machine

[Anton Johansson via qemu development]

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 hw/core/null-machine.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index c52b022d3a..f132a7b89b 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -17,6 +17,7 @@
 #include "system/address-spaces.h"
 #include "hw/core/cpu.h"
 #include "hw/arm/machines-qom.h"
+#include "hw/riscv/machines-qom.h"
 
 static void machine_none_init(MachineState *mch)
 {
@@ -59,4 +60,6 @@ static void machine_none_machine_init(MachineClass *mc)
 DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init,
                                { TYPE_TARGET_AARCH64_MACHINE },
                                { TYPE_TARGET_ARM_MACHINE },
+                               { TYPE_TARGET_RISCV32_MACHINE },
+                               { TYPE_TARGET_RISCV64_MACHINE },
                                { })

-- 
2.52.0

[PATCH v3 05/14] configs/target: Implement per-binary TargetInfo structure for riscv

[Anton Johansson via qemu development]

Defines TargetInfo for 32- and 64-bit riscv binaries.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++++++++++
 configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++++++++++
 configs/targets/meson.build       |  1 +
 3 files changed, 53 insertions(+)

diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c
new file mode 100644
index 0000000000..752c813077
--- /dev/null
+++ b/configs/targets/riscv32-softmmu.c
@@ -0,0 +1,26 @@
+/*
+ * QEMU binary/target API (qemu-system-riscv32)
+ *
+ *  Copyright (c) rev.ng Labs Srl.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/target-info-impl.h"
+#include "qemu/target-info-init.h"
+#include "hw/riscv/machines-qom.h"
+#include "target/riscv/cpu-qom.h"
+#include "target/riscv/cpu-param.h"
+
+static const TargetInfo target_info_riscv32_system = {
+    .target_name = "riscv32",
+    .target_arch = SYS_EMU_TARGET_RISCV32,
+    .long_bits = 32,
+    .cpu_type = TYPE_RISCV_CPU,
+    .machine_typename = TYPE_TARGET_RISCV32_MACHINE,
+    .endianness = ENDIAN_MODE_LITTLE,
+    .page_bits_init = TARGET_PAGE_BITS,
+};
+
+target_info_init(target_info_riscv32_system)
diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c
new file mode 100644
index 0000000000..5150f0fe9d
--- /dev/null
+++ b/configs/targets/riscv64-softmmu.c
@@ -0,0 +1,26 @@
+/*
+ * QEMU binary/target API (qemu-system-riscv64)
+ *
+ *  Copyright (c) rev.ng Labs Srl.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/target-info-impl.h"
+#include "qemu/target-info-init.h"
+#include "hw/riscv/machines-qom.h"
+#include "target/riscv/cpu-qom.h"
+#include "target/riscv/cpu-param.h"
+
+static const TargetInfo target_info_riscv64_system = {
+    .target_name = "riscv64",
+    .target_arch = SYS_EMU_TARGET_RISCV64,
+    .long_bits = 64,
+    .cpu_type = TYPE_RISCV_CPU,
+    .machine_typename = TYPE_TARGET_RISCV64_MACHINE,
+    .endianness = ENDIAN_MODE_LITTLE,
+    .page_bits_init = TARGET_PAGE_BITS,
+};
+
+target_info_init(target_info_riscv64_system)
diff --git a/configs/targets/meson.build b/configs/targets/meson.build
index cca2514eb5..2ab4d27eaf 100644
--- a/configs/targets/meson.build
+++ b/configs/targets/meson.build
@@ -1,5 +1,6 @@
 foreach target : [
       'arm-softmmu', 'aarch64-softmmu',
+      'riscv32-softmmu', 'riscv64-softmmu'
   ]
   config_target_info += {target : files(target + '.c')}
 endforeach

-- 
2.52.0

[PATCH v3 06/14] target-info: Add target_riscv64()

[Anton Johansson via qemu development]

Adds a helper function to tell if the binary is targeting riscv64 or
not.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 include/qemu/target-info.h | 7 +++++++
 target-info.c              | 5 +++++
 2 files changed, 12 insertions(+)

diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 23c997de54..6c5b714288 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -99,4 +99,11 @@ bool target_ppc64(void);
  */
 bool target_s390x(void);
 
+/**
+ * target_riscv64:
+ *
+ * Returns whether the target architecture is riscv64
+ */
+bool target_riscv64(void);
+
 #endif
diff --git a/target-info.c b/target-info.c
index 28c458fc7a..04c69c41f8 100644
--- a/target-info.c
+++ b/target-info.c
@@ -93,3 +93,8 @@ bool target_s390x(void)
 {
     return target_arch() == SYS_EMU_TARGET_S390X;
 }
+
+bool target_riscv64(void)
+{
+    return target_arch() == SYS_EMU_TARGET_RISCV64;
+}

-- 
2.52.0

[PATCH v3 07/14] target/riscv: Replace TYPE_RISCV_CPU_BASE

[Anton Johansson via qemu development]

TYPE_RISCV_CPU_BASE is used only to initialize the correct default
machine for 3 machines. Replace it with a runtime check.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 include/hw/riscv/machines-qom.h | 12 ++++++++++++
 target/riscv/cpu.h              |  6 ------
 hw/riscv/microblaze-v-generic.c |  2 +-
 hw/riscv/spike.c                |  2 +-
 hw/riscv/virt.c                 |  2 +-
 5 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index 3459437d84..8396155373 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -9,7 +9,9 @@
 #ifndef HW_RISCV_MACHINES_QOM_H
 #define HW_RISCV_MACHINES_QOM_H
 
+#include "qemu/target-info.h"
 #include "hw/core/boards.h"
+#include "target/riscv/cpu-qom.h"
 
 #define TYPE_TARGET_RISCV32_MACHINE \
         "target-info-riscv32-machine"
@@ -43,4 +45,14 @@ extern InterfaceInfo riscv32_64_machine_interfaces[];
         DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
                                             riscv32_64_machine_interfaces)
 
+/* Default CPU type inferred from target info */
+static inline const char *riscv_default_cpu_type(void)
+{
+    if (target_riscv64()) {
+        return TYPE_RISCV_CPU_BASE64;
+    } else {
+        return TYPE_RISCV_CPU_BASE32;
+    }
+}
+
 #endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fb44f0485d..f521686c43 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -39,12 +39,6 @@ typedef struct CPUArchState CPURISCVState;
 
 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
 
-#if defined(TARGET_RISCV32)
-# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
-#endif
-
 /*
  * b0: Whether a instruction always raise a store AMO or not.
  */
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index d33ac39a68..386c5dce9c 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -183,7 +183,7 @@ static void mb_v_generic_machine_init(MachineClass *mc)
     mc->init = mb_v_generic_init;
     mc->min_cpus = 1;
     mc->max_cpus = 1;
-    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+    mc->default_cpu_type = riscv_default_cpu_type();
     mc->default_cpus = 1;
 }
 
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 08ef291b6b..b937cf0fa6 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -343,7 +343,7 @@ static void spike_machine_class_init(ObjectClass *oc, const void *data)
     mc->init = spike_board_init;
     mc->max_cpus = SPIKE_CPUS_MAX;
     mc->is_default = true;
-    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+    mc->default_cpu_type = riscv_default_cpu_type();
     mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 39caf37c01..e108e29f63 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1933,7 +1933,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
     mc->desc = "RISC-V VirtIO board";
     mc->init = virt_machine_init;
     mc->max_cpus = VIRT_CPUS_MAX;
-    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+    mc->default_cpu_type = riscv_default_cpu_type();
     mc->block_default_type = IF_VIRTIO;
     mc->no_cdrom = 1;
     mc->pci_allow_0_address = true;

-- 
2.52.0

[PATCH v3 08/14] target/riscv: Remove ifdefs in cpu.h

[Anton Johansson via qemu development]

KVM fields of CPURISCVState are now always exposed as CONFIG_KVM cannot
be used in common code.

riscv_cpu_mxl() is changed to return CPURISCVState::misa_mxl
unconditionally, as use of target_riscv64() would result in an extra
load and compare with TargetInfo::target_arch.  We might as well just
perform a single load.  Likewise, for cpu_recompute_xl(),
cpu_address_xl(), and riscv_cpu_sxl(), we opt for returning the
corresponding CPURISCVState field with ifdefs for system mode adding
extra conditions.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 target/riscv/cpu.h | 36 ++++++++----------------------------
 1 file changed, 8 insertions(+), 28 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f521686c43..5dc76f07bf 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -493,14 +493,12 @@ struct CPUArchState {
     hwaddr kernel_addr;
     hwaddr fdt_addr;
 
-#ifdef CONFIG_KVM
     /* kvm timer */
     bool kvm_timer_dirty;
     uint64_t kvm_timer_time;
     uint64_t kvm_timer_compare;
     uint64_t kvm_timer_state;
     uint64_t kvm_timer_frequency;
-#endif /* CONFIG_KVM */
 
     /* RNMI */
     uint64_t mnscratch;
@@ -706,14 +704,10 @@ FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)
 FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32)
 FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1)
 
-#ifdef TARGET_RISCV32
-#define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
-#else
 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 {
     return env->misa_mxl;
 }
-#endif
 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 
 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
@@ -757,9 +751,6 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mode)
 }
 #endif
 
-#if defined(TARGET_RISCV32)
-#define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
-#else
 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
 {
 #if !defined(CONFIG_USER_ONLY)
@@ -768,43 +759,32 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
     return env->misa_mxl;
 #endif
 }
-#endif
 
-#if defined(TARGET_RISCV32)
-#define cpu_address_xl(env)  ((void)(env), MXL_RV32)
-#else
 static inline RISCVMXL cpu_address_xl(CPURISCVState *env)
 {
-#ifdef CONFIG_USER_ONLY
-    return env->xl;
-#else
-    privilege_mode_t mode = cpu_address_mode(env);
-
-    return cpu_get_xl(env, mode);
+#ifndef CONFIG_USER_ONLY
+    if (target_riscv64()) {
+        privilege_mode_t mode = cpu_address_mode(env);
+        return cpu_get_xl(env, mode);
+    }
 #endif
+    return env->xl;
 }
-#endif
 
 static inline uint16_t riscv_cpu_xlen(CPURISCVState *env)
 {
     return 16 << env->xl;
 }
 
-#ifdef TARGET_RISCV32
-#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
-#else
 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
 {
-#ifdef CONFIG_USER_ONLY
-    return env->misa_mxl;
-#else
+#ifndef CONFIG_USER_ONLY
     if (env->misa_mxl != MXL_RV32) {
         return get_field(env->mstatus, MSTATUS64_SXL);
     }
 #endif
-    return MXL_RV32;
+    return env->misa_mxl;
 }
-#endif
 
 /*
  * Returns the current effective privilege mode.

-- 
2.52.0

[PATCH v3 09/14] target/riscv: Replace TARGET_LONG_BITS in header exposed to common code

[Anton Johansson via qemu development]

IRQ_LOCAL_GUEST_MAX depends on TARGET_LONG_BITS and is used in
hw/intc/riscv_imsic.c.  The macro is replaced by a field in RISCVCPUDef
initialized in riscv_cpu_class_base_init().

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 target/riscv/cpu.h      |  1 +
 target/riscv/cpu_bits.h |  2 --
 hw/intc/riscv_imsic.c   |  4 +++-
 target/riscv/cpu.c      | 14 ++++++++++++--
 4 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5dc76f07bf..78b4f47d2d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -559,6 +559,7 @@ typedef struct RISCVCPUDef {
     int32_t vext_spec;
     RISCVCPUConfig cfg;
     bool bare;
+    uint8_t irq_local_guest_max;
     const RISCVCSR *custom_csrs;
 } RISCVCPUDef;
 
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index b62dd82fe7..13e052bce2 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -809,8 +809,6 @@ typedef enum RISCVException {
 #define IRQ_S_GEXT                         12
 #define IRQ_PMU_OVF                        13
 #define IRQ_LOCAL_MAX                      64
-/* -1 is due to bit zero of hgeip and hgeie being ROZ. */
-#define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)
 
 /* RNMI causes */
 #define RNMI_MAX                           16
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index 3ce9f146c0..d4f57549b1 100644
--- a/hw/intc/riscv_imsic.c
+++ b/hw/intc/riscv_imsic.c
@@ -453,13 +453,15 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
 {
     DeviceState *dev = qdev_new(TYPE_RISCV_IMSIC);
     CPUState *cpu = cpu_by_arch_id(hartid);
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(RISCV_CPU(cpu));
     uint32_t i;
 
     assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1)));
     if (mmode) {
         assert(num_pages == 1);
     } else {
-        assert(num_pages >= 1 && num_pages <= (IRQ_LOCAL_GUEST_MAX + 1));
+        assert(num_pages >= 1 &&
+               num_pages <= (mcc->def->irq_local_guest_max + 1));
     }
     assert(IMSIC_MIN_ID <= num_ids);
     assert(num_ids <= IMSIC_MAX_ID);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 36f9570f2d..08445cb1d5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1021,6 +1021,7 @@ void riscv_add_satp_mode_properties(Object *obj)
 
 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
 {
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(opaque);
     RISCVCPU *cpu = RISCV_CPU(opaque);
     CPURISCVState *env = &cpu->env;
 
@@ -1055,7 +1056,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
         default:
             g_assert_not_reached();
         }
-    } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
+    } else if (irq < (IRQ_LOCAL_MAX + mcc->def->irq_local_guest_max)) {
         /* Require H-extension for handling guest local interrupts */
         if (!riscv_has_ext(env, RVH)) {
             g_assert_not_reached();
@@ -1102,7 +1103,7 @@ static void riscv_cpu_init(Object *obj)
 
 #ifndef CONFIG_USER_ONLY
     qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
-                      IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
+                      IRQ_LOCAL_MAX + mcc->def->irq_local_guest_max);
     qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi,
                             "riscv.cpu.rnmi", RNMI_MAX);
 #endif /* CONFIG_USER_ONLY */
@@ -2818,6 +2819,15 @@ static void riscv_cpu_class_base_init(ObjectClass *c, const void *data)
         mcc->def = g_new0(RISCVCPUDef, 1);
     }
 
+    /*
+     * RISCVCPUDef::irq_local_guest_max is initialized to
+     * `target_long_bits()-1` due to bit zero of hgeip and hgeie
+     * being ROZ.
+     *
+     * This value does not vary between CPU types.
+     */
+    mcc->def->irq_local_guest_max = target_long_bits() - 1;
+
     if (data) {
         const RISCVCPUDef *def = data;
         mcc->def->bare |= def->bare;

-- 
2.52.0

[PATCH v3 10/14] target/riscv: Move riscv_pmu_read_ctr() to internal csr.h header

[Anton Johansson via qemu development]

The function depends on target_ulong and is via the pmu.h header exposed
to hw/riscv, this function is only used internally in pmu.c and csr.c,
so move it to the internal csr.h header.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 target/riscv/csr.h | 3 +++
 target/riscv/pmu.h | 2 --
 target/riscv/pmu.c | 1 +
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.h b/target/riscv/csr.h
index c791260f83..0454898bb7 100644
--- a/target/riscv/csr.h
+++ b/target/riscv/csr.h
@@ -99,4 +99,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
                        target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 
+/* PMU CSRs */
+RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
+                                  bool upper_half, uint32_t ctr_idx);
 #endif /* RISCV_CSR_H */
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
index b4f1e469a2..273d8f3f94 100644
--- a/target/riscv/pmu.h
+++ b/target/riscv/pmu.h
@@ -36,7 +36,5 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
                           uint32_t ctr_idx);
 void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, privilege_mode_t newpriv,
                                  bool new_virt);
-RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
-                                  bool upper_half, uint32_t ctr_idx);
 
 #endif /* RISCV_PMU_H */
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 3444400bd2..4b7be6164e 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -22,6 +22,7 @@
 #include "qemu/timer.h"
 #include "cpu.h"
 #include "pmu.h"
+#include "target/riscv/csr.h"
 #include "exec/icount.h"
 #include "system/device_tree.h"
 

-- 
2.52.0

[PATCH v3 11/14] target/riscv: Stub out kvm functions

[Anton Johansson via qemu development]

Functions used externally by hw/riscv are stubbed out for non-kvm
configurations, allowing a single compilation of hw/riscv.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 target/riscv/kvm/kvm-stub.c  | 23 +++++++++++++++++++++++
 target/riscv/kvm/meson.build |  1 +
 2 files changed, 24 insertions(+)

diff --git a/target/riscv/kvm/kvm-stub.c b/target/riscv/kvm/kvm-stub.c
new file mode 100644
index 0000000000..64e39c96d8
--- /dev/null
+++ b/target/riscv/kvm/kvm-stub.c
@@ -0,0 +1,23 @@
+/*
+ * QEMU RISCV specific KVM stubs
+ *
+ *  Copyright (c) rev.ng Labs Srl.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "target/riscv/kvm/kvm_riscv.h"
+
+void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+                          uint64_t aia_irq_num, uint64_t aia_msi_num,
+                          uint64_t aplic_base, uint64_t imsic_base,
+                          uint64_t guest_num)
+{
+    g_assert_not_reached();
+}
+
+uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu)
+{
+    g_assert_not_reached();
+}
diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build
index 7e92415091..d3f395f431 100644
--- a/target/riscv/kvm/meson.build
+++ b/target/riscv/kvm/meson.build
@@ -1 +1,2 @@
+riscv_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
 riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c'))

-- 
2.52.0

[PATCH v3 12/14] target/riscv: Move target_long.h inclusion away from cpu.h

[Anton Johansson via qemu development]

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 target/riscv/cpu.h       | 1 -
 target/riscv/internals.h | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 78b4f47d2d..0c96bb73da 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -26,7 +26,6 @@
 #include "exec/cpu-common.h"
 #include "exec/cpu-interrupt.h"
 #include "exec/gdbstub.h"
-#include "exec/target_long.h"
 #include "qemu/cpu-float.h"
 #include "qom/object.h"
 #include "qemu/int128.h"
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index e143a86f97..f2644eb3b6 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -20,6 +20,7 @@
 #define RISCV_CPU_INTERNALS_H
 
 #include "exec/cpu-common.h"
+#include "exec/target_long.h"
 #include "hw/core/registerfields.h"
 #include "fpu/softfloat-types.h"
 #include "target/riscv/cpu_bits.h"

-- 
2.52.0

[PATCH v3 13/14] hw/riscv: Define SiFive E/U CPUs using runtime conditions

[Anton Johansson via qemu development]

Macros are removed and replaced with inlined ternary statements.  The
now empty sifive_cpu.h header is then removed.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 include/hw/riscv/sifive_cpu.h | 31 -------------------------------
 include/hw/riscv/sifive_e.h   |  1 -
 include/hw/riscv/sifive_u.h   |  1 -
 hw/riscv/sifive_e.c           |  3 ++-
 hw/riscv/sifive_u.c           |  7 +++++--
 5 files changed, 7 insertions(+), 36 deletions(-)

diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
deleted file mode 100644
index 136799633a..0000000000
--- a/include/hw/riscv/sifive_cpu.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * SiFive CPU types
- *
- * Copyright (c) 2017 SiFive, Inc.
- * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_CPU_H
-#define HW_SIFIVE_CPU_H
-
-#if defined(TARGET_RISCV32)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
-#endif
-
-#endif /* HW_SIFIVE_CPU_H */
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 4cf902ebc0..0f0d407d5d 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -20,7 +20,6 @@
 #define HW_SIFIVE_E_H
 
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_cpu.h"
 #include "hw/gpio/sifive_gpio.h"
 #include "hw/misc/sifive_e_aon.h"
 #include "hw/core/boards.h"
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index e4c9860d50..bfaaf254af 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -24,7 +24,6 @@
 #include "hw/dma/sifive_pdma.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_cpu.h"
 #include "hw/gpio/sifive_gpio.h"
 #include "hw/misc/sifive_u_otp.h"
 #include "hw/misc/sifive_u_prci.h"
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 71925583bd..76505fdc4d 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -151,7 +151,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc, const void *data)
     mc->desc = "RISC-V Board compatible with SiFive E SDK";
     mc->init = sifive_e_machine_init;
     mc->max_cpus = 1;
-    mc->default_cpu_type = SIFIVE_E_CPU;
+    mc->default_cpu_type = (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_E51
+                                              : TYPE_RISCV_CPU_SIFIVE_E31;
     mc->default_ram_id = "riscv.sifive.e.ram";
     mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
 
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6a637e3b86..b1f5bad8aa 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -723,7 +723,8 @@ static void sifive_u_machine_class_init(ObjectClass *oc, const void *data)
     mc->init = sifive_u_machine_init;
     mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
-    mc->default_cpu_type = SIFIVE_U_CPU;
+    mc->default_cpu_type = (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_U54
+                                              : TYPE_RISCV_CPU_SIFIVE_U34;
     mc->default_cpus = mc->min_cpus;
     mc->default_ram_id = "riscv.sifive.u.ram";
     mc->auto_create_sdcard = true;
@@ -756,6 +757,8 @@ type_init(sifive_u_machine_init_register_types)
 static void sifive_u_soc_instance_init(Object *obj)
 {
     SiFiveUSoCState *s = RISCV_U_SOC(obj);
+    const char *e_cpu_type = (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_E51
+                                                : TYPE_RISCV_CPU_SIFIVE_E31;
 
     object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
     qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
@@ -764,7 +767,7 @@ static void sifive_u_soc_instance_init(Object *obj)
                             TYPE_RISCV_HART_ARRAY);
     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
-    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
+    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", e_cpu_type);
     qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
 
     object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);

-- 
2.52.0

[PATCH v3 14/14] hw/riscv: Compile once

[Anton Johansson via qemu development]

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 hw/riscv/meson.build | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 533472e22a..8ea5b098eb 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -1,21 +1,21 @@
-riscv_ss = ss.source_set()
-riscv_ss.add(files('boot.c'))
-riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
-riscv_ss.add(files('riscv_hart.c'))
-riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
-riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
-riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
-riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
-riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
-riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files(
+riscv_common_ss = ss.source_set()
+riscv_common_ss.add(files('boot.c'))
+riscv_common_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
+riscv_common_ss.add(files('riscv_hart.c'))
+riscv_common_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
+riscv_common_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
+riscv_common_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
+riscv_common_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
+riscv_common_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
+riscv_common_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
+riscv_common_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
+riscv_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
+riscv_common_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files(
 	'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-hpm.c'))
-riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))
-riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan_kmh.c'))
+riscv_common_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))
+riscv_common_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan_kmh.c'))
 
-riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c'))
-riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'))
+riscv_common_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c'))
+riscv_common_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'))
 
-hw_arch += {'riscv': riscv_ss}
+hw_common_arch += {'riscv': riscv_common_ss}

-- 
2.52.0

Re: [PATCH v3 12/14] target/riscv: Move target_long.h inclusion away from cpu.h

[Pierrick Bouvier]

On 5/20/2026 8:13 AM, Anton Johansson wrote:
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>  target/riscv/cpu.h       | 1 -
>  target/riscv/internals.h | 1 +
>  2 files changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v3 11/14] target/riscv: Stub out kvm functions

[Philippe Mathieu-Daudé]

Hi Anton,

On 20/5/26 15:13, Anton Johansson wrote:
> Functions used externally by hw/riscv are stubbed out for non-kvm
> configurations, allowing a single compilation of hw/riscv.
> 
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>   target/riscv/kvm/kvm-stub.c  | 23 +++++++++++++++++++++++
>   target/riscv/kvm/meson.build |  1 +
>   2 files changed, 24 insertions(+)


> diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build
> index 7e92415091..d3f395f431 100644
> --- a/target/riscv/kvm/meson.build
> +++ b/target/riscv/kvm/meson.build
> @@ -1 +1,2 @@
> +riscv_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
>   riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c'))
> 

If we can not use stub_ss, see commit 0da978cdbc6 ("target/arm: define
stub library").

Re: [PATCH v3 06/14] target-info: Add target_riscv64()

[Chao Liu]

On Wed, May 20, 2026 at 03:12:58PM +0800, Anton Johansson via wrote:
> Adds a helper function to tell if the binary is targeting riscv64 or
> not.
> 
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>  include/qemu/target-info.h | 7 +++++++
>  target-info.c              | 5 +++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
> index 23c997de54..6c5b714288 100644
> --- a/include/qemu/target-info.h
> +++ b/include/qemu/target-info.h
> @@ -99,4 +99,11 @@ bool target_ppc64(void);
>   */
>  bool target_s390x(void);
>  
> +/**
There’s one extra * character here; otherwise LGTM.

Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

Thanks,
Chao
> + * target_riscv64:
> + *
> + * Returns whether the target architecture is riscv64
> + */
> +bool target_riscv64(void);
> +
>  #endif
> diff --git a/target-info.c b/target-info.c
> index 28c458fc7a..04c69c41f8 100644
> --- a/target-info.c
> +++ b/target-info.c
> @@ -93,3 +93,8 @@ bool target_s390x(void)
>  {
>      return target_arch() == SYS_EMU_TARGET_S390X;
>  }
> +
> +bool target_riscv64(void)
> +{
> +    return target_arch() == SYS_EMU_TARGET_RISCV64;
> +}
> 
> -- 
> 2.52.0
> 
> 

Re: [PATCH v3 07/14] target/riscv: Replace TYPE_RISCV_CPU_BASE

[Chao Liu]

On Wed, May 20, 2026 at 03:12:59PM +0800, Anton Johansson via wrote:
> TYPE_RISCV_CPU_BASE is used only to initialize the correct default
> machine for 3 machines. Replace it with a runtime check.
> 
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

> ---
>  include/hw/riscv/machines-qom.h | 12 ++++++++++++
>  target/riscv/cpu.h              |  6 ------
>  hw/riscv/microblaze-v-generic.c |  2 +-
>  hw/riscv/spike.c                |  2 +-
>  hw/riscv/virt.c                 |  2 +-
>  5 files changed, 15 insertions(+), 9 deletions(-)
> 
> diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
> index 3459437d84..8396155373 100644
> --- a/include/hw/riscv/machines-qom.h
> +++ b/include/hw/riscv/machines-qom.h
> @@ -9,7 +9,9 @@
>  #ifndef HW_RISCV_MACHINES_QOM_H
>  #define HW_RISCV_MACHINES_QOM_H
>  
> +#include "qemu/target-info.h"
>  #include "hw/core/boards.h"
> +#include "target/riscv/cpu-qom.h"
>  
>  #define TYPE_TARGET_RISCV32_MACHINE \
>          "target-info-riscv32-machine"
> @@ -43,4 +45,14 @@ extern InterfaceInfo riscv32_64_machine_interfaces[];
>          DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
>                                              riscv32_64_machine_interfaces)
>  
> +/* Default CPU type inferred from target info */
> +static inline const char *riscv_default_cpu_type(void)
> +{
> +    if (target_riscv64()) {
> +        return TYPE_RISCV_CPU_BASE64;
> +    } else {
> +        return TYPE_RISCV_CPU_BASE32;
> +    }
> +}
> +
>  #endif
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fb44f0485d..f521686c43 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -39,12 +39,6 @@ typedef struct CPUArchState CPURISCVState;
>  
>  #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
>  
> -#if defined(TARGET_RISCV32)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
> -#elif defined(TARGET_RISCV64)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
> -#endif
> -
>  /*
>   * b0: Whether a instruction always raise a store AMO or not.
>   */
> diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
> index d33ac39a68..386c5dce9c 100644
> --- a/hw/riscv/microblaze-v-generic.c
> +++ b/hw/riscv/microblaze-v-generic.c
> @@ -183,7 +183,7 @@ static void mb_v_generic_machine_init(MachineClass *mc)
>      mc->init = mb_v_generic_init;
>      mc->min_cpus = 1;
>      mc->max_cpus = 1;
> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +    mc->default_cpu_type = riscv_default_cpu_type();
>      mc->default_cpus = 1;
>  }
>  
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 08ef291b6b..b937cf0fa6 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -343,7 +343,7 @@ static void spike_machine_class_init(ObjectClass *oc, const void *data)
>      mc->init = spike_board_init;
>      mc->max_cpus = SPIKE_CPUS_MAX;
>      mc->is_default = true;
> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +    mc->default_cpu_type = riscv_default_cpu_type();
>      mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
>      mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
>      mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 39caf37c01..e108e29f63 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1933,7 +1933,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
>      mc->desc = "RISC-V VirtIO board";
>      mc->init = virt_machine_init;
>      mc->max_cpus = VIRT_CPUS_MAX;
> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +    mc->default_cpu_type = riscv_default_cpu_type();
>      mc->block_default_type = IF_VIRTIO;
>      mc->no_cdrom = 1;
>      mc->pci_allow_0_address = true;
> 
> -- 
> 2.52.0
> 
> 

Re: [PATCH v3 13/14] hw/riscv: Define SiFive E/U CPUs using runtime conditions

[Chao Liu]

On Wed, May 20, 2026 at 03:13:05PM +0800, Anton Johansson via wrote:
> Macros are removed and replaced with inlined ternary statements.  The
> now empty sifive_cpu.h header is then removed.
> 
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

> ---
>  include/hw/riscv/sifive_cpu.h | 31 -------------------------------
>  include/hw/riscv/sifive_e.h   |  1 -
>  include/hw/riscv/sifive_u.h   |  1 -
>  hw/riscv/sifive_e.c           |  3 ++-
>  hw/riscv/sifive_u.c           |  7 +++++--
>  5 files changed, 7 insertions(+), 36 deletions(-)
> 
> diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
> deleted file mode 100644
> index 136799633a..0000000000
> --- a/include/hw/riscv/sifive_cpu.h
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -/*
> - * SiFive CPU types
> - *
> - * Copyright (c) 2017 SiFive, Inc.
> - * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms and conditions of the GNU General Public License,
> - * version 2 or later, as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope it will be useful, but WITHOUT
> - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> - * more details.
> - *
> - * You should have received a copy of the GNU General Public License along with
> - * this program.  If not, see <http://www.gnu.org/licenses/>.
> - */
> -
> -#ifndef HW_SIFIVE_CPU_H
> -#define HW_SIFIVE_CPU_H
> -
> -#if defined(TARGET_RISCV32)
> -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
> -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
> -#elif defined(TARGET_RISCV64)
> -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
> -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
> -#endif
> -
> -#endif /* HW_SIFIVE_CPU_H */
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 4cf902ebc0..0f0d407d5d 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -20,7 +20,6 @@
>  #define HW_SIFIVE_E_H
>  
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_cpu.h"
>  #include "hw/gpio/sifive_gpio.h"
>  #include "hw/misc/sifive_e_aon.h"
>  #include "hw/core/boards.h"
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index e4c9860d50..bfaaf254af 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -24,7 +24,6 @@
>  #include "hw/dma/sifive_pdma.h"
>  #include "hw/net/cadence_gem.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_cpu.h"
>  #include "hw/gpio/sifive_gpio.h"
>  #include "hw/misc/sifive_u_otp.h"
>  #include "hw/misc/sifive_u_prci.h"
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 71925583bd..76505fdc4d 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -151,7 +151,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc, const void *data)
>      mc->desc = "RISC-V Board compatible with SiFive E SDK";
>      mc->init = sifive_e_machine_init;
>      mc->max_cpus = 1;
> -    mc->default_cpu_type = SIFIVE_E_CPU;
> +    mc->default_cpu_type = (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_E51
> +                                              : TYPE_RISCV_CPU_SIFIVE_E31;
>      mc->default_ram_id = "riscv.sifive.e.ram";
>      mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
>  
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 6a637e3b86..b1f5bad8aa 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -723,7 +723,8 @@ static void sifive_u_machine_class_init(ObjectClass *oc, const void *data)
>      mc->init = sifive_u_machine_init;
>      mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
>      mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
> -    mc->default_cpu_type = SIFIVE_U_CPU;
> +    mc->default_cpu_type = (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_U54
> +                                              : TYPE_RISCV_CPU_SIFIVE_U34;
>      mc->default_cpus = mc->min_cpus;
>      mc->default_ram_id = "riscv.sifive.u.ram";
>      mc->auto_create_sdcard = true;
> @@ -756,6 +757,8 @@ type_init(sifive_u_machine_init_register_types)
>  static void sifive_u_soc_instance_init(Object *obj)
>  {
>      SiFiveUSoCState *s = RISCV_U_SOC(obj);
> +    const char *e_cpu_type = (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_E51
> +                                                : TYPE_RISCV_CPU_SIFIVE_E31;
>  
>      object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
>      qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
> @@ -764,7 +767,7 @@ static void sifive_u_soc_instance_init(Object *obj)
>                              TYPE_RISCV_HART_ARRAY);
>      qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
>      qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
> -    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
> +    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", e_cpu_type);
>      qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
>  
>      object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
> 
> -- 
> 2.52.0
> 
> 

Re: [PATCH v3 02/14] hw/riscv: Add macros and globals for simplifying machine definitions

[Richard Henderson]

On 5/20/26 06:12, Anton Johansson via qemu development wrote:
> +extern InterfaceInfo riscv32_machine_interfaces[];
> +extern InterfaceInfo riscv64_machine_interfaces[];
> +extern InterfaceInfo riscv32_64_machine_interfaces[];

const.

> +InterfaceInfo riscv32_machine_interfaces[] = {
> +    { TYPE_TARGET_RISCV32_MACHINE },
> +    { }
> +};
> +
> +InterfaceInfo riscv64_machine_interfaces[] = {
> +    { TYPE_TARGET_RISCV64_MACHINE },
> +    { }
> +};
> +
> +InterfaceInfo riscv32_64_machine_interfaces[] = {
> +    { TYPE_TARGET_RISCV32_MACHINE },
> +    { TYPE_TARGET_RISCV64_MACHINE },
> +    { }
> +};

const.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v3 01/14] hw/riscv: Register generic riscv[32|64] QOM interfaces

[Richard Henderson]

On 5/20/26 06:12, Anton Johansson via qemu development wrote:
> Defines generic 32- and 64-bit riscv machine interfaces for machines to
> implement.
> 
> Reviewed-by: Pierrick Bouvier<pierrick.bouvier@linaro.org>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
>   include/hw/riscv/machines-qom.h | 20 ++++++++++++++++++++
>   target-info-qom.c               |  9 +++++++++
>   2 files changed, 29 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v3 04/14] hw/core: Add riscv[32|64] to "none" machine

[Richard Henderson]

On 5/20/26 06:12, Anton Johansson via qemu development wrote:
> Reviewed-by: Pierrick Bouvier<pierrick.bouvier@linaro.org>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
>   hw/core/null-machine.c | 3 +++
>   1 file changed, 3 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v3 05/14] configs/target: Implement per-binary TargetInfo structure for riscv

[Richard Henderson]

On 5/20/26 06:12, Anton Johansson via qemu development wrote:
> Defines TargetInfo for 32- and 64-bit riscv binaries.
> 
> Reviewed-by: Pierrick Bouvier<pierrick.bouvier@linaro.org>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
>   configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++++++++++
>   configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++++++++++
>   configs/targets/meson.build       |  1 +
>   3 files changed, 53 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v3 06/14] target-info: Add target_riscv64()

[Philippe Mathieu-Daudé]

On 20/5/26 15:12, Anton Johansson wrote:
> Adds a helper function to tell if the binary is targeting riscv64 or
> not.
> 
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>   include/qemu/target-info.h | 7 +++++++
>   target-info.c              | 5 +++++
>   2 files changed, 12 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH v3 06/14] target-info: Add target_riscv64()

[Philippe Mathieu-Daudé]

On 21/5/26 10:19, Chao Liu wrote:
> On Wed, May 20, 2026 at 03:12:58PM +0800, Anton Johansson via wrote:
>> Adds a helper function to tell if the binary is targeting riscv64 or
>> not.
>>
>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>> Signed-off-by: Anton Johansson <anjo@rev.ng>
>> ---
>>   include/qemu/target-info.h | 7 +++++++
>>   target-info.c              | 5 +++++
>>   2 files changed, 12 insertions(+)
>>
>> diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
>> index 23c997de54..6c5b714288 100644
>> --- a/include/qemu/target-info.h
>> +++ b/include/qemu/target-info.h
>> @@ -99,4 +99,11 @@ bool target_ppc64(void);
>>    */
>>   bool target_s390x(void);
>>   
>> +/**
> There’s one extra * character here; otherwise LGTM.

This is the Javadoc tag which is also used by C tools such doxygen:
https://www.doxygen.nl/manual/docblocks.html#cppblock

We use sphinx with a kerneldoc.py plugin which understands it:
https://www.kernel.org/doc/Documentation/doc-guide/kernel-doc.rst

i.e. https://www.qemu.org/docs/master/devel/index-api.html

> 
> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> 
> Thanks,
> Chao
>> + * target_riscv64:
>> + *
>> + * Returns whether the target architecture is riscv64
>> + */
>> +bool target_riscv64(void);
>> +
>>   #endif
>> diff --git a/target-info.c b/target-info.c
>> index 28c458fc7a..04c69c41f8 100644
>> --- a/target-info.c
>> +++ b/target-info.c
>> @@ -93,3 +93,8 @@ bool target_s390x(void)
>>   {
>>       return target_arch() == SYS_EMU_TARGET_S390X;
>>   }
>> +
>> +bool target_riscv64(void)
>> +{
>> +    return target_arch() == SYS_EMU_TARGET_RISCV64;
>> +}
>>
>> -- 
>> 2.52.0
>>
>>

Re: [PATCH v3 00/14] single-binary: Compile hw/riscv once

[Alistair Francis]

On Wed, 2026-05-20 at 15:12 +0200, Anton Johansson wrote:
> Compiles hw/riscv a single time for both qemu-system-riscv32 and
> qemu-system-riscv64 by adopting the TargetInfo API and by moving
> machine definitions to generic QOM interfaces. This is the same
> approach
> as taken by Philippe in
> 
>     "single-binary: Make hw/arm/ common"
>     (20251021205741.57109-1-philmd@linaro.org).
> 
> All in all, the number of compilation when building both
> riscv[32|64]-softmmu is reduced by 11, and the binary size of
> qemu-system-riscv[32|64] is increased by 0.11% and 0.026%
> respectively
> (corresponding to 65k and 14k bytes).
> 
> This patchset is based on:
> 
>     "single-binary: Make riscv cpu.h target independent"
>     (20260520125406.28693-1-anjo@rev.ng).
> 
> Branch passing CI can be found here:
> 
>   https://gitlab.com/AntonJohansson/qemu/-/pipelines/2215536778
> 
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> Changes in v3:
> - Dropped merged prequisite patchsets.
> - patch 5/14 "configs/target: Implement per-binary TargetInfo
> structure
>   for riscv": Use new target_info_init() TargetInfo registration.
> - patch 7/14 "target/riscv: Replace TYPE_RISCV_CPU_BASE": Rename
>   virt_default_cpu_type() -> riscv_default_cpu_type() and define in
>   machines-qom.h.
> - Dropped patch "[PATCH v2 11/14] target/riscv: Make pmu.h target-
> agnostic":
>   This patch replaced target_ulongs with privilege_mode_t and has
> been folded
>   into the prerequisite patchset introducing the typedef. 
> - Added patch 12/14 "target/riscv: Move target_long.h inclusion
>   away from cpu.h": Moves target_long.h inclusion to target specific
>   header. 
> - Link to v2:
> https://lore.kernel.org/qemu-devel/20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng
> 
> Changes in v2:
> - Inlined sifive_cpu.h runtime functions and removed header
> (Philippe);
> - Moved IRQ_LOCAL_GUEST_MAX macro to field in RISCVCPUDef (Philippe);
> - Added reviewed-bys;
> - Link to v1:
> https://lore.kernel.org/qemu-devel/20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng
> .
> 
> ---
> Anton Johansson (14):
>       hw/riscv: Register generic riscv[32|64] QOM interfaces
>       hw/riscv: Add macros and globals for simplifying machine
> definitions
>       hw/riscv: Filter machine types for qemu-system-riscv32/64
> binaries
>       hw/core: Add riscv[32|64] to "none" machine
>       configs/target: Implement per-binary TargetInfo structure for
> riscv
>       target-info: Add target_riscv64()
>       target/riscv: Replace TYPE_RISCV_CPU_BASE
>       target/riscv: Remove ifdefs in cpu.h
>       target/riscv: Replace TARGET_LONG_BITS in header exposed to
> common code
>       target/riscv: Move riscv_pmu_read_ctr() to internal csr.h
> header
>       target/riscv: Stub out kvm functions
>       target/riscv: Move target_long.h inclusion away from cpu.h
>       hw/riscv: Define SiFive E/U CPUs using runtime conditions
>       hw/riscv: Compile once

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> 
>  include/hw/riscv/machines-qom.h   | 58
> +++++++++++++++++++++++++++++++++++++++
>  include/hw/riscv/sifive_cpu.h     | 31 ---------------------
>  include/hw/riscv/sifive_e.h       |  1 -
>  include/hw/riscv/sifive_u.h       |  1 -
>  include/qemu/target-info.h        |  7 +++++
>  target/riscv/cpu.h                | 44 ++++++-----------------------
>  target/riscv/cpu_bits.h           |  2 --
>  target/riscv/csr.h                |  3 ++
>  target/riscv/internals.h          |  1 +
>  target/riscv/pmu.h                |  2 --
>  configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++
>  configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++
>  hw/core/null-machine.c            |  3 ++
>  hw/intc/riscv_imsic.c             |  4 ++-
>  hw/riscv/boston-aia.c             |  3 +-
>  hw/riscv/microblaze-v-generic.c   |  5 ++--
>  hw/riscv/microchip_pfsoc.c        |  2 ++
>  hw/riscv/opentitan.c              |  2 ++
>  hw/riscv/shakti_c.c               |  2 ++
>  hw/riscv/sifive_e.c               |  5 +++-
>  hw/riscv/sifive_u.c               |  9 ++++--
>  hw/riscv/spike.c                  |  4 ++-
>  hw/riscv/virt.c                   |  5 +++-
>  hw/riscv/xiangshan_kmh.c          |  2 ++
>  target-info-qom.c                 |  9 ++++++
>  target-info.c                     |  5 ++++
>  target/riscv/cpu.c                | 14 ++++++++--
>  target/riscv/kvm/kvm-stub.c       | 23 ++++++++++++++++
>  target/riscv/machine.c            | 17 ++++++++++++
>  target/riscv/pmu.c                |  1 +
>  configs/targets/meson.build       |  1 +
>  hw/riscv/meson.build              | 36 ++++++++++++------------
>  target/riscv/kvm/meson.build      |  1 +
>  33 files changed, 254 insertions(+), 101 deletions(-)

Re: [PATCH v3 00/14] single-binary: Compile hw/riscv once

[Alistair Francis]

On Wed, 2026-05-20 at 15:12 +0200, Anton Johansson wrote:

Also please send patches to all people listed under the RISC-V
maintainers, otherwise not everyone ends up seeing the messages.

Alistair

> Compiles hw/riscv a single time for both qemu-system-riscv32 and
> qemu-system-riscv64 by adopting the TargetInfo API and by moving
> machine definitions to generic QOM interfaces. This is the same
> approach
> as taken by Philippe in
> 
>     "single-binary: Make hw/arm/ common"
>     (20251021205741.57109-1-philmd@linaro.org).
> 
> All in all, the number of compilation when building both
> riscv[32|64]-softmmu is reduced by 11, and the binary size of
> qemu-system-riscv[32|64] is increased by 0.11% and 0.026%
> respectively
> (corresponding to 65k and 14k bytes).
> 
> This patchset is based on:
> 
>     "single-binary: Make riscv cpu.h target independent"
>     (20260520125406.28693-1-anjo@rev.ng).
> 
> Branch passing CI can be found here:
> 
>   https://gitlab.com/AntonJohansson/qemu/-/pipelines/2215536778
> 
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> Changes in v3:
> - Dropped merged prequisite patchsets.
> - patch 5/14 "configs/target: Implement per-binary TargetInfo
> structure
>   for riscv": Use new target_info_init() TargetInfo registration.
> - patch 7/14 "target/riscv: Replace TYPE_RISCV_CPU_BASE": Rename
>   virt_default_cpu_type() -> riscv_default_cpu_type() and define in
>   machines-qom.h.
> - Dropped patch "[PATCH v2 11/14] target/riscv: Make pmu.h target-
> agnostic":
>   This patch replaced target_ulongs with privilege_mode_t and has
> been folded
>   into the prerequisite patchset introducing the typedef. 
> - Added patch 12/14 "target/riscv: Move target_long.h inclusion
>   away from cpu.h": Moves target_long.h inclusion to target specific
>   header. 
> - Link to v2:
> https://lore.kernel.org/qemu-devel/20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng
> 
> Changes in v2:
> - Inlined sifive_cpu.h runtime functions and removed header
> (Philippe);
> - Moved IRQ_LOCAL_GUEST_MAX macro to field in RISCVCPUDef (Philippe);
> - Added reviewed-bys;
> - Link to v1:
> https://lore.kernel.org/qemu-devel/20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng
> .
> 
> ---
> Anton Johansson (14):
>       hw/riscv: Register generic riscv[32|64] QOM interfaces
>       hw/riscv: Add macros and globals for simplifying machine
> definitions
>       hw/riscv: Filter machine types for qemu-system-riscv32/64
> binaries
>       hw/core: Add riscv[32|64] to "none" machine
>       configs/target: Implement per-binary TargetInfo structure for
> riscv
>       target-info: Add target_riscv64()
>       target/riscv: Replace TYPE_RISCV_CPU_BASE
>       target/riscv: Remove ifdefs in cpu.h
>       target/riscv: Replace TARGET_LONG_BITS in header exposed to
> common code
>       target/riscv: Move riscv_pmu_read_ctr() to internal csr.h
> header
>       target/riscv: Stub out kvm functions
>       target/riscv: Move target_long.h inclusion away from cpu.h
>       hw/riscv: Define SiFive E/U CPUs using runtime conditions
>       hw/riscv: Compile once
> 
>  include/hw/riscv/machines-qom.h   | 58
> +++++++++++++++++++++++++++++++++++++++
>  include/hw/riscv/sifive_cpu.h     | 31 ---------------------
>  include/hw/riscv/sifive_e.h       |  1 -
>  include/hw/riscv/sifive_u.h       |  1 -
>  include/qemu/target-info.h        |  7 +++++
>  target/riscv/cpu.h                | 44 ++++++-----------------------
>  target/riscv/cpu_bits.h           |  2 --
>  target/riscv/csr.h                |  3 ++
>  target/riscv/internals.h          |  1 +
>  target/riscv/pmu.h                |  2 --
>  configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++
>  configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++
>  hw/core/null-machine.c            |  3 ++
>  hw/intc/riscv_imsic.c             |  4 ++-
>  hw/riscv/boston-aia.c             |  3 +-
>  hw/riscv/microblaze-v-generic.c   |  5 ++--
>  hw/riscv/microchip_pfsoc.c        |  2 ++
>  hw/riscv/opentitan.c              |  2 ++
>  hw/riscv/shakti_c.c               |  2 ++
>  hw/riscv/sifive_e.c               |  5 +++-
>  hw/riscv/sifive_u.c               |  9 ++++--
>  hw/riscv/spike.c                  |  4 ++-
>  hw/riscv/virt.c                   |  5 +++-
>  hw/riscv/xiangshan_kmh.c          |  2 ++
>  target-info-qom.c                 |  9 ++++++
>  target-info.c                     |  5 ++++
>  target/riscv/cpu.c                | 14 ++++++++--
>  target/riscv/kvm/kvm-stub.c       | 23 ++++++++++++++++
>  target/riscv/machine.c            | 17 ++++++++++++
>  target/riscv/pmu.c                |  1 +
>  configs/targets/meson.build       |  1 +
>  hw/riscv/meson.build              | 36 ++++++++++++------------
>  target/riscv/kvm/meson.build      |  1 +
>  33 files changed, 254 insertions(+), 101 deletions(-)

Re: [PATCH v3 00/14] single-binary: Compile hw/riscv once

[Philippe Mathieu-Daudé]

On 20/5/26 15:12, Anton Johansson wrote:

> ---
> Anton Johansson (14):
>        hw/riscv: Register generic riscv[32|64] QOM interfaces
>        hw/riscv: Add macros and globals for simplifying machine definitions
>        hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries
>        hw/core: Add riscv[32|64] to "none" machine
>        configs/target: Implement per-binary TargetInfo structure for riscv
>        target-info: Add target_riscv64()

Queuing first 6 patches (addressing rth comment), thanks.

Re: [PATCH v3 00/14] single-binary: Compile hw/riscv once

[Anton Johansson via]

On 27/05/26, Philippe Mathieu-Daudé wrote:
> On 20/5/26 15:12, Anton Johansson wrote:
> 
> > ---
> > Anton Johansson (14):
> >        hw/riscv: Register generic riscv[32|64] QOM interfaces
> >        hw/riscv: Add macros and globals for simplifying machine definitions
> >        hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries
> >        hw/core: Add riscv[32|64] to "none" machine
> >        configs/target: Implement per-binary TargetInfo structure for riscv
> >        target-info: Add target_riscv64()
> 
> Queuing first 6 patches (addressing rth comment), thanks.

Thank you!:) Must have missed Richards comment huh, by bad.

-- 
Anton Johansson
rev.ng Labs Srl.

Re: [PATCH v3 00/14] single-binary: Compile hw/riscv once

[Anton Johansson via qemu development]

On 27/05/26, Philippe Mathieu-Daudé wrote:
> On 20/5/26 15:12, Anton Johansson wrote:
> 
> > ---
> > Anton Johansson (14):
> >        hw/riscv: Register generic riscv[32|64] QOM interfaces
> >        hw/riscv: Add macros and globals for simplifying machine definitions
> >        hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries
> >        hw/core: Add riscv[32|64] to "none" machine
> >        configs/target: Implement per-binary TargetInfo structure for riscv
> >        target-info: Add target_riscv64()
> 
> Queuing first 6 patches (addressing rth comment), thanks.

Thank you!:) Must have missed Richards comment huh, by bad.

-- 
Anton Johansson
rev.ng Labs Srl.

Re: [PATCH v3 00/14] single-binary: Compile hw/riscv once

[Philippe Mathieu-Daudé]

On 28/5/26 17:06, Anton Johansson wrote:
> On 27/05/26, Philippe Mathieu-Daudé wrote:
>> On 20/5/26 15:12, Anton Johansson wrote:
>>
>>> ---
>>> Anton Johansson (14):
>>>         hw/riscv: Register generic riscv[32|64] QOM interfaces
>>>         hw/riscv: Add macros and globals for simplifying machine definitions
>>>         hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries
>>>         hw/core: Add riscv[32|64] to "none" machine
>>>         configs/target: Implement per-binary TargetInfo structure for riscv
>>>         target-info: Add target_riscv64()
>>
>> Queuing first 6 patches (addressing rth comment), thanks.
> 
> Thank you!:) Must have missed Richards comment huh, by bad.

(The reason I couldn't take the whole series is because the rest
has dependencies on another series of yours which is already in
Alistair riscv queue).