[PATCH v4 0/2] ns16550: add support for WCH CH382 and ASIX AX99100

[PATCH v4 0/2] ns16550: add support for WCH CH382 and ASIX AX99100

[Jiaqing Zhao]

This series adds ns16550 support for two PCIe serial adapters found on
market:

 - WCH (Nanjing Qinheng Microelectronics) CH382, available as
   CH382 2S [1c00:3253] and CH382 2S1P [1c00:3250].
 - ASIX AX99100 PCIe to Multi-I/O Controller [125b:9910].

Both chips expose 16550-compatible UARTs through PCI I/O BAR0 and
work with the existing ns16550 driver once a matching device table
entry and parameter set are added.

v4:
 - Add Reviewed-by from Stefano.

v3:
 - New patch 2/2: add support for ASIX AX99100.
 - Add forgotten Reviewed-by from Denis in patch 1/2 (WCH CH382).

v2:
 - Reorder entries in ns16550_config to keep them sorted by device ID.
 - Rename PCI_VENDOR_ID_WCH to PCI_VENDOR_ID_WCHIC as WCH has multiple
   vendor IDs.

Jiaqing Zhao (2):
  ns16550: add support for WCH CH382 serial adapters
  ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller

 xen/drivers/char/ns16550.c | 38 ++++++++++++++++++++++++++++++++++++++
 xen/include/xen/pci_ids.h  |  4 ++++
 2 files changed, 42 insertions(+)

-- 
2.53.0

[PATCH v4 1/2] ns16550: add support for WCH CH382 serial adapters

[Jiaqing Zhao]

Add support for the WCH (Nanjing Qinheng Microelectronics Co., Ltd.)
CH382 PCIe dual port serial adapter. The CH382 is available in two
variants:
 - CH382 2S   [1c00:3253]: 2 serial ports
 - CH382 2S1P [1c00:3250]: 2 serial ports + 1 parallel port

This chip uses IO BAR0, base baud rate 115200, ports starting at offset
0xc0 and spaced 8 bytes apart, and a 256-byte FIFO. [1]

[1] https://www.wch-ic.com/downloads/CH382DS1_PDF.html

Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com>
Reviewed-by: Denis Mukhin <dmukhin@ford.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/drivers/char/ns16550.c | 23 +++++++++++++++++++++++
 xen/include/xen/pci_ids.h  |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
index 878da27f2e..cf10a06a3d 100644
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -95,6 +95,7 @@ struct ns16550_config {
         param_exar_xr17v354,
         param_exar_xr17v358,
         param_intel_lpss,
+        param_wch_ch382,
     } param;
 };
 
@@ -861,6 +862,16 @@ static const struct ns16550_config_param __initconst uart_param[] = {
         .mmio = 1,
         .max_ports = 1,
     },
+    [param_wch_ch382] = {
+        .base_baud = 115200,
+        .first_offset = 0xc0,
+        .uart_offset = 8,
+        .reg_width = 1,
+        .fifo_size = 256,
+        .lsr_mask = UART_LSR_THRE,
+        .bar0 = 1,
+        .max_ports = 2,
+    },
 };
 
 static const struct ns16550_config __initconst uart_config[] =
@@ -1189,6 +1200,18 @@ static const struct ns16550_config __initconst uart_config[] =
         .dev_id = 0x7adc,
         .param = param_intel_lpss
     },
+    /* WCH CH382 2S1P */
+    {
+        .vendor_id = PCI_VENDOR_ID_WCHIC,
+        .dev_id = 0x3250,
+        .param = param_wch_ch382
+    },
+    /* WCH CH382 2S */
+    {
+        .vendor_id = PCI_VENDOR_ID_WCHIC,
+        .dev_id = 0x3253,
+        .param = param_wch_ch382
+    },
 };
 
 static int __init
diff --git a/xen/include/xen/pci_ids.h b/xen/include/xen/pci_ids.h
index 5884a20b8f..15e938225c 100644
--- a/xen/include/xen/pci_ids.h
+++ b/xen/include/xen/pci_ids.h
@@ -13,6 +13,8 @@
 
 #define PCI_VENDOR_ID_BROADCOM           0x14e4
 
+#define PCI_VENDOR_ID_WCHIC              0x1c00
+
 #define PCI_VENDOR_ID_INTEL              0x8086
 
 #endif /* XEN_PCI_IDS_H */
-- 
2.53.0

Re: [PATCH v4 1/2] ns16550: add support for WCH CH382 serial adapters

[Roger Pau Monné]

On Tue, Jun 02, 2026 at 01:34:20PM +0800, Jiaqing Zhao wrote:
> Add support for the WCH (Nanjing Qinheng Microelectronics Co., Ltd.)
> CH382 PCIe dual port serial adapter. The CH382 is available in two
> variants:
>  - CH382 2S   [1c00:3253]: 2 serial ports
>  - CH382 2S1P [1c00:3250]: 2 serial ports + 1 parallel port
> 
> This chip uses IO BAR0, base baud rate 115200, ports starting at offset
> 0xc0 and spaced 8 bytes apart, and a 256-byte FIFO. [1]
> 
> [1] https://www.wch-ic.com/downloads/CH382DS1_PDF.html
> 
> Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com>
> Reviewed-by: Denis Mukhin <dmukhin@ford.com>
> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> ---
>  xen/drivers/char/ns16550.c | 23 +++++++++++++++++++++++
>  xen/include/xen/pci_ids.h  |  2 ++
>  2 files changed, 25 insertions(+)
> 
> diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
> index 878da27f2e..cf10a06a3d 100644
> --- a/xen/drivers/char/ns16550.c
> +++ b/xen/drivers/char/ns16550.c
> @@ -95,6 +95,7 @@ struct ns16550_config {
>          param_exar_xr17v354,
>          param_exar_xr17v358,
>          param_intel_lpss,
> +        param_wch_ch382,
>      } param;
>  };
>  
> @@ -861,6 +862,16 @@ static const struct ns16550_config_param __initconst uart_param[] = {
>          .mmio = 1,
>          .max_ports = 1,
>      },
> +    [param_wch_ch382] = {
> +        .base_baud = 115200,
> +        .first_offset = 0xc0,
> +        .uart_offset = 8,
> +        .reg_width = 1,
> +        .fifo_size = 256,
> +        .lsr_mask = UART_LSR_THRE,
> +        .bar0 = 1,

.bar0 field is a boolean, and hence this should be "true", not "1".

The rest LGTM:

Acked-by: Roger Pau Monné <roger.pau@citrix.com>

Thanks, Roger.

[PATCH v4 2/2] ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller

[Jiaqing Zhao]

Add a PCI device table entry and matching parameter for the ASIX
AX99100 PCIe to Multi-I/O controller [125b:9910]. Each port on the
chip is a standalone PCI function, with UART registers on its I/O
BAR0.

Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/drivers/char/ns16550.c | 15 +++++++++++++++
 xen/include/xen/pci_ids.h  |  2 ++
 2 files changed, 17 insertions(+)

diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
index cf10a06a3d..26503070dc 100644
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -96,6 +96,7 @@ struct ns16550_config {
         param_exar_xr17v358,
         param_intel_lpss,
         param_wch_ch382,
+        param_asix,
     } param;
 };
 
@@ -872,6 +873,14 @@ static const struct ns16550_config_param __initconst uart_param[] = {
         .bar0 = 1,
         .max_ports = 2,
     },
+    [param_asix] = {
+        .base_baud = 115200,
+        .reg_width = 1,
+        .fifo_size = 256,
+        .lsr_mask = UART_LSR_THRE,
+        .bar0 = 1,
+        .max_ports = 1,
+    },
 };
 
 static const struct ns16550_config __initconst uart_config[] =
@@ -1212,6 +1221,12 @@ static const struct ns16550_config __initconst uart_config[] =
         .dev_id = 0x3253,
         .param = param_wch_ch382
     },
+    /* ASIX AX99100 PCIe to Multi I/O Controller */
+    {
+        .vendor_id = PCI_VENDOR_ID_ASIX,
+        .dev_id = 0x9910,
+        .param = param_asix
+    },
 };
 
 static int __init
diff --git a/xen/include/xen/pci_ids.h b/xen/include/xen/pci_ids.h
index 15e938225c..fd424ef55d 100644
--- a/xen/include/xen/pci_ids.h
+++ b/xen/include/xen/pci_ids.h
@@ -5,6 +5,8 @@
 
 #define PCI_VENDOR_ID_NVIDIA             0x10de
 
+#define PCI_VENDOR_ID_ASIX               0x125b
+
 #define PCI_VENDOR_ID_PERICOM            0x12d8
 
 #define PCI_VENDOR_ID_EXAR               0x13a8
-- 
2.53.0

Re: [PATCH v4 2/2] ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller

[Jiaqing Zhao]

Hi all,

Apologies for the noise. I forgot to remove the incorrect tocmd in git sendemail config and
accidentally included the maintainers in --to instead of --cc when sending this patchset.

Sorry for the unnecessary notification. I'll be more careful with my git send-email recipients
next time.

Thanks,
Jiaqing

On 2026-06-02 13:34, Jiaqing Zhao wrote:
> Add a PCI device table entry and matching parameter for the ASIX
> AX99100 PCIe to Multi-I/O controller [125b:9910]. Each port on the
> chip is a standalone PCI function, with UART registers on its I/O
> BAR0.
> 
> Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com>
> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> ---
>  xen/drivers/char/ns16550.c | 15 +++++++++++++++
>  xen/include/xen/pci_ids.h  |  2 ++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
> index cf10a06a3d..26503070dc 100644
> --- a/xen/drivers/char/ns16550.c
> +++ b/xen/drivers/char/ns16550.c
> @@ -96,6 +96,7 @@ struct ns16550_config {
>          param_exar_xr17v358,
>          param_intel_lpss,
>          param_wch_ch382,
> +        param_asix,
>      } param;
>  };
>  
> @@ -872,6 +873,14 @@ static const struct ns16550_config_param __initconst uart_param[] = {
>          .bar0 = 1,
>          .max_ports = 2,
>      },
> +    [param_asix] = {
> +        .base_baud = 115200,
> +        .reg_width = 1,
> +        .fifo_size = 256,
> +        .lsr_mask = UART_LSR_THRE,
> +        .bar0 = 1,
> +        .max_ports = 1,
> +    },
>  };
>  
>  static const struct ns16550_config __initconst uart_config[] =
> @@ -1212,6 +1221,12 @@ static const struct ns16550_config __initconst uart_config[] =
>          .dev_id = 0x3253,
>          .param = param_wch_ch382
>      },
> +    /* ASIX AX99100 PCIe to Multi I/O Controller */
> +    {
> +        .vendor_id = PCI_VENDOR_ID_ASIX,
> +        .dev_id = 0x9910,
> +        .param = param_asix
> +    },
>  };
>  
>  static int __init
> diff --git a/xen/include/xen/pci_ids.h b/xen/include/xen/pci_ids.h
> index 15e938225c..fd424ef55d 100644
> --- a/xen/include/xen/pci_ids.h
> +++ b/xen/include/xen/pci_ids.h
> @@ -5,6 +5,8 @@
>  
>  #define PCI_VENDOR_ID_NVIDIA             0x10de
>  
> +#define PCI_VENDOR_ID_ASIX               0x125b
> +
>  #define PCI_VENDOR_ID_PERICOM            0x12d8
>  
>  #define PCI_VENDOR_ID_EXAR               0x13a8

Re: [PATCH v4 2/2] ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller

[Roger Pau Monné]

On Tue, Jun 02, 2026 at 01:34:21PM +0800, Jiaqing Zhao wrote:
> Add a PCI device table entry and matching parameter for the ASIX
> AX99100 PCIe to Multi-I/O controller [125b:9910]. Each port on the
> chip is a standalone PCI function, with UART registers on its I/O
> BAR0.
> 
> Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com>
> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> ---
>  xen/drivers/char/ns16550.c | 15 +++++++++++++++
>  xen/include/xen/pci_ids.h  |  2 ++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
> index cf10a06a3d..26503070dc 100644
> --- a/xen/drivers/char/ns16550.c
> +++ b/xen/drivers/char/ns16550.c
> @@ -96,6 +96,7 @@ struct ns16550_config {
>          param_exar_xr17v358,
>          param_intel_lpss,
>          param_wch_ch382,
> +        param_asix,
>      } param;
>  };
>  
> @@ -872,6 +873,14 @@ static const struct ns16550_config_param __initconst uart_param[] = {
>          .bar0 = 1,
>          .max_ports = 2,
>      },
> +    [param_asix] = {
> +        .base_baud = 115200,
> +        .reg_width = 1,
> +        .fifo_size = 256,
> +        .lsr_mask = UART_LSR_THRE,
> +        .bar0 = 1,

Same comment about using 1 instead of true, the rest seem reasonable:

Acked-by: Roger Pau Monné <roger.pau@citrix.com>

Thanks, Roger.

Re: [PATCH v4 0/2] ns16550: add support for WCH CH382 and ASIX AX99100

[Jan Beulich]

On 02.06.2026 07:34, Jiaqing Zhao wrote:
> This series adds ns16550 support for two PCIe serial adapters found on
> market:
> 
>  - WCH (Nanjing Qinheng Microelectronics) CH382, available as
>    CH382 2S [1c00:3253] and CH382 2S1P [1c00:3250].
>  - ASIX AX99100 PCIe to Multi-I/O Controller [125b:9910].
> 
> Both chips expose 16550-compatible UARTs through PCI I/O BAR0 and
> work with the existing ns16550 driver once a matching device table
> entry and parameter set are added.
> 
> v4:
>  - Add Reviewed-by from Stefano.

There's no need to re-submit just for this. Mail volume is already high
enough. The fact that this wasn't merged yet doesn't indicate any need
to re-submit: This series simply needs to wait until the tree re-opens
for the 4.23 dev cycle.

Jan

Re: [PATCH v4 0/2] ns16550: add support for WCH CH382 and ASIX AX99100

[Jiaqing Zhao]

Sorry I missed this mail. Please ignore my latest v6...

On 2026-06-02 18:15, Jan Beulich wrote:
> [You don't often get email from jbeulich@suse.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> On 02.06.2026 07:34, Jiaqing Zhao wrote:
>> This series adds ns16550 support for two PCIe serial adapters found on
>> market:
>>
>>  - WCH (Nanjing Qinheng Microelectronics) CH382, available as
>>    CH382 2S [1c00:3253] and CH382 2S1P [1c00:3250].
>>  - ASIX AX99100 PCIe to Multi-I/O Controller [125b:9910].
>>
>> Both chips expose 16550-compatible UARTs through PCI I/O BAR0 and
>> work with the existing ns16550 driver once a matching device table
>> entry and parameter set are added.
>>
>> v4:
>>  - Add Reviewed-by from Stefano.
> 
> There's no need to re-submit just for this. Mail volume is already high
> enough. The fact that this wasn't merged yet doesn't indicate any need
> to re-submit: This series simply needs to wait until the tree re-opens
> for the 4.23 dev cycle.
> 
> Jan