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From: Charles Keepax <ckeepax@opensource.cirrus.com>
To: "Chancel Liu (OSS)" <chancel.liu@oss.nxp.com>
Cc: Mark Brown <broonie@kernel.org>,
	"lgirdwood@gmail.com" <lgirdwood@gmail.com>,
	"perex@perex.cz" <perex@perex.cz>,
	"tiwai@suse.com" <tiwai@suse.com>,
	"david.rhodes@cirrus.com" <david.rhodes@cirrus.com>,
	"rf@opensource.cirrus.com" <rf@opensource.cirrus.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-sound@vger.kernel.org" <linux-sound@vger.kernel.org>,
	"patches@opensource.cirrus.com" <patches@opensource.cirrus.com>
Subject: Re: [PATCH] ASoC: cs42xx8: Add SPI bus support for CS42448/CS42888 codec
Date: Tue, 2 Jun 2026 09:44:02 +0100	[thread overview]
Message-ID: <ah6X0vwXpayzcWXI@opensource.cirrus.com> (raw)
In-Reply-To: <AM9PR04MB8353ED13E31C180953F8C9A8E3122@AM9PR04MB8353.eurprd04.prod.outlook.com>

On Tue, Jun 02, 2026 at 06:25:33AM +0000, Chancel Liu (OSS) wrote:
> > > The existing cs42xx8 driver only supported I2C control interface.
> > > Add SPI bus support for the Cirrus Logic CS42448/CS42888 Audio CODEC.
> > 
> > > + * The SPI frame is 3 bytes:
> > > + *   Byte 0: chip address [7:1] = 1001111, bit[0] = R/W (0=write,
> > 1=read)
> > > + *           Write: 0x9E,  Read: 0x9F
> > > + *   Byte 1: MAP - Memory Address Pointer
> > > + *           bit[7] = INCR (auto-increment for burst), bits[6:0] =
> > address
> > 
> > > + * We configure reg_bits=16 so that regmap treats the address field as
> > 2 bytes
> > > + * (big-endian). The chip address byte (0x9E/0x9F) is placed in the
> > high byte
> > > + * via write_flag_mask / read_flag_mask, and the MAP register address
> > occupies
> > > + * the low byte. This produces the correct 3-byte on-wire frame without
> > any
> > > + * custom bus implementation:
> > > + *
> > > + *   write: [0x9E, MAP_addr, data]
> > > + *   read:  [0x9F, MAP_addr] -> [data]
> > 
> > What about INCR?
> > 
> 
> Indeed. This patch doesn't handle INCR. I'll enable INCR after reworking
> on write_flag_mask/read_flag_mask.
> 

I don't think the driver does anything that reads/writes more
than a single register, so one could probably just set
use_single_read/write and punt on handling INCR for now.

> > > +static const struct of_device_id cs42xx8_of_match[] = {
> > > +	{ .compatible = "cirrus,cs42448", .data = &cs42448_data, },
> > > +	{ .compatible = "cirrus,cs42888", .data = &cs42888_data, },
> > > +	{ /* sentinel */ }
> > > +};
> > > +MODULE_DEVICE_TABLE(of, cs42xx8_of_match);
> > 
> > This should have an update to the bindings as well.

Thanks sorry missed that.

Thanks,
Charles

  reply	other threads:[~2026-06-02  8:44 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-01  8:02 [PATCH] ASoC: cs42xx8: Add SPI bus support for CS42448/CS42888 codec chancel.liu
2026-06-01  8:39 ` Charles Keepax
2026-06-02  5:31   ` Chancel Liu (OSS)
2026-06-01 16:53 ` Mark Brown
2026-06-02  6:25   ` Chancel Liu (OSS)
2026-06-02  8:44     ` Charles Keepax [this message]
2026-06-02  9:56       ` Chancel Liu (OSS)
2026-06-03  9:50 ` [PATCH v2 0/2] " chancel.liu
2026-06-03  9:50   ` [PATCH v2 1/2] ASoC: dt-bindings: cirrus,cs42xx8: Add SPI bus support chancel.liu
2026-06-03 10:00     ` sashiko-bot
2026-06-03  9:50   ` [PATCH v2 2/2] ASoC: cs42xx8: Add SPI bus support for CS42448/CS42888 codec chancel.liu
2026-06-03 10:15     ` sashiko-bot
2026-06-03 11:46   ` [PATCH v2 0/2] " Charles Keepax
2026-06-03 11:57   ` Mark Brown
2026-06-03 12:14     ` Chancel Liu (OSS)
2026-06-03 11:57   ` Mark Brown

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