* [PATCH v5 0/3] ns16550: add support for WCH CH382 and ASIX AX99100
@ 2026-06-02 16:13 Jiaqing Zhao
2026-06-02 16:13 ` [PATCH v5 1/3] ns16550: properly initialize booleans in uart_param[] Jiaqing Zhao
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Jiaqing Zhao @ 2026-06-02 16:13 UTC (permalink / raw)
To: xen-devel
Cc: Andrew Cooper, Anthony PERARD, Jan Beulich, Julien Grall,
Michal Orzel, Roger Pau Monné, Stefano Stabellini,
Jiaqing Zhao
This series adds ns16550 support for two PCIe serial adapters found on
market:
- WCH (Nanjing Qinheng Microelectronics) CH382, available as
CH382 2S [1c00:3253] and CH382 2S1P [1c00:3250].
- ASIX AX99100 PCIe to Multi-I/O Controller [125b:9910].
Both chips expose 16550-compatible UARTs through PCI I/O BAR0 and
work with the existing ns16550 driver once a matching device table
entry and parameter set are added.
v5:
- Add Acked-by from Roger.
- New patch 1/3: Initialize booleans in uart_param[] with "true"
instead of 1, as suggested by Roger.
v4:
- Add Reviewed-by from Stefano.
v3:
- New patch 2/2: add support for ASIX AX99100.
- Add forgotten Reviewed-by from Denis in patch 1/2 (WCH CH382).
v2:
- Reorder entries in ns16550_config to keep them sorted by device ID.
- Rename PCI_VENDOR_ID_WCH to PCI_VENDOR_ID_WCHIC as WCH has multiple
vendor IDs.
Jiaqing Zhao (3):
ns16550: properly initialize booleans in uart_param[]
ns16550: add support for WCH CH382 serial adapters
ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller
Jiaqing Zhao (3):
ns16550: properly initialize booleans in uart_param[]
ns16550: add support for WCH CH382 serial adapters
ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller
xen/drivers/char/ns16550.c | 68 +++++++++++++++++++++++++++++---------
xen/include/xen/pci_ids.h | 4 +++
2 files changed, 57 insertions(+), 15 deletions(-)
--
2.53.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v5 1/3] ns16550: properly initialize booleans in uart_param[] 2026-06-02 16:13 [PATCH v5 0/3] ns16550: add support for WCH CH382 and ASIX AX99100 Jiaqing Zhao @ 2026-06-02 16:13 ` Jiaqing Zhao 2026-06-02 17:11 ` dmukhin 2026-06-03 5:45 ` Jan Beulich 2026-06-02 16:13 ` [PATCH v5 2/3] ns16550: add support for WCH CH382 serial adapters Jiaqing Zhao 2026-06-02 16:13 ` [PATCH v5 3/3] ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller Jiaqing Zhao 2 siblings, 2 replies; 6+ messages in thread From: Jiaqing Zhao @ 2026-06-02 16:13 UTC (permalink / raw) To: xen-devel Cc: Andrew Cooper, Anthony PERARD, Jan Beulich, Julien Grall, Michal Orzel, Roger Pau Monné, Stefano Stabellini, Jiaqing Zhao .bar0 and .mmio in struct ns16550_config_param are booleans, hence they should be initialized with "true", not "1". No functional change. Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com> --- xen/drivers/char/ns16550.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 878da27f2e..ed4e29ec25 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -758,7 +758,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 16, .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT), - .mmio = 1, + .mmio = true, .max_ports = 1, }, [param_oxford] = { @@ -768,7 +768,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 16, .lsr_mask = UART_LSR_THRE, - .mmio = 1, + .mmio = true, .max_ports = 1, /* It can do more, but we would need more custom code.*/ }, [param_oxford_2port] = { @@ -778,7 +778,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 16, .lsr_mask = UART_LSR_THRE, - .mmio = 1, + .mmio = true, .max_ports = 2, }, [param_pericom_1port] = { @@ -787,7 +787,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 16, .lsr_mask = UART_LSR_THRE, - .bar0 = 1, + .bar0 = true, .max_ports = 1, }, [param_pericom_2port] = { @@ -796,7 +796,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 16, .lsr_mask = UART_LSR_THRE, - .bar0 = 1, + .bar0 = true, .max_ports = 2, }, /* @@ -809,7 +809,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 16, .lsr_mask = UART_LSR_THRE, - .bar0 = 1, + .bar0 = true, .max_ports = 4, }, [param_pericom_8port] = { @@ -818,7 +818,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 16, .lsr_mask = UART_LSR_THRE, - .bar0 = 1, + .bar0 = true, .max_ports = 8, }, [param_exar_xr17v352] = { @@ -827,8 +827,8 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 256, .lsr_mask = UART_LSR_THRE, - .bar0 = 1, - .mmio = 1, + .bar0 = true, + .mmio = true, .max_ports = 2, }, [param_exar_xr17v354] = { @@ -837,8 +837,8 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 256, .lsr_mask = UART_LSR_THRE, - .bar0 = 1, - .mmio = 1, + .bar0 = true, + .mmio = true, .max_ports = 4, }, [param_exar_xr17v358] = { @@ -847,8 +847,8 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 256, .lsr_mask = UART_LSR_THRE, - .bar0 = 1, - .mmio = 1, + .bar0 = true, + .mmio = true, .max_ports = 8, }, [param_intel_lpss] = { @@ -857,8 +857,8 @@ static const struct ns16550_config_param __initconst uart_param[] = { .reg_width = 1, .fifo_size = 64, .lsr_mask = UART_LSR_THRE, - .bar0 = 1, - .mmio = 1, + .bar0 = true, + .mmio = true, .max_ports = 1, }, }; -- 2.53.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v5 1/3] ns16550: properly initialize booleans in uart_param[] 2026-06-02 16:13 ` [PATCH v5 1/3] ns16550: properly initialize booleans in uart_param[] Jiaqing Zhao @ 2026-06-02 17:11 ` dmukhin 2026-06-03 5:45 ` Jan Beulich 1 sibling, 0 replies; 6+ messages in thread From: dmukhin @ 2026-06-02 17:11 UTC (permalink / raw) To: Jiaqing Zhao Cc: xen-devel, Andrew Cooper, Anthony PERARD, Jan Beulich, Julien Grall, Michal Orzel, Roger Pau Monné, Stefano Stabellini On Wed, Jun 03, 2026 at 12:13:20AM +0800, Jiaqing Zhao wrote: > .bar0 and .mmio in struct ns16550_config_param are booleans, hence they > should be initialized with "true", not "1". No functional change. > > Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com> Reviewed-by: Denis Mukhin <dmukhin@ford.com> > --- > xen/drivers/char/ns16550.c | 30 +++++++++++++++--------------- > 1 file changed, 15 insertions(+), 15 deletions(-) > > diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c > index 878da27f2e..ed4e29ec25 100644 > --- a/xen/drivers/char/ns16550.c > +++ b/xen/drivers/char/ns16550.c > @@ -758,7 +758,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 16, > .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT), > - .mmio = 1, > + .mmio = true, > .max_ports = 1, > }, > [param_oxford] = { > @@ -768,7 +768,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 16, > .lsr_mask = UART_LSR_THRE, > - .mmio = 1, > + .mmio = true, > .max_ports = 1, /* It can do more, but we would need more custom code.*/ > }, > [param_oxford_2port] = { > @@ -778,7 +778,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 16, > .lsr_mask = UART_LSR_THRE, > - .mmio = 1, > + .mmio = true, > .max_ports = 2, > }, > [param_pericom_1port] = { > @@ -787,7 +787,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 16, > .lsr_mask = UART_LSR_THRE, > - .bar0 = 1, > + .bar0 = true, > .max_ports = 1, > }, > [param_pericom_2port] = { > @@ -796,7 +796,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 16, > .lsr_mask = UART_LSR_THRE, > - .bar0 = 1, > + .bar0 = true, > .max_ports = 2, > }, > /* > @@ -809,7 +809,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 16, > .lsr_mask = UART_LSR_THRE, > - .bar0 = 1, > + .bar0 = true, > .max_ports = 4, > }, > [param_pericom_8port] = { > @@ -818,7 +818,7 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 16, > .lsr_mask = UART_LSR_THRE, > - .bar0 = 1, > + .bar0 = true, > .max_ports = 8, > }, > [param_exar_xr17v352] = { > @@ -827,8 +827,8 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 256, > .lsr_mask = UART_LSR_THRE, > - .bar0 = 1, > - .mmio = 1, > + .bar0 = true, > + .mmio = true, > .max_ports = 2, > }, > [param_exar_xr17v354] = { > @@ -837,8 +837,8 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 256, > .lsr_mask = UART_LSR_THRE, > - .bar0 = 1, > - .mmio = 1, > + .bar0 = true, > + .mmio = true, > .max_ports = 4, > }, > [param_exar_xr17v358] = { > @@ -847,8 +847,8 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 256, > .lsr_mask = UART_LSR_THRE, > - .bar0 = 1, > - .mmio = 1, > + .bar0 = true, > + .mmio = true, > .max_ports = 8, > }, > [param_intel_lpss] = { > @@ -857,8 +857,8 @@ static const struct ns16550_config_param __initconst uart_param[] = { > .reg_width = 1, > .fifo_size = 64, > .lsr_mask = UART_LSR_THRE, > - .bar0 = 1, > - .mmio = 1, > + .bar0 = true, > + .mmio = true, > .max_ports = 1, > }, > }; > -- > 2.53.0 > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v5 1/3] ns16550: properly initialize booleans in uart_param[] 2026-06-02 16:13 ` [PATCH v5 1/3] ns16550: properly initialize booleans in uart_param[] Jiaqing Zhao 2026-06-02 17:11 ` dmukhin @ 2026-06-03 5:45 ` Jan Beulich 1 sibling, 0 replies; 6+ messages in thread From: Jan Beulich @ 2026-06-03 5:45 UTC (permalink / raw) To: Jiaqing Zhao Cc: Andrew Cooper, xen-devel, Anthony PERARD, Julien Grall, Michal Orzel, Roger Pau Monné, Stefano Stabellini On 02.06.2026 18:13, Jiaqing Zhao wrote: > .bar0 and .mmio in struct ns16550_config_param are booleans, hence they > should be initialized with "true", not "1". No functional change. > > Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com> Acked-by: Jan Beulich <jbeulich@suse.com> ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 2/3] ns16550: add support for WCH CH382 serial adapters 2026-06-02 16:13 [PATCH v5 0/3] ns16550: add support for WCH CH382 and ASIX AX99100 Jiaqing Zhao 2026-06-02 16:13 ` [PATCH v5 1/3] ns16550: properly initialize booleans in uart_param[] Jiaqing Zhao @ 2026-06-02 16:13 ` Jiaqing Zhao 2026-06-02 16:13 ` [PATCH v5 3/3] ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller Jiaqing Zhao 2 siblings, 0 replies; 6+ messages in thread From: Jiaqing Zhao @ 2026-06-02 16:13 UTC (permalink / raw) To: xen-devel Cc: Andrew Cooper, Anthony PERARD, Jan Beulich, Julien Grall, Michal Orzel, Roger Pau Monné, Stefano Stabellini, Jiaqing Zhao, Denis Mukhin Add support for the WCH (Nanjing Qinheng Microelectronics Co., Ltd.) CH382 PCIe dual port serial adapter. The CH382 is available in two variants: - CH382 2S [1c00:3253]: 2 serial ports - CH382 2S1P [1c00:3250]: 2 serial ports + 1 parallel port This chip uses IO BAR0, base baud rate 115200, ports starting at offset 0xc0 and spaced 8 bytes apart, and a 256-byte FIFO. [1] [1] https://www.wch-ic.com/downloads/CH382DS1_PDF.html Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com> Reviewed-by: Denis Mukhin <dmukhin@ford.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Acked-by: Roger Pau Monné <roger.pau@citrix.com> --- xen/drivers/char/ns16550.c | 23 +++++++++++++++++++++++ xen/include/xen/pci_ids.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index ed4e29ec25..5a93685da4 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -95,6 +95,7 @@ struct ns16550_config { param_exar_xr17v354, param_exar_xr17v358, param_intel_lpss, + param_wch_ch382, } param; }; @@ -861,6 +862,16 @@ static const struct ns16550_config_param __initconst uart_param[] = { .mmio = true, .max_ports = 1, }, + [param_wch_ch382] = { + .base_baud = 115200, + .first_offset = 0xc0, + .uart_offset = 8, + .reg_width = 1, + .fifo_size = 256, + .lsr_mask = UART_LSR_THRE, + .bar0 = true, + .max_ports = 2, + }, }; static const struct ns16550_config __initconst uart_config[] = @@ -1189,6 +1200,18 @@ static const struct ns16550_config __initconst uart_config[] = .dev_id = 0x7adc, .param = param_intel_lpss }, + /* WCH CH382 2S1P */ + { + .vendor_id = PCI_VENDOR_ID_WCHIC, + .dev_id = 0x3250, + .param = param_wch_ch382 + }, + /* WCH CH382 2S */ + { + .vendor_id = PCI_VENDOR_ID_WCHIC, + .dev_id = 0x3253, + .param = param_wch_ch382 + }, }; static int __init diff --git a/xen/include/xen/pci_ids.h b/xen/include/xen/pci_ids.h index 5884a20b8f..15e938225c 100644 --- a/xen/include/xen/pci_ids.h +++ b/xen/include/xen/pci_ids.h @@ -13,6 +13,8 @@ #define PCI_VENDOR_ID_BROADCOM 0x14e4 +#define PCI_VENDOR_ID_WCHIC 0x1c00 + #define PCI_VENDOR_ID_INTEL 0x8086 #endif /* XEN_PCI_IDS_H */ -- 2.53.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v5 3/3] ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller 2026-06-02 16:13 [PATCH v5 0/3] ns16550: add support for WCH CH382 and ASIX AX99100 Jiaqing Zhao 2026-06-02 16:13 ` [PATCH v5 1/3] ns16550: properly initialize booleans in uart_param[] Jiaqing Zhao 2026-06-02 16:13 ` [PATCH v5 2/3] ns16550: add support for WCH CH382 serial adapters Jiaqing Zhao @ 2026-06-02 16:13 ` Jiaqing Zhao 2 siblings, 0 replies; 6+ messages in thread From: Jiaqing Zhao @ 2026-06-02 16:13 UTC (permalink / raw) To: xen-devel Cc: Andrew Cooper, Anthony PERARD, Jan Beulich, Julien Grall, Michal Orzel, Roger Pau Monné, Stefano Stabellini, Jiaqing Zhao Add a PCI device table entry and matching parameter for the ASIX AX99100 PCIe to Multi-I/O controller [125b:9910]. Each port on the chip is a standalone PCI function, with UART registers on its I/O BAR0. Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Acked-by: Roger Pau Monné <roger.pau@citrix.com> --- xen/drivers/char/ns16550.c | 15 +++++++++++++++ xen/include/xen/pci_ids.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 5a93685da4..1510cf143f 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -96,6 +96,7 @@ struct ns16550_config { param_exar_xr17v358, param_intel_lpss, param_wch_ch382, + param_asix, } param; }; @@ -872,6 +873,14 @@ static const struct ns16550_config_param __initconst uart_param[] = { .bar0 = true, .max_ports = 2, }, + [param_asix] = { + .base_baud = 115200, + .reg_width = 1, + .fifo_size = 256, + .lsr_mask = UART_LSR_THRE, + .bar0 = true, + .max_ports = 1, + }, }; static const struct ns16550_config __initconst uart_config[] = @@ -1212,6 +1221,12 @@ static const struct ns16550_config __initconst uart_config[] = .dev_id = 0x3253, .param = param_wch_ch382 }, + /* ASIX AX99100 PCIe to Multi I/O Controller */ + { + .vendor_id = PCI_VENDOR_ID_ASIX, + .dev_id = 0x9910, + .param = param_asix + }, }; static int __init diff --git a/xen/include/xen/pci_ids.h b/xen/include/xen/pci_ids.h index 15e938225c..fd424ef55d 100644 --- a/xen/include/xen/pci_ids.h +++ b/xen/include/xen/pci_ids.h @@ -5,6 +5,8 @@ #define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_VENDOR_ID_ASIX 0x125b + #define PCI_VENDOR_ID_PERICOM 0x12d8 #define PCI_VENDOR_ID_EXAR 0x13a8 -- 2.53.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-06-03 5:46 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-06-02 16:13 [PATCH v5 0/3] ns16550: add support for WCH CH382 and ASIX AX99100 Jiaqing Zhao 2026-06-02 16:13 ` [PATCH v5 1/3] ns16550: properly initialize booleans in uart_param[] Jiaqing Zhao 2026-06-02 17:11 ` dmukhin 2026-06-03 5:45 ` Jan Beulich 2026-06-02 16:13 ` [PATCH v5 2/3] ns16550: add support for WCH CH382 serial adapters Jiaqing Zhao 2026-06-02 16:13 ` [PATCH v5 3/3] ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller Jiaqing Zhao
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