[PATCH v7 00/15] CMTG enablement

[PATCH v7 00/15] CMTG enablement

[Animesh Manna]

Common mode timing generator (CMTG) support is added NVL onwards.
Enable CMTG which will be needed by other fearure like dynamic dc
state enablement later.

Testing ongoing, currently counters are incrementing as expected.

Animesh Manna (12):
  drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
  drm/i915/cmtg: Set CMTG clock select
  drm/i915/cmtg: Add cmtg transcoder offset in struct _device_info
  drm/i915/cmtg: Set timings for CMTG
  drm/i915/cmtg: Program VRR registers of CMTG
  drm/i915/cmtg: Set transcoder mn for CMTG
  drm/i915/cmtg: Add hook to enable CMTG with sync to port
  drm/i915/cmtg: Add a hook to make eDP transcoder secondary
  drm/i915/cmtg: Add CMTG interrupt handling
  drm/i915/cmtg: Add trigger to enable/disable cmtg
  drm/i915/cmtg: Restore CMTG after DC6 exit
  [Not for Review] Debug patch

Dibin Moolakadan Subrahmanian (3):
  drm/i915/cmtg: Modify existing hook to disable CMTG
  drm/i915/cmtg: Add CMTG HWGB programming
  drm/i915/cmtg: Add CMTG scan line programming

 drivers/gpu/drm/i915/display/intel_cmtg.c     | 318 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  15 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  24 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   5 +
 drivers/gpu/drm/i915/display/intel_display.c  |  42 ++-
 .../drm/i915/display/intel_display_device.c   |  14 +
 .../drm/i915/display/intel_display_device.h   |   2 +-
 .../gpu/drm/i915/display/intel_display_irq.c  |  12 +
 .../drm/i915/display/intel_display_limits.h   |   2 +
 .../drm/i915/display/intel_display_power.c    |  17 +
 .../drm/i915/display/intel_display_power.h    |   2 +
 .../gpu/drm/i915/display/intel_display_regs.h |   6 +
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_vrr.c      |   5 +
 14 files changed, 456 insertions(+), 12 deletions(-)

-- 
2.29.0

[PATCH v7 01/15] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Animesh Manna]

CMTG will be enabled only with DC3co, so add a separate function
intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
DC3co will be enabled in a separate patch.

v2:
- Remove separate flag for DC3co from crtc_state. [Uma, Dibin]

v3:
- Do not access power domain members directly. [Jani]

v4:
- Remove check for DC3co state now. if needed add Dc3co allow check
later once Dc3co patches are merged. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 14 +++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index e1fdc6fe9762..a279f3dcd1ec 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -4,7 +4,6 @@
  */
 
 #include <linux/string_choices.h>
-#include <linux/types.h>
 
 #include <drm/drm_device.h>
 #include <drm/drm_print.h>
@@ -16,6 +15,7 @@
 #include "intel_display_device.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
+#include "intel_display_types.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -185,3 +185,15 @@ void intel_cmtg_sanitize(struct intel_display *display)
 
 	intel_cmtg_disable(display, &cmtg_config);
 }
+
+bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
+	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return true;
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index ba62199adaa2..ed540581738f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -6,8 +6,12 @@
 #ifndef __INTEL_CMTG_H__
 #define __INTEL_CMTG_H__
 
+#include <linux/types.h>
+
 struct intel_display;
+struct intel_crtc_state;
 
 void intel_cmtg_sanitize(struct intel_display *display);
+bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
-- 
2.29.0

Re: [PATCH v7 01/15] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Dibin Moolakadan Subrahmanian]

On 26-05-2026 19:07, Animesh Manna wrote:
> CMTG will be enabled only with DC3co, so add a separate function
> intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
> DC3co will be enabled in a separate patch.
>
> v2:
> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
>
> v3:
> - Do not access power domain members directly. [Jani]
>
> v4:
> - Remove check for DC3co state now. if needed add Dc3co allow check
> later once Dc3co patches are merged. [Uma]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cmtg.c | 14 +++++++++++++-
>   drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
>   2 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e1fdc6fe9762..a279f3dcd1ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -4,7 +4,6 @@
>    */
>   
>   #include <linux/string_choices.h>
> -#include <linux/types.h>
>   
>   #include <drm/drm_device.h>
>   #include <drm/drm_print.h>
> @@ -16,6 +15,7 @@
>   #include "intel_display_device.h"
>   #include "intel_display_power.h"
>   #include "intel_display_regs.h"
> +#include "intel_display_types.h"
>   
>   /**
>    * DOC: Common Primary Timing Generator (CMTG)
> @@ -185,3 +185,15 @@ void intel_cmtg_sanitize(struct intel_display *display)
>   
>   	intel_cmtg_disable(display, &cmtg_config);
>   }
> +
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
> +	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +		return true;
> +
> +	return false;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..ed540581738f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -6,8 +6,12 @@
>   #ifndef __INTEL_CMTG_H__
>   #define __INTEL_CMTG_H__
>   
> +#include <linux/types.h>
> +
>   struct intel_display;
> +struct intel_crtc_state;
>   
>   void intel_cmtg_sanitize(struct intel_display *display);
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
>   
>   #endif /* __INTEL_CMTG_H__ */

It would be helpful to mention the relevant BSpec number
describing the TRANSCODER restriction here.

Reviewed-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

[PATCH v7 02/15] drm/i915/cmtg: Set CMTG clock select

[Animesh Manna]

Program the CMTG Clock Select register based on the transcoder used.

v2:
- Correct mask for PHY B. [Jani]
- Use REG_FIELD_PREP() for enable value. [Dibin]
- Extend cmtg clock select for xe3plpd. [Dibin]

v3:
- CMTG support removed for old platform.

v4:
- Optimize further with else-if. [Uma]
- Correct CMTG_CLK_SEL_B_MASK. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 22 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  5 +++++
 4 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index a279f3dcd1ec..fbc8a4f2b9cb 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -197,3 +197,25 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
 
 	return false;
 }
+
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 clk_sel_clr = 0;
+	u32 clk_sel_set = 0;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	if (cpu_transcoder == TRANSCODER_A) {
+		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
+	} else if (cpu_transcoder == TRANSCODER_B) {
+		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
+	}
+
+	if (clk_sel_set)
+		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index ed540581738f..87092ce6d67b 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 945a35578284..4a80b88d88fd 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -10,8 +10,10 @@
 
 #define CMTG_CLK_SEL			_MMIO(0x46160)
 #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
+#define CMTG_CLK_SELECT_PHYA_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
 #define CMTG_CLK_SEL_A_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
 #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
+#define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
 #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 24a51ab21b55..acf48a25b1d6 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -9,6 +9,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
+#include "intel_cmtg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_display_regs.h"
@@ -3418,10 +3419,14 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
 void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
+
+	if (HAS_LT_PHY(display))
+		intel_cmtg_set_clk_select(crtc_state);
 }
 
 /*
-- 
2.29.0

[PATCH v7 03/15] drm/i915/cmtg: Add cmtg transcoder offset in struct _device_info

[Animesh Manna]

As all cmtg registers offset from base cmtg register is similar to
normal transcoder register, so follow existing way of defining
transcoder register for cmtg as well. Add base CMTG offset in
struct _display_device_info which will be used to derive the actual
register address for platform supporting CMTG.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../gpu/drm/i915/display/intel_display_device.c    | 14 ++++++++++++++
 .../gpu/drm/i915/display/intel_display_device.h    |  2 +-
 .../gpu/drm/i915/display/intel_display_limits.h    |  2 ++
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 69a9f782935c..f17fc2c68472 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -101,6 +101,8 @@ static const struct intel_display_device_info no_display = {};
 #define TRANSCODER_EDP_OFFSET 0x6f000
 #define TRANSCODER_DSI0_OFFSET	0x6b000
 #define TRANSCODER_DSI1_OFFSET	0x6b800
+#define TRANSCODER_CMTG0_OFFSET 0x6F000
+#define TRANSCODER_CMTG1_OFFSET 0x6F100
 
 #define CURSOR_A_OFFSET 0x70080
 #define CURSOR_B_OFFSET 0x700c0
@@ -1352,6 +1354,18 @@ static const struct intel_display_device_info xe2_lpd_display = {
 		BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
 		BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
 	.__runtime_defaults.has_dbuf_overlap_detection = true,
+	.trans_offsets = {
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
+		[TRANSCODER_D] = TRANSCODER_D_OFFSET,
+		[TRANSCODER_CMTG0] = TRANSCODER_CMTG0_OFFSET,
+		[TRANSCODER_CMTG1] = TRANSCODER_CMTG1_OFFSET,
+	},
+	.__runtime_defaults.cpu_transcoder_mask =
+		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
+		BIT(TRANSCODER_CMTG0) | BIT(TRANSCODER_CMTG1),
 };
 
 static const struct intel_display_device_info wcl_display = {
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 12e5a522a299..acb9ca87dda7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -292,7 +292,7 @@ struct intel_display_runtime_info {
 	u32 rawclk_freq;
 
 	u8 pipe_mask;
-	u8 cpu_transcoder_mask;
+	u16 cpu_transcoder_mask;
 	u16 port_mask;
 
 	u8 num_sprites[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
index 453f7b720815..ea89473c177f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -45,6 +45,8 @@ enum transcoder {
 	TRANSCODER_DSI_1,
 	TRANSCODER_DSI_A = TRANSCODER_DSI_0,	/* legacy DSI */
 	TRANSCODER_DSI_C = TRANSCODER_DSI_1,	/* legacy DSI */
+	TRANSCODER_CMTG0,
+	TRANSCODER_CMTG1,
 
 	I915_MAX_TRANSCODERS
 };
-- 
2.29.0

[PATCH v7 04/15] drm/i915/cmtg: Set timings for CMTG

[Animesh Manna]

Timing registers are separate for CMTG, read transcoder register
and program cmtg transcoder with those values.

v2:
- Use sw state instead of reading directly from hardware. [Jani]
- Move set_timing later after encoder enable. [Dibin]

v3:
- Replace id with trans. [Jani]
- Program cmtg set_timing() along with primary transcoder timing.

v4:
- Use _MMIO_TRANS() for cmtg registers instead of direct
multiplication. [Jani]

v5:
- Modify register definition approach and match existing
transcoder definition. [Ville]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c    | 74 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display.c |  4 ++
 3 files changed, 79 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index fbc8a4f2b9cb..0e730afbb4ab 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -219,3 +219,77 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
 	if (clk_sel_set)
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
+
+static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
+{
+	switch (cpu_transcoder) {
+	case TRANSCODER_A:
+		return TRANSCODER_CMTG0;
+	case TRANSCODER_B:
+		return TRANSCODER_CMTG1;
+	default:
+		return INVALID_TRANSCODER;
+	}
+}
+
+void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
+
+	/*
+	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
+	 * bits are not required. Since the support for these bits is going to
+	 * be deprecated in upcoming platforms, avoid writing these bits for the
+	 * platforms that do not use legacy Timing Generator.
+	 */
+	crtc_vtotal = 1;
+
+	/*
+	 * VBLANK_START not used by hw, just clear it
+	 * to make it stand out in register dumps.
+	 */
+	crtc_vblank_start = 1;
+
+	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
+
+	if (lrr) {
+		intel_de_write(display, TRANS_SET_CONTEXT_LATENCY(display, cmtg_transcoder),
+			       crtc_state->set_context_latency);
+		intel_de_write(display, TRANS_VBLANK(display, cmtg_transcoder),
+			       VBLANK_START(crtc_vblank_start - 1) |
+			       VBLANK_END(crtc_vblank_end - 1));
+		intel_de_write(display, TRANS_VTOTAL(display, cmtg_transcoder),
+			       VACTIVE(crtc_vdisplay - 1) |
+			       VTOTAL(crtc_vtotal - 1));
+		return;
+	}
+
+	intel_de_write(display, TRANS_HTOTAL(display, cmtg_transcoder),
+		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
+		       HTOTAL(adjusted_mode->crtc_htotal - 1));
+	intel_de_write(display, TRANS_HBLANK(display, cmtg_transcoder),
+		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
+		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
+	intel_de_write(display, TRANS_HSYNC(display, cmtg_transcoder),
+		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
+		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
+	intel_de_write(display, TRANS_VTOTAL(display, cmtg_transcoder),
+		       VACTIVE(crtc_vdisplay - 1) |
+		       VTOTAL(crtc_vtotal - 1));
+	intel_de_write(display, TRANS_VBLANK(display, cmtg_transcoder),
+		       VBLANK_START(crtc_vblank_start - 1) |
+		       VBLANK_END(crtc_vblank_end - 1));
+	intel_de_write(display, TRANS_VSYNC(display, cmtg_transcoder),
+		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
+		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
+	intel_de_write(display, TRANS_SET_CONTEXT_LATENCY(display, cmtg_transcoder),
+		       crtc_state->set_context_latency);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 87092ce6d67b..53a44f505dd2 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6c8935f69db1..f8bcd1fcddca 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -60,6 +60,7 @@
 #include "intel_bw.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
+#include "intel_cmtg.h"
 #include "intel_color.h"
 #include "intel_crt.h"
 #include "intel_crtc.h"
@@ -2753,6 +2754,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
 			       crtc_state->min_hblank);
 	}
+
+	intel_cmtg_set_timings(crtc_state, false);
 }
 
 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
@@ -2814,6 +2817,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 		       VACTIVE(crtc_vdisplay - 1) |
 		       VTOTAL(crtc_vtotal - 1));
 
+	intel_cmtg_set_timings(crtc_state, true);
 	intel_vrr_set_fixed_rr_timings(crtc_state);
 	intel_vrr_transcoder_enable(crtc_state);
 }
-- 
2.29.0

Re: [PATCH v7 04/15] drm/i915/cmtg: Set timings for CMTG

[Ville Syrjälä]

On Tue, May 26, 2026 at 07:08:00PM +0530, Animesh Manna wrote:
> Timing registers are separate for CMTG, read transcoder register
> and program cmtg transcoder with those values.
> 
> v2:
> - Use sw state instead of reading directly from hardware. [Jani]
> - Move set_timing later after encoder enable. [Dibin]
> 
> v3:
> - Replace id with trans. [Jani]
> - Program cmtg set_timing() along with primary transcoder timing.
> 
> v4:
> - Use _MMIO_TRANS() for cmtg registers instead of direct
> multiplication. [Jani]
> 
> v5:
> - Modify register definition approach and match existing
> transcoder definition. [Ville]
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c    | 74 ++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_display.c |  4 ++
>  3 files changed, 79 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index fbc8a4f2b9cb..0e730afbb4ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -219,3 +219,77 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
>  	if (clk_sel_set)
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
>  }
> +
> +static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
> +{
> +	switch (cpu_transcoder) {
> +	case TRANSCODER_A:
> +		return TRANSCODER_CMTG0;
> +	case TRANSCODER_B:
> +		return TRANSCODER_CMTG1;
> +	default:
> +		return INVALID_TRANSCODER;
> +	}
> +}
> +
> +void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
> +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> +
> +	/*
> +	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> +	 * bits are not required. Since the support for these bits is going to
> +	 * be deprecated in upcoming platforms, avoid writing these bits for the
> +	 * platforms that do not use legacy Timing Generator.
> +	 */
> +	crtc_vtotal = 1;
> +
> +	/*
> +	 * VBLANK_START not used by hw, just clear it
> +	 * to make it stand out in register dumps.
> +	 */
> +	crtc_vblank_start = 1;
> +
> +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> +
> +	if (lrr) {
> +		intel_de_write(display, TRANS_SET_CONTEXT_LATENCY(display, cmtg_transcoder),
> +			       crtc_state->set_context_latency);
> +		intel_de_write(display, TRANS_VBLANK(display, cmtg_transcoder),
> +			       VBLANK_START(crtc_vblank_start - 1) |
> +			       VBLANK_END(crtc_vblank_end - 1));
> +		intel_de_write(display, TRANS_VTOTAL(display, cmtg_transcoder),
> +			       VACTIVE(crtc_vdisplay - 1) |
> +			       VTOTAL(crtc_vtotal - 1));
> +		return;
> +	}
> +
> +	intel_de_write(display, TRANS_HTOTAL(display, cmtg_transcoder),
> +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> +	intel_de_write(display, TRANS_HBLANK(display, cmtg_transcoder),
> +		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> +		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> +	intel_de_write(display, TRANS_HSYNC(display, cmtg_transcoder),
> +		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> +		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> +	intel_de_write(display, TRANS_VTOTAL(display, cmtg_transcoder),
> +		       VACTIVE(crtc_vdisplay - 1) |
> +		       VTOTAL(crtc_vtotal - 1));
> +	intel_de_write(display, TRANS_VBLANK(display, cmtg_transcoder),
> +		       VBLANK_START(crtc_vblank_start - 1) |
> +		       VBLANK_END(crtc_vblank_end - 1));
> +	intel_de_write(display, TRANS_VSYNC(display, cmtg_transcoder),
> +		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> +		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> +	intel_de_write(display, TRANS_SET_CONTEXT_LATENCY(display, cmtg_transcoder),
> +		       crtc_state->set_context_latency);
> +}

We already have functions to configure the timing registers. Why can't
we just reuse those (as in pass the transcoder from the caller)?

> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 87092ce6d67b..53a44f505dd2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
>  
> +void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
>  void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_sanitize(struct intel_display *display);
>  bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6c8935f69db1..f8bcd1fcddca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -60,6 +60,7 @@
>  #include "intel_bw.h"
>  #include "intel_cdclk.h"
>  #include "intel_clock_gating.h"
> +#include "intel_cmtg.h"
>  #include "intel_color.h"
>  #include "intel_crt.h"
>  #include "intel_crtc.h"
> @@ -2753,6 +2754,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
>  			       crtc_state->min_hblank);
>  	}
> +
> +	intel_cmtg_set_timings(crtc_state, false);
>  }
>  
>  static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> @@ -2814,6 +2817,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>  		       VACTIVE(crtc_vdisplay - 1) |
>  		       VTOTAL(crtc_vtotal - 1));
>  
> +	intel_cmtg_set_timings(crtc_state, true);
>  	intel_vrr_set_fixed_rr_timings(crtc_state);
>  	intel_vrr_transcoder_enable(crtc_state);
>  }
> -- 
> 2.29.0

-- 
Ville Syrjälä
Intel

RE: [PATCH v7 04/15] drm/i915/cmtg: Set timings for CMTG

[Manna, Animesh]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, May 29, 2026 4:29 PM
> To: Manna, Animesh <animesh.manna@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Shankar,
> Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [PATCH v7 04/15] drm/i915/cmtg: Set timings for CMTG
> 
> On Tue, May 26, 2026 at 07:08:00PM +0530, Animesh Manna wrote:
> > Timing registers are separate for CMTG, read transcoder register and
> > program cmtg transcoder with those values.
> >
> > v2:
> > - Use sw state instead of reading directly from hardware. [Jani]
> > - Move set_timing later after encoder enable. [Dibin]
> >
> > v3:
> > - Replace id with trans. [Jani]
> > - Program cmtg set_timing() along with primary transcoder timing.
> >
> > v4:
> > - Use _MMIO_TRANS() for cmtg registers instead of direct
> > multiplication. [Jani]
> >
> > v5:
> > - Modify register definition approach and match existing transcoder
> > definition. [Ville]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cmtg.c    | 74 ++++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
> >  drivers/gpu/drm/i915/display/intel_display.c |  4 ++
> >  3 files changed, 79 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index fbc8a4f2b9cb..0e730afbb4ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -219,3 +219,77 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
> >  	if (clk_sel_set)
> >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set);  }
> > +
> > +static inline enum transcoder to_cmtg_transcoder(enum transcoder
> > +cpu_transcoder) {
> > +	switch (cpu_transcoder) {
> > +	case TRANSCODER_A:
> > +		return TRANSCODER_CMTG0;
> > +	case TRANSCODER_B:
> > +		return TRANSCODER_CMTG1;
> > +	default:
> > +		return INVALID_TRANSCODER;
> > +	}
> > +}
> > +
> > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > +*crtc_state, bool lrr) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> > +	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state-
> >cpu_transcoder);
> > +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> > +
> > +	if (!intel_cmtg_is_allowed(crtc_state))
> > +		return;
> > +
> > +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > +
> > +	/*
> > +	 * For platforms that always use VRR Timing Generator, the
> VTOTAL.Vtotal
> > +	 * bits are not required. Since the support for these bits is going to
> > +	 * be deprecated in upcoming platforms, avoid writing these bits for
> the
> > +	 * platforms that do not use legacy Timing Generator.
> > +	 */
> > +	crtc_vtotal = 1;
> > +
> > +	/*
> > +	 * VBLANK_START not used by hw, just clear it
> > +	 * to make it stand out in register dumps.
> > +	 */
> > +	crtc_vblank_start = 1;
> > +
> > +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > +
> > +	if (lrr) {
> > +		intel_de_write(display,
> TRANS_SET_CONTEXT_LATENCY(display, cmtg_transcoder),
> > +			       crtc_state->set_context_latency);
> > +		intel_de_write(display, TRANS_VBLANK(display,
> cmtg_transcoder),
> > +			       VBLANK_START(crtc_vblank_start - 1) |
> > +			       VBLANK_END(crtc_vblank_end - 1));
> > +		intel_de_write(display, TRANS_VTOTAL(display,
> cmtg_transcoder),
> > +			       VACTIVE(crtc_vdisplay - 1) |
> > +			       VTOTAL(crtc_vtotal - 1));
> > +		return;
> > +	}
> > +
> > +	intel_de_write(display, TRANS_HTOTAL(display, cmtg_transcoder),
> > +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> > +	intel_de_write(display, TRANS_HBLANK(display, cmtg_transcoder),
> > +		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> > +		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> > +	intel_de_write(display, TRANS_HSYNC(display, cmtg_transcoder),
> > +		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> > +		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> > +	intel_de_write(display, TRANS_VTOTAL(display, cmtg_transcoder),
> > +		       VACTIVE(crtc_vdisplay - 1) |
> > +		       VTOTAL(crtc_vtotal - 1));
> > +	intel_de_write(display, TRANS_VBLANK(display, cmtg_transcoder),
> > +		       VBLANK_START(crtc_vblank_start - 1) |
> > +		       VBLANK_END(crtc_vblank_end - 1));
> > +	intel_de_write(display, TRANS_VSYNC(display, cmtg_transcoder),
> > +		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> > +		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> > +	intel_de_write(display, TRANS_SET_CONTEXT_LATENCY(display,
> cmtg_transcoder),
> > +		       crtc_state->set_context_latency); }
> 
> We already have functions to configure the timing registers. Why can't we
> just reuse those (as in pass the transcoder from the caller)?

Due to following reasons did not reuse, 
1. CMTG will be enabled very specific case like single EDP on pipe-A/pipe-B during psr2/lobf/pr-alpm.
2. Function prototype of existing functions to configure the timing registers need to be changed.
3. Need condition check for DP_MIN_HBLANK_CTL register programming.
4. Two version of set-timings - intel_set_transcoder_timings_lrr() and intel_set_transcoder_timings().
5. May overload intel_display.c.

I can try to reuse If you have strong objections on current implementation, please let me know.
Also is it only for timing registers or same needed for link-m/n and vrr registers.

Regards,
Animesh
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index 87092ce6d67b..53a44f505dd2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -11,6 +11,7 @@
> >  struct intel_display;
> >  struct intel_crtc_state;
> >
> > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > +*crtc_state, bool lrr);
> >  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > *crtc_state);  void intel_cmtg_sanitize(struct intel_display
> > *display);  bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > *crtc_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 6c8935f69db1..f8bcd1fcddca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -60,6 +60,7 @@
> >  #include "intel_bw.h"
> >  #include "intel_cdclk.h"
> >  #include "intel_clock_gating.h"
> > +#include "intel_cmtg.h"
> >  #include "intel_color.h"
> >  #include "intel_crt.h"
> >  #include "intel_crtc.h"
> > @@ -2753,6 +2754,8 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
> >  		intel_de_write(display,
> DP_MIN_HBLANK_CTL(cpu_transcoder),
> >  			       crtc_state->min_hblank);
> >  	}
> > +
> > +	intel_cmtg_set_timings(crtc_state, false);
> >  }
> >
> >  static void intel_set_transcoder_timings_lrr(const struct
> > intel_crtc_state *crtc_state) @@ -2814,6 +2817,7 @@ static void
> intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
> >  		       VACTIVE(crtc_vdisplay - 1) |
> >  		       VTOTAL(crtc_vtotal - 1));
> >
> > +	intel_cmtg_set_timings(crtc_state, true);
> >  	intel_vrr_set_fixed_rr_timings(crtc_state);
> >  	intel_vrr_transcoder_enable(crtc_state);
> >  }
> > --
> > 2.29.0
> 
> --
> Ville Syrjälä
> Intel

RE: [PATCH v7 04/15] drm/i915/cmtg: Set timings for CMTG

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Monday, June 1, 2026 8:02 PM
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Shankar, Uma
> <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: RE: [PATCH v7 04/15] drm/i915/cmtg: Set timings for CMTG
> 
> 
> 
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Friday, May 29, 2026 4:29 PM
> > To: Manna, Animesh <animesh.manna@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org;
> > Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>; Nikula, Jani
> > <jani.nikula@intel.com>
> > Subject: Re: [PATCH v7 04/15] drm/i915/cmtg: Set timings for CMTG
> >
> > On Tue, May 26, 2026 at 07:08:00PM +0530, Animesh Manna wrote:
> > > Timing registers are separate for CMTG, read transcoder register and
> > > program cmtg transcoder with those values.
> > >
> > > v2:
> > > - Use sw state instead of reading directly from hardware. [Jani]
> > > - Move set_timing later after encoder enable. [Dibin]
> > >
> > > v3:
> > > - Replace id with trans. [Jani]
> > > - Program cmtg set_timing() along with primary transcoder timing.
> > >
> > > v4:
> > > - Use _MMIO_TRANS() for cmtg registers instead of direct
> > > multiplication. [Jani]
> > >
> > > v5:
> > > - Modify register definition approach and match existing transcoder
> > > definition. [Ville]
> > >
> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_cmtg.c    | 74 ++++++++++++++++++++
> > >  drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
> > >  drivers/gpu/drm/i915/display/intel_display.c |  4 ++
> > >  3 files changed, 79 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > index fbc8a4f2b9cb..0e730afbb4ab 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > @@ -219,3 +219,77 @@ void intel_cmtg_set_clk_select(const struct
> > intel_crtc_state *crtc_state)
> > >  	if (clk_sel_set)
> > >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> > clk_sel_set);  }
> > > +
> > > +static inline enum transcoder to_cmtg_transcoder(enum transcoder
> > > +cpu_transcoder) {
> > > +	switch (cpu_transcoder) {
> > > +	case TRANSCODER_A:
> > > +		return TRANSCODER_CMTG0;
> > > +	case TRANSCODER_B:
> > > +		return TRANSCODER_CMTG1;
> > > +	default:
> > > +		return INVALID_TRANSCODER;
> > > +	}
> > > +}
> > > +
> > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > +*crtc_state, bool lrr) {
> > > +	struct intel_display *display = to_intel_display(crtc_state);
> > > +	const struct drm_display_mode *adjusted_mode = &crtc_state-
> > >hw.adjusted_mode;
> > > +	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state-
> > >cpu_transcoder);
> > > +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start,
> > > +crtc_vblank_end;
> > > +
> > > +	if (!intel_cmtg_is_allowed(crtc_state))
> > > +		return;
> > > +
> > > +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > > +
> > > +	/*
> > > +	 * For platforms that always use VRR Timing Generator, the
> > VTOTAL.Vtotal
> > > +	 * bits are not required. Since the support for these bits is going to
> > > +	 * be deprecated in upcoming platforms, avoid writing these bits
> > > +for
> > the
> > > +	 * platforms that do not use legacy Timing Generator.
> > > +	 */
> > > +	crtc_vtotal = 1;
> > > +
> > > +	/*
> > > +	 * VBLANK_START not used by hw, just clear it
> > > +	 * to make it stand out in register dumps.
> > > +	 */
> > > +	crtc_vblank_start = 1;
> > > +
> > > +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > > +
> > > +	if (lrr) {
> > > +		intel_de_write(display,
> > TRANS_SET_CONTEXT_LATENCY(display, cmtg_transcoder),
> > > +			       crtc_state->set_context_latency);
> > > +		intel_de_write(display, TRANS_VBLANK(display,
> > cmtg_transcoder),
> > > +			       VBLANK_START(crtc_vblank_start - 1) |
> > > +			       VBLANK_END(crtc_vblank_end - 1));
> > > +		intel_de_write(display, TRANS_VTOTAL(display,
> > cmtg_transcoder),
> > > +			       VACTIVE(crtc_vdisplay - 1) |
> > > +			       VTOTAL(crtc_vtotal - 1));
> > > +		return;
> > > +	}
> > > +
> > > +	intel_de_write(display, TRANS_HTOTAL(display, cmtg_transcoder),
> > > +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > > +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> > > +	intel_de_write(display, TRANS_HBLANK(display, cmtg_transcoder),
> > > +		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> > > +		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> > > +	intel_de_write(display, TRANS_HSYNC(display, cmtg_transcoder),
> > > +		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> > > +		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> > > +	intel_de_write(display, TRANS_VTOTAL(display, cmtg_transcoder),
> > > +		       VACTIVE(crtc_vdisplay - 1) |
> > > +		       VTOTAL(crtc_vtotal - 1));
> > > +	intel_de_write(display, TRANS_VBLANK(display, cmtg_transcoder),
> > > +		       VBLANK_START(crtc_vblank_start - 1) |
> > > +		       VBLANK_END(crtc_vblank_end - 1));
> > > +	intel_de_write(display, TRANS_VSYNC(display, cmtg_transcoder),
> > > +		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> > > +		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> > > +	intel_de_write(display, TRANS_SET_CONTEXT_LATENCY(display,
> > cmtg_transcoder),
> > > +		       crtc_state->set_context_latency); }
> >
> > We already have functions to configure the timing registers. Why can't
> > we just reuse those (as in pass the transcoder from the caller)?
> 
> Due to following reasons did not reuse, 1. CMTG will be enabled very specific
> case like single EDP on pipe-A/pipe-B during psr2/lobf/pr-alpm.
> 2. Function prototype of existing functions to configure the timing registers need to
> be changed.
> 3. Need condition check for DP_MIN_HBLANK_CTL register programming.
> 4. Two version of set-timings - intel_set_transcoder_timings_lrr() and
> intel_set_transcoder_timings().
> 5. May overload intel_display.c.
> 
> I can try to reuse If you have strong objections on current implementation, please
> let me know.
> Also is it only for timing registers or same needed for link-m/n and vrr registers.

Code duplication for timing registers can be avoided by using a common helper. Abstract the
logic in helper and use for both CMTG and regular Timing Generator.

Regards,
Uma Shankar

> Regards,
> Animesh
> >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > index 87092ce6d67b..53a44f505dd2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > @@ -11,6 +11,7 @@
> > >  struct intel_display;
> > >  struct intel_crtc_state;
> > >
> > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > +*crtc_state, bool lrr);
> > >  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > > *crtc_state);  void intel_cmtg_sanitize(struct intel_display
> > > *display);  bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > > *crtc_state); diff --git
> > > a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 6c8935f69db1..f8bcd1fcddca 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -60,6 +60,7 @@
> > >  #include "intel_bw.h"
> > >  #include "intel_cdclk.h"
> > >  #include "intel_clock_gating.h"
> > > +#include "intel_cmtg.h"
> > >  #include "intel_color.h"
> > >  #include "intel_crt.h"
> > >  #include "intel_crtc.h"
> > > @@ -2753,6 +2754,8 @@ static void intel_set_transcoder_timings(const
> > struct intel_crtc_state *crtc_sta
> > >  		intel_de_write(display,
> > DP_MIN_HBLANK_CTL(cpu_transcoder),
> > >  			       crtc_state->min_hblank);
> > >  	}
> > > +
> > > +	intel_cmtg_set_timings(crtc_state, false);
> > >  }
> > >
> > >  static void intel_set_transcoder_timings_lrr(const struct
> > > intel_crtc_state *crtc_state) @@ -2814,6 +2817,7 @@ static void
> > intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
> > >  		       VACTIVE(crtc_vdisplay - 1) |
> > >  		       VTOTAL(crtc_vtotal - 1));
> > >
> > > +	intel_cmtg_set_timings(crtc_state, true);
> > >  	intel_vrr_set_fixed_rr_timings(crtc_state);
> > >  	intel_vrr_transcoder_enable(crtc_state);
> > >  }
> > > --
> > > 2.29.0
> >
> > --
> > Ville Syrjälä
> > Intel

[PATCH v7 05/15] drm/i915/cmtg: Program VRR registers of CMTG

[Animesh Manna]

Program the VRR registers of CMTG, as the VRR timing generator
will always be enabled for NVL.

v2: Use sw state instead of reading from hardware. [Jani]
v3: Program cmtg vrr control and timing registers along with
vrr transcoder registers.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 34 +++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h |  2 ++
 drivers/gpu/drm/i915/display/intel_vrr.c  |  5 ++++
 3 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 0e730afbb4ab..fc8d85fcbc4a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -16,6 +16,7 @@
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_vrr_regs.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -293,3 +294,36 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 	intel_de_write(display, TRANS_SET_CONTEXT_LATENCY(display, cmtg_transcoder),
 		       crtc_state->set_context_latency);
 }
+
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_write(display, TRANS_VRR_VMIN(display, cmtg_transcoder), crtc_state->vrr.vmin - 1);
+	intel_de_write(display, TRANS_VRR_VMAX(display, cmtg_transcoder), crtc_state->vrr.vmax - 1);
+	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cmtg_transcoder),
+		       crtc_state->vrr.flipline - 1);
+}
+
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+	u32 vrr_ctl;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN |
+		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
+
+	/* TODO: The code below may need to be revisited once CMRR is enabled */
+	if (crtc_state->cmrr.enable)
+		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 53a44f505dd2..c92e3a62ff0d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,8 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1b09992ce9fd..1260ceb7958e 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -7,6 +7,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
+#include "intel_cmtg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
@@ -334,6 +335,8 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
 		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
+
+	intel_cmtg_set_vrr_timings(crtc_state);
 }
 
 static
@@ -932,6 +935,8 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
+
+	intel_cmtg_set_vrr_ctl(crtc_state);
 }
 
 static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
-- 
2.29.0

[PATCH v7 06/15] drm/i915/cmtg: Set transcoder mn for CMTG

[Animesh Manna]

Program CMTG link M/N.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c    | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display.c |  5 ++++-
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index fc8d85fcbc4a..b66894407e6a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -327,3 +327,16 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
 }
+
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+	const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_write(display, PIPE_LINK_M1(display, cmtg_transcoder), m_n->link_m);
+	intel_de_write(display, PIPE_LINK_N1(display, cmtg_transcoder), m_n->link_n);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index c92e3a62ff0d..6796eb727eef 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f8bcd1fcddca..354eca79bac0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1615,6 +1615,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 					       &crtc_state->dp_m2_n2);
 	}
 
+	intel_cmtg_set_m_n(crtc_state);
 	intel_set_transcoder_timings(crtc_state);
 
 	if (cpu_transcoder != TRANSCODER_EDP)
@@ -6662,9 +6663,11 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
 	    display->platform.broadwell || display->platform.haswell)
 		hsw_set_linetime_wm(new_crtc_state);
 
-	if (new_crtc_state->update_m_n)
+	if (new_crtc_state->update_m_n) {
 		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
 					       &new_crtc_state->dp_m_n);
+		intel_cmtg_set_m_n(new_crtc_state);
+	}
 
 	if (new_crtc_state->update_lrr)
 		intel_set_transcoder_timings_lrr(new_crtc_state);
-- 
2.29.0

[PATCH v7 07/15] drm/i915/cmtg: Add hook to enable CMTG with sync to port

[Animesh Manna]

Add a hook to enable CMTG by programming CMTG CTL with Sync to Port.
When CMTG starts running, the Sync to Port bit will be cleared. Add
a wait to check its running status and trigger WARN_ON() on timeout.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 27 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  7 +++--
 3 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index b66894407e6a..63e430f7e63b 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -104,11 +104,11 @@ static void intel_cmtg_get_config(struct intel_display *display,
 {
 	u32 val;
 
-	val = intel_de_read(display, TRANS_CMTG_CTL_A);
+	val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_A));
 	cmtg_config->cmtg_a_enable = val & CMTG_ENABLE;
 
 	if (intel_cmtg_has_cmtg_b(display)) {
-		val = intel_de_read(display, TRANS_CMTG_CTL_B);
+		val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_B));
 		cmtg_config->cmtg_b_enable = val & CMTG_ENABLE;
 	}
 
@@ -141,14 +141,14 @@ static void intel_cmtg_disable(struct intel_display *display,
 
 	if (cmtg_config->cmtg_a_enable) {
 		drm_dbg_kms(display->drm, "Disabling CMTG A\n");
-		intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0);
+		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_A), CMTG_ENABLE, 0);
 		clk_sel_clr |= CMTG_CLK_SEL_A_MASK;
 		clk_sel_set |= CMTG_CLK_SEL_A_DISABLED;
 	}
 
 	if (cmtg_config->cmtg_b_enable) {
 		drm_dbg_kms(display->drm, "Disabling CMTG B\n");
-		intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0);
+		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_B), CMTG_ENABLE, 0);
 		clk_sel_clr |= CMTG_CLK_SEL_B_MASK;
 		clk_sel_set |= CMTG_CLK_SEL_B_DISABLED;
 	}
@@ -340,3 +340,22 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, PIPE_LINK_M1(display, cmtg_transcoder), m_n->link_m);
 	intel_de_write(display, PIPE_LINK_N1(display, cmtg_transcoder), m_n->link_n);
 }
+
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 cmtg_ctl;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
+				       CMTG_SYNC_TO_PORT, 50)) {
+		drm_WARN(display->drm, 1, "CMTG: %s enable timeout\n",
+			 transcoder_name(cpu_transcoder));
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 6796eb727eef..64ff6a19948a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 4a80b88d88fd..a93236bf7b75 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -16,8 +16,11 @@
 #define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
-#define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
-#define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
+#define _TRANS_CMTG_CTL_A		0x6fa88
+#define _TRANS_CMTG_CTL_B		0x6fb88
+#define TRANS_CMTG_CTL(trans)		_MMIO_TRANS((trans), \
+						    _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
 #define  CMTG_ENABLE			REG_BIT(31)
+#define  CMTG_SYNC_TO_PORT		REG_BIT(29)
 
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

[PATCH v7 08/15] drm/i915/cmtg: Add a hook to make eDP transcoder secondary

[Animesh Manna]

Program DDI_FUNC_CTL2 to configure the eDP transcoder as secondary
to the CMTG transcoder.

v2:
- Update commit header to be more clear. [Uma]

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 63e430f7e63b..34715280d65d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -359,3 +359,16 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 			 transcoder_name(cpu_transcoder));
 	}
 }
+
+void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
+
+	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 64ff6a19948a..12abbafa7d08 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
-- 
2.29.0

Re: [PATCH v7 08/15] drm/i915/cmtg: Add a hook to make eDP transcoder secondary

[Dibin Moolakadan Subrahmanian]

On 26-05-2026 19:08, Animesh Manna wrote:
> Program DDI_FUNC_CTL2 to configure the eDP transcoder as secondary
> to the CMTG transcoder.
>
> v2:
> - Update commit header to be more clear. [Uma]
>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
>   drivers/gpu/drm/i915/display/intel_cmtg.h |  1 +
>   2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 63e430f7e63b..34715280d65d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -359,3 +359,16 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
>   			 transcoder_name(cpu_transcoder));
>   	}
>   }
> +
> +void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
> +
> +	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 64ff6a19948a..12abbafa7d08 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>   struct intel_display;
>   struct intel_crtc_state;
>   
> +void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
>   void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
>   void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
>   void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);

Looks good to me.
Reviewed-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Re: [PATCH v7 08/15] drm/i915/cmtg: Add a hook to make eDP transcoder secondary

[Ville Syrjälä]

On Tue, May 26, 2026 at 07:08:04PM +0530, Animesh Manna wrote:
> Program DDI_FUNC_CTL2 to configure the eDP transcoder as secondary
> to the CMTG transcoder.
> 
> v2:
> - Update commit header to be more clear. [Uma]
> 
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h |  1 +
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 63e430f7e63b..34715280d65d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -359,3 +359,16 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
>  			 transcoder_name(cpu_transcoder));
>  	}
>  }
> +
> +void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);

We already have a place where we configure TRANS_DDI_FUNC_CTL2.
Why is this not there?

> +
> +	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 64ff6a19948a..12abbafa7d08 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
>  
> +void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
> -- 
> 2.29.0

-- 
Ville Syrjälä
Intel

RE: [PATCH v7 08/15] drm/i915/cmtg: Add a hook to make eDP transcoder secondary

[Manna, Animesh]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, May 29, 2026 4:22 PM
> To: Manna, Animesh <animesh.manna@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Shankar,
> Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [PATCH v7 08/15] drm/i915/cmtg: Add a hook to make eDP
> transcoder secondary
> 
> On Tue, May 26, 2026 at 07:08:04PM +0530, Animesh Manna wrote:
> > Program DDI_FUNC_CTL2 to configure the eDP transcoder as secondary to
> > the CMTG transcoder.
> >
> > v2:
> > - Update commit header to be more clear. [Uma]
> >
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
> > drivers/gpu/drm/i915/display/intel_cmtg.h |  1 +
> >  2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index 63e430f7e63b..34715280d65d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -359,3 +359,16 @@ void intel_cmtg_enable_sync(const struct
> intel_crtc_state *crtc_state)
> >  			 transcoder_name(cpu_transcoder));
> >  	}
> >  }
> > +
> > +void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > +	if (!intel_cmtg_is_allowed(crtc_state))
> > +		return;
> > +
> > +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
> > +0, CMTG_SECONDARY_MODE);
> 
> We already have a place where we configure TRANS_DDI_FUNC_CTL2.
> Why is this not there?

The idea here to enable primary eDP transcoder first and then enable CMTG. Later make eDP transcoder secondary to CMTG.
So not added in intel_ddi_enable().

Regards,
Animesh
 
> 
> > +
> > +	drm_dbg_kms(display->drm, "CMTG: %s enabled\n",
> > +transcoder_name(cpu_transcoder)); }
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index 64ff6a19948a..12abbafa7d08 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -11,6 +11,7 @@
> >  struct intel_display;
> >  struct intel_crtc_state;
> >
> > +void intel_cmtg_enable_ddi(const struct intel_crtc_state
> > +*crtc_state);
> >  void intel_cmtg_enable_sync(const struct intel_crtc_state
> > *crtc_state);  void intel_cmtg_set_m_n(const struct intel_crtc_state
> > *crtc_state);  void intel_cmtg_set_vrr_timings(const struct
> > intel_crtc_state *crtc_state);
> > --
> > 2.29.0
> 
> --
> Ville Syrjälä
> Intel

[PATCH v7 09/15] drm/i915/cmtg: Modify existing hook to disable CMTG

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Earlier cmtg_disable() used to disable all instances of CMTG
which cannot handle individual request for specific CMTG instance.
Introduce cmtg_disable_all() which will disable all cmtg instances
and cmtg_disable() only disable specific instance.

v2:
- Use intel_de_rmw to simplify. [Uma]

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 60 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
 3 files changed, 47 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 34715280d65d..643e2e846d25 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -82,6 +82,18 @@ static void intel_cmtg_dump_config(struct intel_display *display,
 		    str_yes_no(cmtg_config->trans_b_secondary));
 }
 
+static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
+{
+	switch (cpu_transcoder) {
+	case TRANSCODER_A:
+		return TRANSCODER_CMTG0;
+	case TRANSCODER_B:
+		return TRANSCODER_CMTG1;
+	default:
+		return INVALID_TRANSCODER;
+	}
+}
+
 static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,
 					       enum transcoder trans)
 {
@@ -125,8 +137,8 @@ static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
 	return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary;
 }
 
-static void intel_cmtg_disable(struct intel_display *display,
-			       struct intel_cmtg_config *cmtg_config)
+static void intel_cmtg_disable_all(struct intel_display *display,
+				   struct intel_cmtg_config *cmtg_config)
 {
 	u32 clk_sel_clr = 0;
 	u32 clk_sel_set = 0;
@@ -157,6 +169,36 @@ static void intel_cmtg_disable(struct intel_display *display,
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+	u32 clk_sel_clr = 0;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
+		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
+		     CMTG_SECONDARY_MODE, 0);
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
+
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
+		drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
+			 transcoder_name(cpu_transcoder));
+		return;
+	}
+
+	clk_sel_clr = cpu_transcoder == TRANSCODER_A ? CMTG_CLK_SEL_A_MASK : CMTG_CLK_SEL_B_MASK;
+	intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, 0);
+
+	drm_dbg_kms(display->drm, "CMTG: %s disabled\n", transcoder_name(cpu_transcoder));
+}
+
 /*
  * Read out CMTG configuration and, on platforms that allow disabling it without
  * a modeset, do it.
@@ -184,7 +226,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
 	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
 		return;
 
-	intel_cmtg_disable(display, &cmtg_config);
+	intel_cmtg_disable_all(display, &cmtg_config);
 }
 
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
@@ -221,18 +263,6 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
 
-static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
-{
-	switch (cpu_transcoder) {
-	case TRANSCODER_A:
-		return TRANSCODER_CMTG0;
-	case TRANSCODER_B:
-		return TRANSCODER_CMTG1;
-	default:
-		return INVALID_TRANSCODER;
-	}
-}
-
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 12abbafa7d08..79785afccc51 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index a93236bf7b75..240a02cd4a3a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -22,5 +22,6 @@
 						    _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
 #define  CMTG_ENABLE			REG_BIT(31)
 #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
+#define  CMTG_STATE			REG_BIT(23)
 
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

Re: [PATCH v7 09/15] drm/i915/cmtg: Modify existing hook to disable CMTG

[Ville Syrjälä]

On Tue, May 26, 2026 at 07:08:05PM +0530, Animesh Manna wrote:
> From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> 
> Earlier cmtg_disable() used to disable all instances of CMTG
> which cannot handle individual request for specific CMTG instance.
> Introduce cmtg_disable_all() which will disable all cmtg instances
> and cmtg_disable() only disable specific instance.
> 
> v2:
> - Use intel_de_rmw to simplify. [Uma]
> 
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 60 ++++++++++++++-----
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
>  3 files changed, 47 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 34715280d65d..643e2e846d25 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -82,6 +82,18 @@ static void intel_cmtg_dump_config(struct intel_display *display,
>  		    str_yes_no(cmtg_config->trans_b_secondary));
>  }
>  
> +static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
> +{
> +	switch (cpu_transcoder) {
> +	case TRANSCODER_A:
> +		return TRANSCODER_CMTG0;
> +	case TRANSCODER_B:
> +		return TRANSCODER_CMTG1;
> +	default:
> +		return INVALID_TRANSCODER;
> +	}
> +}
> +
>  static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,
>  					       enum transcoder trans)
>  {
> @@ -125,8 +137,8 @@ static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
>  	return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary;
>  }
>  
> -static void intel_cmtg_disable(struct intel_display *display,
> -			       struct intel_cmtg_config *cmtg_config)
> +static void intel_cmtg_disable_all(struct intel_display *display,
> +				   struct intel_cmtg_config *cmtg_config)
>  {
>  	u32 clk_sel_clr = 0;
>  	u32 clk_sel_set = 0;
> @@ -157,6 +169,36 @@ static void intel_cmtg_disable(struct intel_display *display,
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
>  }
>  
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
> +	u32 clk_sel_clr = 0;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;

I think we just want to track the cmtg transcoder in the crtc state,
instead of this stuff that just assumes things.

> +
> +	intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
> +		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
> +
> +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
> +		     CMTG_SECONDARY_MODE, 0);
> +
> +	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
> +
> +	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
> +		drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
> +			 transcoder_name(cpu_transcoder));
> +		return;
> +	}
> +
> +	clk_sel_clr = cpu_transcoder == TRANSCODER_A ? CMTG_CLK_SEL_A_MASK : CMTG_CLK_SEL_B_MASK;
> +	intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, 0);
> +
> +	drm_dbg_kms(display->drm, "CMTG: %s disabled\n", transcoder_name(cpu_transcoder));
> +}
> +
>  /*
>   * Read out CMTG configuration and, on platforms that allow disabling it without
>   * a modeset, do it.
> @@ -184,7 +226,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
>  	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
>  		return;
>  
> -	intel_cmtg_disable(display, &cmtg_config);
> +	intel_cmtg_disable_all(display, &cmtg_config);
>  }
>  
>  bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
> @@ -221,18 +263,6 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
>  }
>  
> -static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
> -{
> -	switch (cpu_transcoder) {
> -	case TRANSCODER_A:
> -		return TRANSCODER_CMTG0;
> -	case TRANSCODER_B:
> -		return TRANSCODER_CMTG1;
> -	default:
> -		return INVALID_TRANSCODER;
> -	}
> -}
> -
>  void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 12abbafa7d08..79785afccc51 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>  struct intel_display;
>  struct intel_crtc_state;
>  
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index a93236bf7b75..240a02cd4a3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -22,5 +22,6 @@
>  						    _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
>  #define  CMTG_ENABLE			REG_BIT(31)
>  #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
> +#define  CMTG_STATE			REG_BIT(23)
>  
>  #endif /* __INTEL_CMTG_REGS_H__ */
> -- 
> 2.29.0

-- 
Ville Syrjälä
Intel

RE: [PATCH v7 09/15] drm/i915/cmtg: Modify existing hook to disable CMTG

[Manna, Animesh]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, May 29, 2026 4:32 PM
> To: Manna, Animesh <animesh.manna@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Shankar,
> Uma <uma.shankar@intel.com>; Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [PATCH v7 09/15] drm/i915/cmtg: Modify existing hook to disable
> CMTG
> 
> On Tue, May 26, 2026 at 07:08:05PM +0530, Animesh Manna wrote:
> > From: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> >
> > Earlier cmtg_disable() used to disable all instances of CMTG which
> > cannot handle individual request for specific CMTG instance.
> > Introduce cmtg_disable_all() which will disable all cmtg instances and
> > cmtg_disable() only disable specific instance.
> >
> > v2:
> > - Use intel_de_rmw to simplify. [Uma]
> >
> > Signed-off-by: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cmtg.c     | 60 ++++++++++++++-----
> >  drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
> >  .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
> >  3 files changed, 47 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index 34715280d65d..643e2e846d25 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -82,6 +82,18 @@ static void intel_cmtg_dump_config(struct
> intel_display *display,
> >  		    str_yes_no(cmtg_config->trans_b_secondary));
> >  }
> >
> > +static inline enum transcoder to_cmtg_transcoder(enum transcoder
> > +cpu_transcoder) {
> > +	switch (cpu_transcoder) {
> > +	case TRANSCODER_A:
> > +		return TRANSCODER_CMTG0;
> > +	case TRANSCODER_B:
> > +		return TRANSCODER_CMTG1;
> > +	default:
> > +		return INVALID_TRANSCODER;
> > +	}
> > +}
> > +
> >  static bool intel_cmtg_transcoder_is_secondary(struct intel_display
> *display,
> >  					       enum transcoder trans)
> >  {
> > @@ -125,8 +137,8 @@ static bool
> intel_cmtg_disable_requires_modeset(struct intel_display *display,
> >  	return cmtg_config->trans_a_secondary ||
> > cmtg_config->trans_b_secondary;  }
> >
> > -static void intel_cmtg_disable(struct intel_display *display,
> > -			       struct intel_cmtg_config *cmtg_config)
> > +static void intel_cmtg_disable_all(struct intel_display *display,
> > +				   struct intel_cmtg_config *cmtg_config)
> >  {
> >  	u32 clk_sel_clr = 0;
> >  	u32 clk_sel_set = 0;
> > @@ -157,6 +169,36 @@ static void intel_cmtg_disable(struct intel_display
> *display,
> >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set);  }
> >
> > +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state-
> >cpu_transcoder);
> > +	u32 clk_sel_clr = 0;
> > +
> > +	if (!intel_cmtg_is_allowed(crtc_state))
> > +		return;
> 
> I think we just want to track the cmtg transcoder in the crtc state, instead of
> this stuff that just assumes things.

Based on cmtg.enabled flag cmtg_disable() will be called.

if (crtc->cmtg.enabled)
                intel_cmtg_disable(old_crtc_state);

But current code maybe confusing, I will add a check inside cmtg_disable().

If (!crtc->cmtg.enabled)
	return;

Regards,
Animesh
> 
> > +
> > +	intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
> > +		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
> > +
> > +	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
> > +		     CMTG_SECONDARY_MODE, 0);
> > +
> > +	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> CMTG_ENABLE,
> > +0);
> > +
> > +	if (intel_de_wait_for_clear_ms(display,
> TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
> > +		drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
> > +			 transcoder_name(cpu_transcoder));
> > +		return;
> > +	}
> > +
> > +	clk_sel_clr = cpu_transcoder == TRANSCODER_A ?
> CMTG_CLK_SEL_A_MASK : CMTG_CLK_SEL_B_MASK;
> > +	intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, 0);
> > +
> > +	drm_dbg_kms(display->drm, "CMTG: %s disabled\n",
> > +transcoder_name(cpu_transcoder)); }
> > +
> >  /*
> >   * Read out CMTG configuration and, on platforms that allow disabling it
> without
> >   * a modeset, do it.
> > @@ -184,7 +226,7 @@ void intel_cmtg_sanitize(struct intel_display
> *display)
> >  	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
> >  		return;
> >
> > -	intel_cmtg_disable(display, &cmtg_config);
> > +	intel_cmtg_disable_all(display, &cmtg_config);
> >  }
> >
> >  bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
> > @@ -221,18 +263,6 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
> >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set);  }
> >
> > -static inline enum transcoder to_cmtg_transcoder(enum transcoder
> > cpu_transcoder) -{
> > -	switch (cpu_transcoder) {
> > -	case TRANSCODER_A:
> > -		return TRANSCODER_CMTG0;
> > -	case TRANSCODER_B:
> > -		return TRANSCODER_CMTG1;
> > -	default:
> > -		return INVALID_TRANSCODER;
> > -	}
> > -}
> > -
> >  void intel_cmtg_set_timings(const struct intel_crtc_state
> > *crtc_state, bool lrr)  {
> >  	struct intel_display *display = to_intel_display(crtc_state); diff
> > --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index 12abbafa7d08..79785afccc51 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -11,6 +11,7 @@
> >  struct intel_display;
> >  struct intel_crtc_state;
> >
> > +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
> >  void intel_cmtg_enable_ddi(const struct intel_crtc_state
> > *crtc_state);  void intel_cmtg_enable_sync(const struct
> > intel_crtc_state *crtc_state);  void intel_cmtg_set_m_n(const struct
> > intel_crtc_state *crtc_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > index a93236bf7b75..240a02cd4a3a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > @@ -22,5 +22,6 @@
> >  						    _TRANS_CMTG_CTL_A,
> _TRANS_CMTG_CTL_B)
> >  #define  CMTG_ENABLE			REG_BIT(31)
> >  #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
> > +#define  CMTG_STATE			REG_BIT(23)
> >
> >  #endif /* __INTEL_CMTG_REGS_H__ */
> > --
> > 2.29.0
> 
> --
> Ville Syrjälä
> Intel

[PATCH v7 10/15] drm/i915/cmtg: Add CMTG interrupt handling

[Animesh Manna]

Add support for vsync, vblank, and delayed vblank interrupts of
CMTG which are part of DE port interrupt.

v2:
- Use consistent DC3co check as used in earlier patches. [Uma]
- Use else-if instead of separate if block. [Uma]
- Merge mask and unmask function as it is similar. [Uma]
- Modify DISPLAY_VER() check. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 42 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 +
 .../gpu/drm/i915/display/intel_display_irq.c  | 12 ++++++
 .../gpu/drm/i915/display/intel_display_regs.h |  6 +++
 4 files changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 643e2e846d25..17e8da4fa7ee 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -13,6 +13,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_device.h"
+#include "intel_display_irq.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
@@ -402,3 +403,44 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
+
+static void intel_cmtg_mask_interrupt(const struct intel_crtc_state *crtc_state, bool mask)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 interrupt_mask = 0;
+
+	if (cpu_transcoder == TRANSCODER_A)
+		interrupt_mask = CMTG_VBLANK_A | CMTG_DELAYED_VBLANK_A | CMTG_VSYNC_A;
+	else if (cpu_transcoder == TRANSCODER_B)
+		interrupt_mask = CMTG_VBLANK_B | CMTG_DELAYED_VBLANK_B | CMTG_VSYNC_B;
+
+	if (mask)
+		bdw_update_port_irq(display, interrupt_mask, 0);
+	else
+		bdw_update_port_irq(display, interrupt_mask, interrupt_mask);
+}
+
+void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	spin_lock_irq(&display->irq.lock);
+	intel_cmtg_mask_interrupt(crtc_state, false);
+	spin_unlock_irq(&display->irq.lock);
+}
+
+void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	spin_lock_irq(&display->irq.lock);
+	intel_cmtg_mask_interrupt(crtc_state, true);
+	spin_unlock_irq(&display->irq.lock);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 79785afccc51..8fcb44d6398f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -21,5 +21,7 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 899a38c0a7b7..f7f670dd5900 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1469,6 +1469,18 @@ static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 				found = true;
 			}
 
+			if (DISPLAY_VER(display) == 35) {
+				if (iir & (CMTG_VBLANK_A | CMTG_VSYNC_A | CMTG_DELAYED_VBLANK_A)) {
+					intel_handle_vblank(display, PIPE_A);
+					found = true;
+				}
+
+				if (iir & (CMTG_VBLANK_B | CMTG_VSYNC_B | CMTG_DELAYED_VBLANK_B)) {
+					intel_handle_vblank(display, PIPE_B);
+					found = true;
+				}
+			}
+
 			if (DISPLAY_VER(display) >= 11) {
 				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4321f8b529da..f38dcd9b6c48 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1458,6 +1458,12 @@
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  DSI1_TE			(1 << 24)
 #define  DSI0_TE			(1 << 23)
+#define  CMTG_VSYNC_B			(1 << 19)
+#define  CMTG_DELAYED_VBLANK_B		(1 << 18)
+#define  CMTG_VBLANK_B			(1 << 17)
+#define  CMTG_VSYNC_A			(1 << 16)
+#define  CMTG_DELAYED_VBLANK_A		(1 << 15)
+#define  CMTG_VBLANK_A			(1 << 14)
 #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
 #define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
 					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
-- 
2.29.0

Re: [PATCH v7 10/15] drm/i915/cmtg: Add CMTG interrupt handling

[Dibin Moolakadan Subrahmanian]

On 26-05-2026 19:08, Animesh Manna wrote:
> Add support for vsync, vblank, and delayed vblank interrupts of
> CMTG which are part of DE port interrupt.
>
> v2:
> - Use consistent DC3co check as used in earlier patches. [Uma]
> - Use else-if instead of separate if block. [Uma]
> - Merge mask and unmask function as it is similar. [Uma]
> - Modify DISPLAY_VER() check. [Uma]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cmtg.c     | 42 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 +
>   .../gpu/drm/i915/display/intel_display_irq.c  | 12 ++++++
>   .../gpu/drm/i915/display/intel_display_regs.h |  6 +++
>   4 files changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 643e2e846d25..17e8da4fa7ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -13,6 +13,7 @@
>   #include "intel_crtc.h"
>   #include "intel_de.h"
>   #include "intel_display_device.h"
> +#include "intel_display_irq.h"
>   #include "intel_display_power.h"
>   #include "intel_display_regs.h"
>   #include "intel_display_types.h"
> @@ -402,3 +403,44 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
>   
>   	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
>   }
> +
> +static void intel_cmtg_mask_interrupt(const struct intel_crtc_state *crtc_state, bool mask)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 interrupt_mask = 0;
> +
> +	if (cpu_transcoder == TRANSCODER_A)
> +		interrupt_mask = CMTG_VBLANK_A | CMTG_DELAYED_VBLANK_A | CMTG_VSYNC_A;
> +	else if (cpu_transcoder == TRANSCODER_B)
> +		interrupt_mask = CMTG_VBLANK_B | CMTG_DELAYED_VBLANK_B | CMTG_VSYNC_B;
> +
> +	if (mask)
> +		bdw_update_port_irq(display, interrupt_mask, 0);
> +	else
> +		bdw_update_port_irq(display, interrupt_mask, interrupt_mask);
> +}
> +
> +void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	spin_lock_irq(&display->irq.lock);
> +	intel_cmtg_mask_interrupt(crtc_state, false);
> +	spin_unlock_irq(&display->irq.lock);
> +}

Is this interrupt getting enabled through `GEN8_DE_PORT_IRQ`
IER ?

> +
> +void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	spin_lock_irq(&display->irq.lock);
> +	intel_cmtg_mask_interrupt(crtc_state, true);
> +	spin_unlock_irq(&display->irq.lock);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 79785afccc51..8fcb44d6398f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -21,5 +21,7 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
>   void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
>   void intel_cmtg_sanitize(struct intel_display *display);
>   bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
>   
>   #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 899a38c0a7b7..f7f670dd5900 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1469,6 +1469,18 @@ static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
>   				found = true;
>   			}
>   
> +			if (DISPLAY_VER(display) == 35) {
> +				if (iir & (CMTG_VBLANK_A | CMTG_VSYNC_A | CMTG_DELAYED_VBLANK_A)) {
> +					intel_handle_vblank(display, PIPE_A);
> +					found = true;
> +				}
> +
> +				if (iir & (CMTG_VBLANK_B | CMTG_VSYNC_B | CMTG_DELAYED_VBLANK_B)) {
> +					intel_handle_vblank(display, PIPE_B);
> +					found = true;
> +				}
> +			}

I could see `intel_handle_vblank()` getting called only for
`GEN8_PIPE_VBLANK` interrupts. Does it need to be called for
all three interrupts here?

> +
>   			if (DISPLAY_VER(display) >= 11) {
>   				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4321f8b529da..f38dcd9b6c48 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1458,6 +1458,12 @@
>   #define  GEN9_AUX_CHANNEL_B		(1 << 25)
>   #define  DSI1_TE			(1 << 24)
>   #define  DSI0_TE			(1 << 23)
> +#define  CMTG_VSYNC_B			(1 << 19)
> +#define  CMTG_DELAYED_VBLANK_B		(1 << 18)
> +#define  CMTG_VBLANK_B			(1 << 17)
> +#define  CMTG_VSYNC_A			(1 << 16)
> +#define  CMTG_DELAYED_VBLANK_A		(1 << 15)
> +#define  CMTG_VBLANK_A			(1 << 14)
>   #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
>   #define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
>   					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \

RE: [PATCH v7 10/15] drm/i915/cmtg: Add CMTG interrupt handling

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Friday, May 29, 2026 7:46 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH v7 10/15] drm/i915/cmtg: Add CMTG interrupt handling
> 
> 
> On 26-05-2026 19:08, Animesh Manna wrote:
> > Add support for vsync, vblank, and delayed vblank interrupts of CMTG
> > which are part of DE port interrupt.
> >
> > v2:
> > - Use consistent DC3co check as used in earlier patches. [Uma]
> > - Use else-if instead of separate if block. [Uma]
> > - Merge mask and unmask function as it is similar. [Uma]
> > - Modify DISPLAY_VER() check. [Uma]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_cmtg.c     | 42 +++++++++++++++++++
> >   drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 +
> >   .../gpu/drm/i915/display/intel_display_irq.c  | 12 ++++++
> >   .../gpu/drm/i915/display/intel_display_regs.h |  6 +++
> >   4 files changed, 62 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index 643e2e846d25..17e8da4fa7ee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -13,6 +13,7 @@
> >   #include "intel_crtc.h"
> >   #include "intel_de.h"
> >   #include "intel_display_device.h"
> > +#include "intel_display_irq.h"
> >   #include "intel_display_power.h"
> >   #include "intel_display_regs.h"
> >   #include "intel_display_types.h"
> > @@ -402,3 +403,44 @@ void intel_cmtg_enable_ddi(const struct
> > intel_crtc_state *crtc_state)
> >
> >   	drm_dbg_kms(display->drm, "CMTG: %s enabled\n",
> transcoder_name(cpu_transcoder));
> >   }
> > +
> > +static void intel_cmtg_mask_interrupt(const struct intel_crtc_state
> > +*crtc_state, bool mask) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +	u32 interrupt_mask = 0;
> > +
> > +	if (cpu_transcoder == TRANSCODER_A)
> > +		interrupt_mask = CMTG_VBLANK_A |
> CMTG_DELAYED_VBLANK_A | CMTG_VSYNC_A;
> > +	else if (cpu_transcoder == TRANSCODER_B)
> > +		interrupt_mask = CMTG_VBLANK_B |
> CMTG_DELAYED_VBLANK_B |
> > +CMTG_VSYNC_B;
> > +
> > +	if (mask)
> > +		bdw_update_port_irq(display, interrupt_mask, 0);
> > +	else
> > +		bdw_update_port_irq(display, interrupt_mask,
> interrupt_mask); }
> > +
> > +void intel_cmtg_enable_interrupt(const struct intel_crtc_state
> > +*crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +
> > +	if (!intel_cmtg_is_allowed(crtc_state))
> > +		return;
> > +
> > +	spin_lock_irq(&display->irq.lock);
> > +	intel_cmtg_mask_interrupt(crtc_state, false);
> > +	spin_unlock_irq(&display->irq.lock);
> > +}
> 
> Is this interrupt getting enabled through `GEN8_DE_PORT_IRQ` IER ?

Currently transcoder interrupt is used, will check on this.

> 
> > +
> > +void intel_cmtg_disable_interrupt(const struct intel_crtc_state
> > +*crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +
> > +	if (!intel_cmtg_is_allowed(crtc_state))
> > +		return;
> > +
> > +	spin_lock_irq(&display->irq.lock);
> > +	intel_cmtg_mask_interrupt(crtc_state, true);
> > +	spin_unlock_irq(&display->irq.lock);
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index 79785afccc51..8fcb44d6398f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -21,5 +21,7 @@ void intel_cmtg_set_timings(const struct
> intel_crtc_state *crtc_state, bool lrr)
> >   void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
> >   void intel_cmtg_sanitize(struct intel_display *display);
> >   bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > *crtc_state);
> > +void intel_cmtg_enable_interrupt(const struct intel_crtc_state
> > +*crtc_state); void intel_cmtg_disable_interrupt(const struct
> > +intel_crtc_state *crtc_state);
> >
> >   #endif /* __INTEL_CMTG_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> > b/drivers/gpu/drm/i915/display/intel_display_irq.c
> > index 899a38c0a7b7..f7f670dd5900 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> > @@ -1469,6 +1469,18 @@ static void gen8_de_irq_handler(struct
> intel_display *display, u32 master_ctl)
> >   				found = true;
> >   			}
> >
> > +			if (DISPLAY_VER(display) == 35) {
> > +				if (iir & (CMTG_VBLANK_A | CMTG_VSYNC_A
> | CMTG_DELAYED_VBLANK_A)) {
> > +					intel_handle_vblank(display, PIPE_A);
> > +					found = true;
> > +				}
> > +
> > +				if (iir & (CMTG_VBLANK_B | CMTG_VSYNC_B
> | CMTG_DELAYED_VBLANK_B)) {
> > +					intel_handle_vblank(display, PIPE_B);
> > +					found = true;
> > +				}
> > +			}
> 
> I could see `intel_handle_vblank()` getting called only for
> `GEN8_PIPE_VBLANK` interrupts. Does it need to be called for all three
> interrupts here?

You are right, only CMTG_VBLANK will be sufficient.

Regards,
Animesh
> 
> > +
> >   			if (DISPLAY_VER(display) >= 11) {
> >   				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 4321f8b529da..f38dcd9b6c48 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -1458,6 +1458,12 @@
> >   #define  GEN9_AUX_CHANNEL_B		(1 << 25)
> >   #define  DSI1_TE			(1 << 24)
> >   #define  DSI0_TE			(1 << 23)
> > +#define  CMTG_VSYNC_B			(1 << 19)
> > +#define  CMTG_DELAYED_VBLANK_B		(1 << 18)
> > +#define  CMTG_VBLANK_B			(1 << 17)
> > +#define  CMTG_VSYNC_A			(1 << 16)
> > +#define  CMTG_DELAYED_VBLANK_A		(1 << 15)
> > +#define  CMTG_VBLANK_A			(1 << 14)
> >   #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 +
> _HPD_PIN_DDI(hpd_pin))
> >   #define  BXT_DE_PORT_HOTPLUG_MASK
> 	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
> >
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \

[PATCH v7 11/15] drm/i915/cmtg: Add CMTG HWGB programming

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Program CMTG guardband to generate the Lower/Upper and early entry
guardband indicators to the DMC for DC3co control.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 31 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  8 +++++
 3 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 17e8da4fa7ee..09ab91dc9bfe 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -444,3 +444,34 @@ void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state)
 	intel_cmtg_mask_interrupt(crtc_state, true);
 	spin_unlock_irq(&display->irq.lock);
 }
+
+#define DC3CO_ENTRY_LATENCY	55
+#define DC3CO_EXIT_LATENCY	40
+
+void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 breakeven_gb;
+	u32 dc5_exit_latency;
+	u32 line_time_us = 75;
+	u32 val;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	if (crtc_state->linetime)
+		line_time_us = DIV_ROUND_UP(crtc_state->linetime, 8);
+
+	/* Break Even Guardband - DC3co Entry Latency / linetime */
+	breakeven_gb = DIV_ROUND_UP(DC3CO_ENTRY_LATENCY, line_time_us);
+
+	/* DC5 Exit Latency - DC3co Exit Latency / linetime */
+	dc5_exit_latency = DIV_ROUND_UP(DC3CO_EXIT_LATENCY, line_time_us);
+
+	val = REG_FIELD_PREP(CMTG_HW_GB_BREAKEVEN_MASK, breakeven_gb) |
+	      REG_FIELD_PREP(CMTG_HW_GB_DC5_EXIT_LATENCY_MASK, dc5_exit_latency) |
+	      REG_FIELD_PREP(CMTG_HW_GB_UP_LW_BG_DIFF_MASK, 1);
+
+	intel_de_write(display, CMTG_HW_GB(cpu_transcoder), val);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 8fcb44d6398f..2c801a74acf9 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -23,5 +23,6 @@ void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 240a02cd4a3a..a4a2a2fe6b66 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -24,4 +24,12 @@
 #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
 #define  CMTG_STATE			REG_BIT(23)
 
+#define _CMTG_HW_GB_A				0x6fa8c
+#define _CMTG_HW_GB_B				0x6fb8c
+#define CMTG_HW_GB(trans)			_MMIO_TRANS((trans), \
+							    _CMTG_HW_GB_A, _CMTG_HW_GB_B)
+#define CMTG_HW_GB_BREAKEVEN_MASK		REG_GENMASK(11, 0)
+#define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK	REG_GENMASK(27, 16)
+#define CMTG_HW_GB_UP_LW_BG_DIFF_MASK		REG_GENMASK(31, 28)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

[PATCH v7 12/15] drm/i915/cmtg: Add CMTG scan line programming

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Enable the hardware based guardband calculations which allows
DC3co to remain enabled when timings are changing from one fixed
refresh rate to another fixed refresh rate.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c      | 2 ++
 drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 09ab91dc9bfe..a0413013ec43 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -185,6 +185,7 @@ void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
 
 	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
 		     CMTG_SECONDARY_MODE, 0);
+	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), CMTG_HW_GB_ENABLE, 0);
 
 	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
 
@@ -400,6 +401,7 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 		return;
 
 	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
+	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0, CMTG_HW_GB_ENABLE);
 
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index a4a2a2fe6b66..18dcb665df04 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -32,4 +32,10 @@
 #define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK	REG_GENMASK(27, 16)
 #define CMTG_HW_GB_UP_LW_BG_DIFF_MASK		REG_GENMASK(31, 28)
 
+#define _CMTG_SCANLINE_GB1_A		0x456A0
+#define _CMTG_SCANLINE_GB1_B		0x456C0
+#define CMTG_SCANLINE_GB1(trans)	_MMIO_TRANS((trans), \
+						    _CMTG_SCANLINE_GB1_A, _CMTG_SCANLINE_GB1_B)
+#define  CMTG_HW_GB_ENABLE		REG_BIT(31)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

[PATCH v7 13/15] drm/i915/cmtg: Add trigger to enable/disable cmtg

[Animesh Manna]

Enable CMTG with fixed refresh rate mode and with dynamic
dc state enabled.

Disable CMTG with transcoder disable or if there is a transition
to vrr mode from fixed refresh rate mode.

v2:
- Move the enabled flag update to avoid issue in the disable timeout
path. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     |  4 ++++
 drivers/gpu/drm/i915/display/intel_display.c  | 24 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  4 ++++
 3 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index a0413013ec43..d808c62e14b1 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -173,6 +173,7 @@ static void intel_cmtg_disable_all(struct intel_display *display,
 void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
 	u32 clk_sel_clr = 0;
@@ -180,6 +181,7 @@ void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
 	if (!intel_cmtg_is_allowed(crtc_state))
 		return;
 
+	crtc->cmtg.enabled = false;
 	intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
 		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
 
@@ -395,6 +397,7 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (!intel_cmtg_is_allowed(crtc_state))
@@ -403,6 +406,7 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
 	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0, CMTG_HW_GB_ENABLE);
 
+	crtc->cmtg.enabled = true;
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 354eca79bac0..36ff17b88be7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1771,6 +1771,9 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
 	struct intel_crtc *pipe_crtc;
 	int i;
 
+	if (crtc->cmtg.enabled)
+		intel_cmtg_disable(old_crtc_state);
+
 	/*
 	 * FIXME collapse everything to one hook.
 	 * Need care with mst->ddi interactions.
@@ -6868,6 +6871,12 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	if (intel_crtc_needs_fastset(new_crtc_state) &&
 	    old_crtc_state->inherited)
 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
+
+	if (crtc->cmtg.enabled && (intel_crtc_vrr_enabling(state, crtc) ||
+				   !intel_cmtg_is_allowed(new_crtc_state))) {
+		intel_cmtg_disable(new_crtc_state);
+		intel_cmtg_disable_interrupt(new_crtc_state);
+	}
 }
 
 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
@@ -7545,6 +7554,21 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	/* FIXME probably need to sequence this properly */
 	intel_program_dpkgc_latency(state);
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
+
+		/*
+		 * TODO: CMTG needs to be restored on DC6 exit and DC3co entry condition
+		 * need to be checked before calling CMTG functions.
+		 */
+		if (modeset && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+			intel_cmtg_enable_sync(new_crtc_state);
+			intel_cmtg_set_hwgb(new_crtc_state);
+			intel_cmtg_enable_ddi(new_crtc_state);
+			intel_cmtg_enable_interrupt(new_crtc_state);
+		}
+	}
+
 	intel_wait_for_vblank_workers(state);
 
 	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1c0c32c4e43a..74c719b52759 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1573,6 +1573,10 @@ struct intel_crtc {
 #endif
 
 	bool vblank_psr_notify;
+
+	struct {
+		bool enabled;
+	} cmtg;
 };
 
 struct intel_plane_error {
-- 
2.29.0

Re: [PATCH v7 13/15] drm/i915/cmtg: Add trigger to enable/disable cmtg

[Dibin Moolakadan Subrahmanian]

On 26-05-2026 19:08, Animesh Manna wrote:
> Enable CMTG with fixed refresh rate mode and with dynamic
> dc state enabled.
>
> Disable CMTG with transcoder disable or if there is a transition
> to vrr mode from fixed refresh rate mode.
>
> v2:
> - Move the enabled flag update to avoid issue in the disable timeout
> path. [Uma]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cmtg.c     |  4 ++++
>   drivers/gpu/drm/i915/display/intel_display.c  | 24 +++++++++++++++++++
>   .../drm/i915/display/intel_display_types.h    |  4 ++++
>   3 files changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index a0413013ec43..d808c62e14b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -173,6 +173,7 @@ static void intel_cmtg_disable_all(struct intel_display *display,
>   void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>   	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
>   	u32 clk_sel_clr = 0;
> @@ -180,6 +181,7 @@ void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
>   	if (!intel_cmtg_is_allowed(crtc_state))
>   		return;
>   
> +	crtc->cmtg.enabled = false;
>   	intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
>   		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
>   
> @@ -395,6 +397,7 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
>   void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>   
>   	if (!intel_cmtg_is_allowed(crtc_state))
> @@ -403,6 +406,7 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
>   	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
>   	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0, CMTG_HW_GB_ENABLE);
>   
> +	crtc->cmtg.enabled = true;
>   	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
>   }
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 354eca79bac0..36ff17b88be7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1771,6 +1771,9 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
>   	struct intel_crtc *pipe_crtc;
>   	int i;
>   
> +	if (crtc->cmtg.enabled)
> +		intel_cmtg_disable(old_crtc_state);

Should interrupt disable handling also be done here?

Also, since CMTG registers including clock select may be
lost on DC6 entry, could `intel_cmtg_disable()` timeout
during suspend/shutdown?

Would restoring the clock select before disable help here?

> +
>   	/*
>   	 * FIXME collapse everything to one hook.
>   	 * Need care with mst->ddi interactions.
> @@ -6868,6 +6871,12 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>   	if (intel_crtc_needs_fastset(new_crtc_state) &&
>   	    old_crtc_state->inherited)
>   		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> +
> +	if (crtc->cmtg.enabled && (intel_crtc_vrr_enabling(state, crtc) ||
> +				   !intel_cmtg_is_allowed(new_crtc_state))) {
> +		intel_cmtg_disable(new_crtc_state);
> +		intel_cmtg_disable_interrupt(new_crtc_state);
> +	}
>   }
>   
>   static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> @@ -7545,6 +7554,21 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>   	/* FIXME probably need to sequence this properly */
>   	intel_program_dpkgc_latency(state);
>   
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
> +
> +		/*
> +		 * TODO: CMTG needs to be restored on DC6 exit and DC3co entry condition
> +		 * need to be checked before calling CMTG functions.
> +		 */
> +		if (modeset && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
> +			intel_cmtg_enable_sync(new_crtc_state);
> +			intel_cmtg_set_hwgb(new_crtc_state);
> +			intel_cmtg_enable_ddi(new_crtc_state);
> +			intel_cmtg_enable_interrupt(new_crtc_state);
> +		}
> +	}
> +
>   	intel_wait_for_vblank_workers(state);
>   
>   	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1c0c32c4e43a..74c719b52759 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1573,6 +1573,10 @@ struct intel_crtc {
>   #endif
>   
>   	bool vblank_psr_notify;
> +
> +	struct {
> +		bool enabled;
> +	} cmtg;
>   };
>   
>   struct intel_plane_error {

RE: [PATCH v7 13/15] drm/i915/cmtg: Add trigger to enable/disable cmtg

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Friday, May 29, 2026 7:59 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH v7 13/15] drm/i915/cmtg: Add trigger to enable/disable
> cmtg
> 
> 
> On 26-05-2026 19:08, Animesh Manna wrote:
> > Enable CMTG with fixed refresh rate mode and with dynamic dc state
> > enabled.
> >
> > Disable CMTG with transcoder disable or if there is a transition to
> > vrr mode from fixed refresh rate mode.
> >
> > v2:
> > - Move the enabled flag update to avoid issue in the disable timeout
> > path. [Uma]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_cmtg.c     |  4 ++++
> >   drivers/gpu/drm/i915/display/intel_display.c  | 24 +++++++++++++++++++
> >   .../drm/i915/display/intel_display_types.h    |  4 ++++
> >   3 files changed, 32 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index a0413013ec43..d808c62e14b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -173,6 +173,7 @@ static void intel_cmtg_disable_all(struct
> intel_display *display,
> >   void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
> >   {
> >   	struct intel_display *display = to_intel_display(crtc_state);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >   	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state-
> >cpu_transcoder);
> >   	u32 clk_sel_clr = 0;
> > @@ -180,6 +181,7 @@ void intel_cmtg_disable(const struct intel_crtc_state
> *crtc_state)
> >   	if (!intel_cmtg_is_allowed(crtc_state))
> >   		return;
> >
> > +	crtc->cmtg.enabled = false;
> >   	intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
> >   		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
> >
> > @@ -395,6 +397,7 @@ void intel_cmtg_enable_sync(const struct
> intel_crtc_state *crtc_state)
> >   void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
> >   {
> >   	struct intel_display *display = to_intel_display(crtc_state);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >
> >   	if (!intel_cmtg_is_allowed(crtc_state))
> > @@ -403,6 +406,7 @@ void intel_cmtg_enable_ddi(const struct
> intel_crtc_state *crtc_state)
> >   	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder), 0, CMTG_SECONDARY_MODE);
> >   	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0,
> > CMTG_HW_GB_ENABLE);
> >
> > +	crtc->cmtg.enabled = true;
> >   	drm_dbg_kms(display->drm, "CMTG: %s enabled\n",
> transcoder_name(cpu_transcoder));
> >   }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 354eca79bac0..36ff17b88be7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1771,6 +1771,9 @@ static void hsw_crtc_disable(struct
> intel_atomic_state *state,
> >   	struct intel_crtc *pipe_crtc;
> >   	int i;
> >
> > +	if (crtc->cmtg.enabled)
> > +		intel_cmtg_disable(old_crtc_state);
> 
> Should interrupt disable handling also be done here?

Ok, will add.

> 
> Also, since CMTG registers including clock select may be lost on DC6 entry,
> could `intel_cmtg_disable()` timeout during suspend/shutdown?
> 
> Would restoring the clock select before disable help here?

Not sure if clk_select will loose its value, can add to be on the safer side.

Regards,
Animesh 
> 
> > +
> >   	/*
> >   	 * FIXME collapse everything to one hook.
> >   	 * Need care with mst->ddi interactions.
> > @@ -6868,6 +6871,12 @@ static void intel_update_crtc(struct
> intel_atomic_state *state,
> >   	if (intel_crtc_needs_fastset(new_crtc_state) &&
> >   	    old_crtc_state->inherited)
> >   		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> > +
> > +	if (crtc->cmtg.enabled && (intel_crtc_vrr_enabling(state, crtc) ||
> > +				   !intel_cmtg_is_allowed(new_crtc_state))) {
> > +		intel_cmtg_disable(new_crtc_state);
> > +		intel_cmtg_disable_interrupt(new_crtc_state);
> > +	}
> >   }
> >
> >   static void intel_old_crtc_state_disables(struct intel_atomic_state
> > *state, @@ -7545,6 +7554,21 @@ static void
> intel_atomic_commit_tail(struct intel_atomic_state *state)
> >   	/* FIXME probably need to sequence this properly */
> >   	intel_program_dpkgc_latency(state);
> >
> > +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > +		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
> > +
> > +		/*
> > +		 * TODO: CMTG needs to be restored on DC6 exit and DC3co
> entry condition
> > +		 * need to be checked before calling CMTG functions.
> > +		 */
> > +		if (modeset && new_crtc_state->hw.active && !crtc-
> >cmtg.enabled) {
> > +			intel_cmtg_enable_sync(new_crtc_state);
> > +			intel_cmtg_set_hwgb(new_crtc_state);
> > +			intel_cmtg_enable_ddi(new_crtc_state);
> > +			intel_cmtg_enable_interrupt(new_crtc_state);
> > +		}
> > +	}
> > +
> >   	intel_wait_for_vblank_workers(state);
> >
> >   	/* FIXME: We should call drm_atomic_helper_commit_hw_done()
> here
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 1c0c32c4e43a..74c719b52759 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1573,6 +1573,10 @@ struct intel_crtc {
> >   #endif
> >
> >   	bool vblank_psr_notify;
> > +
> > +	struct {
> > +		bool enabled;
> > +	} cmtg;
> >   };
> >
> >   struct intel_plane_error {

[PATCH v7 14/15] drm/i915/cmtg: Restore CMTG after DC6 exit

[Animesh Manna]

Restore CMTG registers after DC6 exit, as they lose their values
in the low-power state.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c    | 15 ++++++++++++---
 .../gpu/drm/i915/display/intel_display_power.c  | 17 +++++++++++++++++
 .../gpu/drm/i915/display/intel_display_power.h  |  2 ++
 3 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 36ff17b88be7..4662bccf30f4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7556,12 +7556,21 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
 		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
+		bool dc3co_to_dc6 = intel_display_power_get_and_reset_dc3co_to_dc6(display);
 
 		/*
-		 * TODO: CMTG needs to be restored on DC6 exit and DC3co entry condition
-		 * need to be checked before calling CMTG functions.
+		 * TODO: DC3co entry condition need to be checked before calling CMTG functions.
 		 */
-		if (modeset && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+		if ((modeset || dc3co_to_dc6) &&
+		    new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+			if (dc3co_to_dc6) {
+				intel_cmtg_set_clk_select(new_crtc_state);
+				intel_cmtg_set_timings(new_crtc_state, false);
+				intel_cmtg_set_vrr_timings(new_crtc_state);
+				intel_cmtg_set_vrr_ctl(new_crtc_state);
+				intel_cmtg_set_m_n(new_crtc_state);
+			}
+
 			intel_cmtg_enable_sync(new_crtc_state);
 			intel_cmtg_set_hwgb(new_crtc_state);
 			intel_cmtg_enable_ddi(new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 751e6b7d4a29..637d547831c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -285,6 +285,19 @@ sanitize_target_dc_state(struct intel_display *display,
 	return target_dc_state;
 }
 
+bool intel_display_power_get_and_reset_dc3co_to_dc6(struct intel_display *display)
+{
+	struct i915_power_domains *power_domains = &display->power.domains;
+	bool ret;
+
+	mutex_lock(&power_domains->lock);
+	ret = power_domains->dc3co_to_dc6;
+	power_domains->dc3co_to_dc6 = false;
+	mutex_unlock(&power_domains->lock);
+
+	return ret;
+}
+
 /**
  * intel_display_power_set_target_dc_state - Set target dc state.
  * @display: display device
@@ -320,6 +333,10 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
 	if (!dc_off_enabled)
 		intel_power_well_enable(display, power_well);
 
+	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO &&
+	    state == DC_STATE_EN_UPTO_DC6)
+		power_domains->dc3co_to_dc6 = true;
+
 	power_domains->target_dc_state = state;
 
 	if (!dc_off_enabled)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index d616d5d09cbe..b43d4146a78a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -138,6 +138,7 @@ struct i915_power_domains {
 	 */
 	bool initializing;
 	bool display_core_suspended;
+	bool dc3co_to_dc6;
 	int power_well_count;
 
 	u32 dc_state;
@@ -183,6 +184,7 @@ void intel_display_power_suspend_late(struct intel_display *display, bool s2idle
 void intel_display_power_resume_early(struct intel_display *display);
 void intel_display_power_suspend(struct intel_display *display);
 void intel_display_power_resume(struct intel_display *display);
+bool intel_display_power_get_and_reset_dc3co_to_dc6(struct intel_display *display);
 void intel_display_power_set_target_dc_state(struct intel_display *display,
 					     u32 state);
 u32 intel_display_power_get_current_dc_state(struct intel_display *display);
-- 
2.29.0

[PATCH v7 15/15] [Not for Review] Debug patch

[Animesh Manna]

Debug patch.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index d808c62e14b1..f6eca7f85dd7 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -238,6 +238,12 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
+	/*
+	 * Currently Dc3co patches are not merged so returning false for
+	 * continuing cmtg patch review
+	 */
+	return false;
+
 	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
 	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		return true;
-- 
2.29.0

✓ CI.KUnit: success for CMTG enablement (rev8)

[Patchwork]

== Series Details ==

Series: CMTG enablement (rev8)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[15:01:04] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:01:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:01:40] Starting KUnit Kernel (1/1)...
[15:01:40] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:01:40] ================== guc_buf (11 subtests) ===================
[15:01:40] [PASSED] test_smallest
[15:01:40] [PASSED] test_largest
[15:01:40] [PASSED] test_granular
[15:01:40] [PASSED] test_unique
[15:01:40] [PASSED] test_overlap
[15:01:40] [PASSED] test_reusable
[15:01:40] [PASSED] test_too_big
[15:01:40] [PASSED] test_flush
[15:01:40] [PASSED] test_lookup
[15:01:40] [PASSED] test_data
[15:01:40] [PASSED] test_class
[15:01:40] ===================== [PASSED] guc_buf =====================
[15:01:40] =================== guc_dbm (7 subtests) ===================
[15:01:40] [PASSED] test_empty
[15:01:40] [PASSED] test_default
[15:01:40] ======================== test_size  ========================
[15:01:40] [PASSED] 4
[15:01:40] [PASSED] 8
[15:01:40] [PASSED] 32
[15:01:40] [PASSED] 256
[15:01:40] ==================== [PASSED] test_size ====================
[15:01:40] ======================= test_reuse  ========================
[15:01:40] [PASSED] 4
[15:01:40] [PASSED] 8
[15:01:40] [PASSED] 32
[15:01:40] [PASSED] 256
[15:01:40] =================== [PASSED] test_reuse ====================
[15:01:40] =================== test_range_overlap  ====================
[15:01:40] [PASSED] 4
[15:01:40] [PASSED] 8
[15:01:40] [PASSED] 32
[15:01:40] [PASSED] 256
[15:01:40] =============== [PASSED] test_range_overlap ================
[15:01:40] =================== test_range_compact  ====================
[15:01:40] [PASSED] 4
[15:01:40] [PASSED] 8
[15:01:40] [PASSED] 32
[15:01:40] [PASSED] 256
[15:01:40] =============== [PASSED] test_range_compact ================
[15:01:40] ==================== test_range_spare  =====================
[15:01:40] [PASSED] 4
[15:01:40] [PASSED] 8
[15:01:40] [PASSED] 32
[15:01:40] [PASSED] 256
[15:01:40] ================ [PASSED] test_range_spare =================
[15:01:40] ===================== [PASSED] guc_dbm =====================
[15:01:40] =================== guc_idm (6 subtests) ===================
[15:01:40] [PASSED] bad_init
[15:01:40] [PASSED] no_init
[15:01:40] [PASSED] init_fini
[15:01:40] [PASSED] check_used
[15:01:40] [PASSED] check_quota
[15:01:40] [PASSED] check_all
[15:01:40] ===================== [PASSED] guc_idm =====================
[15:01:40] ================== no_relay (3 subtests) ===================
[15:01:40] [PASSED] xe_drops_guc2pf_if_not_ready
[15:01:40] [PASSED] xe_drops_guc2vf_if_not_ready
[15:01:40] [PASSED] xe_rejects_send_if_not_ready
[15:01:40] ==================== [PASSED] no_relay =====================
[15:01:40] ================== pf_relay (14 subtests) ==================
[15:01:40] [PASSED] pf_rejects_guc2pf_too_short
[15:01:40] [PASSED] pf_rejects_guc2pf_too_long
[15:01:40] [PASSED] pf_rejects_guc2pf_no_payload
[15:01:40] [PASSED] pf_fails_no_payload
[15:01:40] [PASSED] pf_fails_bad_origin
[15:01:40] [PASSED] pf_fails_bad_type
[15:01:40] [PASSED] pf_txn_reports_error
[15:01:40] [PASSED] pf_txn_sends_pf2guc
[15:01:40] [PASSED] pf_sends_pf2guc
[15:01:40] [SKIPPED] pf_loopback_nop
[15:01:40] [SKIPPED] pf_loopback_echo
[15:01:40] [SKIPPED] pf_loopback_fail
[15:01:40] [SKIPPED] pf_loopback_busy
[15:01:40] [SKIPPED] pf_loopback_retry
[15:01:40] ==================== [PASSED] pf_relay =====================
[15:01:40] ================== vf_relay (3 subtests) ===================
[15:01:40] [PASSED] vf_rejects_guc2vf_too_short
[15:01:40] [PASSED] vf_rejects_guc2vf_too_long
[15:01:40] [PASSED] vf_rejects_guc2vf_no_payload
[15:01:40] ==================== [PASSED] vf_relay =====================
[15:01:40] ================ pf_gt_config (9 subtests) =================
[15:01:40] [PASSED] fair_contexts_1vf
[15:01:40] [PASSED] fair_doorbells_1vf
[15:01:40] [PASSED] fair_ggtt_1vf
[15:01:40] ====================== fair_vram_1vf  ======================
[15:01:40] [PASSED] 3.50 GiB
[15:01:40] [PASSED] 11.5 GiB
[15:01:40] [PASSED] 15.5 GiB
[15:01:40] [PASSED] 31.5 GiB
[15:01:40] [PASSED] 63.5 GiB
[15:01:40] [PASSED] 1.91 GiB
[15:01:40] ================== [PASSED] fair_vram_1vf ==================
[15:01:40] ================ fair_vram_1vf_admin_only  =================
[15:01:40] [PASSED] 3.50 GiB
[15:01:40] [PASSED] 11.5 GiB
[15:01:40] [PASSED] 15.5 GiB
[15:01:40] [PASSED] 31.5 GiB
[15:01:40] [PASSED] 63.5 GiB
[15:01:40] [PASSED] 1.91 GiB
[15:01:40] ============ [PASSED] fair_vram_1vf_admin_only =============
[15:01:40] ====================== fair_contexts  ======================
[15:01:40] [PASSED] 1 VF
[15:01:40] [PASSED] 2 VFs
[15:01:40] [PASSED] 3 VFs
[15:01:40] [PASSED] 4 VFs
[15:01:40] [PASSED] 5 VFs
[15:01:40] [PASSED] 6 VFs
[15:01:40] [PASSED] 7 VFs
[15:01:40] [PASSED] 8 VFs
[15:01:40] [PASSED] 9 VFs
[15:01:40] [PASSED] 10 VFs
[15:01:40] [PASSED] 11 VFs
[15:01:40] [PASSED] 12 VFs
[15:01:40] [PASSED] 13 VFs
[15:01:40] [PASSED] 14 VFs
[15:01:40] [PASSED] 15 VFs
[15:01:40] [PASSED] 16 VFs
[15:01:40] [PASSED] 17 VFs
[15:01:40] [PASSED] 18 VFs
[15:01:40] [PASSED] 19 VFs
[15:01:40] [PASSED] 20 VFs
[15:01:40] [PASSED] 21 VFs
[15:01:40] [PASSED] 22 VFs
[15:01:40] [PASSED] 23 VFs
[15:01:40] [PASSED] 24 VFs
[15:01:40] [PASSED] 25 VFs
[15:01:40] [PASSED] 26 VFs
[15:01:40] [PASSED] 27 VFs
[15:01:40] [PASSED] 28 VFs
[15:01:40] [PASSED] 29 VFs
[15:01:40] [PASSED] 30 VFs
[15:01:40] [PASSED] 31 VFs
[15:01:40] [PASSED] 32 VFs
[15:01:40] [PASSED] 33 VFs
[15:01:40] [PASSED] 34 VFs
[15:01:40] [PASSED] 35 VFs
[15:01:40] [PASSED] 36 VFs
[15:01:40] [PASSED] 37 VFs
[15:01:40] [PASSED] 38 VFs
[15:01:40] [PASSED] 39 VFs
[15:01:40] [PASSED] 40 VFs
[15:01:40] [PASSED] 41 VFs
[15:01:40] [PASSED] 42 VFs
[15:01:40] [PASSED] 43 VFs
[15:01:40] [PASSED] 44 VFs
[15:01:40] [PASSED] 45 VFs
[15:01:40] [PASSED] 46 VFs
[15:01:40] [PASSED] 47 VFs
[15:01:40] [PASSED] 48 VFs
[15:01:40] [PASSED] 49 VFs
[15:01:40] [PASSED] 50 VFs
[15:01:40] [PASSED] 51 VFs
[15:01:40] [PASSED] 52 VFs
[15:01:40] [PASSED] 53 VFs
[15:01:40] [PASSED] 54 VFs
[15:01:40] [PASSED] 55 VFs
[15:01:40] [PASSED] 56 VFs
[15:01:40] [PASSED] 57 VFs
[15:01:40] [PASSED] 58 VFs
[15:01:40] [PASSED] 59 VFs
[15:01:40] [PASSED] 60 VFs
[15:01:40] [PASSED] 61 VFs
[15:01:40] [PASSED] 62 VFs
[15:01:40] [PASSED] 63 VFs
[15:01:40] ================== [PASSED] fair_contexts ==================
[15:01:40] ===================== fair_doorbells  ======================
[15:01:40] [PASSED] 1 VF
[15:01:40] [PASSED] 2 VFs
[15:01:40] [PASSED] 3 VFs
[15:01:40] [PASSED] 4 VFs
[15:01:40] [PASSED] 5 VFs
[15:01:40] [PASSED] 6 VFs
[15:01:40] [PASSED] 7 VFs
[15:01:40] [PASSED] 8 VFs
[15:01:40] [PASSED] 9 VFs
[15:01:40] [PASSED] 10 VFs
[15:01:40] [PASSED] 11 VFs
[15:01:40] [PASSED] 12 VFs
[15:01:40] [PASSED] 13 VFs
[15:01:40] [PASSED] 14 VFs
[15:01:40] [PASSED] 15 VFs
[15:01:40] [PASSED] 16 VFs
[15:01:40] [PASSED] 17 VFs
[15:01:40] [PASSED] 18 VFs
[15:01:40] [PASSED] 19 VFs
[15:01:40] [PASSED] 20 VFs
[15:01:40] [PASSED] 21 VFs
[15:01:40] [PASSED] 22 VFs
[15:01:40] [PASSED] 23 VFs
[15:01:40] [PASSED] 24 VFs
[15:01:40] [PASSED] 25 VFs
[15:01:40] [PASSED] 26 VFs
[15:01:40] [PASSED] 27 VFs
[15:01:40] [PASSED] 28 VFs
[15:01:40] [PASSED] 29 VFs
[15:01:40] [PASSED] 30 VFs
[15:01:40] [PASSED] 31 VFs
[15:01:40] [PASSED] 32 VFs
[15:01:40] [PASSED] 33 VFs
[15:01:40] [PASSED] 34 VFs
[15:01:40] [PASSED] 35 VFs
[15:01:40] [PASSED] 36 VFs
[15:01:40] [PASSED] 37 VFs
[15:01:40] [PASSED] 38 VFs
[15:01:40] [PASSED] 39 VFs
[15:01:40] [PASSED] 40 VFs
[15:01:40] [PASSED] 41 VFs
[15:01:40] [PASSED] 42 VFs
[15:01:40] [PASSED] 43 VFs
[15:01:40] [PASSED] 44 VFs
[15:01:40] [PASSED] 45 VFs
[15:01:40] [PASSED] 46 VFs
[15:01:40] [PASSED] 47 VFs
[15:01:40] [PASSED] 48 VFs
[15:01:40] [PASSED] 49 VFs
[15:01:40] [PASSED] 50 VFs
[15:01:40] [PASSED] 51 VFs
[15:01:40] [PASSED] 52 VFs
[15:01:40] [PASSED] 53 VFs
[15:01:40] [PASSED] 54 VFs
[15:01:40] [PASSED] 55 VFs
[15:01:40] [PASSED] 56 VFs
[15:01:40] [PASSED] 57 VFs
[15:01:40] [PASSED] 58 VFs
[15:01:40] [PASSED] 59 VFs
[15:01:40] [PASSED] 60 VFs
[15:01:40] [PASSED] 61 VFs
[15:01:40] [PASSED] 62 VFs
[15:01:40] [PASSED] 63 VFs
[15:01:40] ================= [PASSED] fair_doorbells ==================
[15:01:40] ======================== fair_ggtt  ========================
[15:01:40] [PASSED] 1 VF
[15:01:40] [PASSED] 2 VFs
[15:01:40] [PASSED] 3 VFs
[15:01:40] [PASSED] 4 VFs
[15:01:40] [PASSED] 5 VFs
[15:01:40] [PASSED] 6 VFs
[15:01:40] [PASSED] 7 VFs
[15:01:40] [PASSED] 8 VFs
[15:01:40] [PASSED] 9 VFs
[15:01:40] [PASSED] 10 VFs
[15:01:40] [PASSED] 11 VFs
[15:01:40] [PASSED] 12 VFs
[15:01:40] [PASSED] 13 VFs
[15:01:40] [PASSED] 14 VFs
[15:01:40] [PASSED] 15 VFs
[15:01:40] [PASSED] 16 VFs
[15:01:40] [PASSED] 17 VFs
[15:01:40] [PASSED] 18 VFs
[15:01:40] [PASSED] 19 VFs
[15:01:40] [PASSED] 20 VFs
[15:01:40] [PASSED] 21 VFs
[15:01:40] [PASSED] 22 VFs
[15:01:40] [PASSED] 23 VFs
[15:01:40] [PASSED] 24 VFs
[15:01:40] [PASSED] 25 VFs
[15:01:40] [PASSED] 26 VFs
[15:01:40] [PASSED] 27 VFs
[15:01:40] [PASSED] 28 VFs
[15:01:40] [PASSED] 29 VFs
[15:01:40] [PASSED] 30 VFs
[15:01:40] [PASSED] 31 VFs
[15:01:40] [PASSED] 32 VFs
[15:01:40] [PASSED] 33 VFs
[15:01:40] [PASSED] 34 VFs
[15:01:40] [PASSED] 35 VFs
[15:01:40] [PASSED] 36 VFs
[15:01:40] [PASSED] 37 VFs
[15:01:40] [PASSED] 38 VFs
[15:01:40] [PASSED] 39 VFs
[15:01:40] [PASSED] 40 VFs
[15:01:40] [PASSED] 41 VFs
[15:01:40] [PASSED] 42 VFs
[15:01:40] [PASSED] 43 VFs
[15:01:40] [PASSED] 44 VFs
[15:01:40] [PASSED] 45 VFs
[15:01:40] [PASSED] 46 VFs
[15:01:40] [PASSED] 47 VFs
[15:01:40] [PASSED] 48 VFs
[15:01:40] [PASSED] 49 VFs
[15:01:40] [PASSED] 50 VFs
[15:01:40] [PASSED] 51 VFs
[15:01:40] [PASSED] 52 VFs
[15:01:40] [PASSED] 53 VFs
[15:01:40] [PASSED] 54 VFs
[15:01:40] [PASSED] 55 VFs
[15:01:40] [PASSED] 56 VFs
[15:01:40] [PASSED] 57 VFs
[15:01:40] [PASSED] 58 VFs
[15:01:40] [PASSED] 59 VFs
[15:01:40] [PASSED] 60 VFs
[15:01:40] [PASSED] 61 VFs
[15:01:40] [PASSED] 62 VFs
[15:01:40] [PASSED] 63 VFs
[15:01:40] ==================== [PASSED] fair_ggtt ====================
[15:01:40] ======================== fair_vram  ========================
[15:01:40] [PASSED] 1 VF
[15:01:40] [PASSED] 2 VFs
[15:01:40] [PASSED] 3 VFs
[15:01:40] [PASSED] 4 VFs
[15:01:40] [PASSED] 5 VFs
[15:01:40] [PASSED] 6 VFs
[15:01:40] [PASSED] 7 VFs
[15:01:40] [PASSED] 8 VFs
[15:01:40] [PASSED] 9 VFs
[15:01:40] [PASSED] 10 VFs
[15:01:40] [PASSED] 11 VFs
[15:01:40] [PASSED] 12 VFs
[15:01:40] [PASSED] 13 VFs
[15:01:40] [PASSED] 14 VFs
[15:01:40] [PASSED] 15 VFs
[15:01:40] [PASSED] 16 VFs
[15:01:40] [PASSED] 17 VFs
[15:01:40] [PASSED] 18 VFs
[15:01:40] [PASSED] 19 VFs
[15:01:40] [PASSED] 20 VFs
[15:01:40] [PASSED] 21 VFs
[15:01:40] [PASSED] 22 VFs
[15:01:40] [PASSED] 23 VFs
[15:01:40] [PASSED] 24 VFs
[15:01:40] [PASSED] 25 VFs
[15:01:40] [PASSED] 26 VFs
[15:01:40] [PASSED] 27 VFs
[15:01:40] [PASSED] 28 VFs
[15:01:40] [PASSED] 29 VFs
[15:01:40] [PASSED] 30 VFs
[15:01:40] [PASSED] 31 VFs
[15:01:40] [PASSED] 32 VFs
[15:01:40] [PASSED] 33 VFs
[15:01:40] [PASSED] 34 VFs
[15:01:40] [PASSED] 35 VFs
[15:01:40] [PASSED] 36 VFs
[15:01:40] [PASSED] 37 VFs
[15:01:40] [PASSED] 38 VFs
[15:01:40] [PASSED] 39 VFs
[15:01:40] [PASSED] 40 VFs
[15:01:40] [PASSED] 41 VFs
[15:01:40] [PASSED] 42 VFs
[15:01:40] [PASSED] 43 VFs
[15:01:40] [PASSED] 44 VFs
[15:01:40] [PASSED] 45 VFs
[15:01:40] [PASSED] 46 VFs
[15:01:40] [PASSED] 47 VFs
[15:01:40] [PASSED] 48 VFs
[15:01:40] [PASSED] 49 VFs
[15:01:40] [PASSED] 50 VFs
[15:01:40] [PASSED] 51 VFs
[15:01:40] [PASSED] 52 VFs
[15:01:40] [PASSED] 53 VFs
[15:01:40] [PASSED] 54 VFs
[15:01:40] [PASSED] 55 VFs
[15:01:40] [PASSED] 56 VFs
[15:01:40] [PASSED] 57 VFs
[15:01:40] [PASSED] 58 VFs
[15:01:40] [PASSED] 59 VFs
[15:01:40] [PASSED] 60 VFs
[15:01:40] [PASSED] 61 VFs
[15:01:40] [PASSED] 62 VFs
[15:01:40] [PASSED] 63 VFs
[15:01:40] ==================== [PASSED] fair_vram ====================
[15:01:40] ================== [PASSED] pf_gt_config ===================
[15:01:40] ===================== lmtt (1 subtest) =====================
[15:01:40] ======================== test_ops  =========================
[15:01:40] [PASSED] 2-level
[15:01:40] [PASSED] multi-level
[15:01:40] ==================== [PASSED] test_ops =====================
[15:01:40] ====================== [PASSED] lmtt =======================
[15:01:40] ================= pf_service (11 subtests) =================
[15:01:40] [PASSED] pf_negotiate_any
[15:01:40] [PASSED] pf_negotiate_base_match
[15:01:40] [PASSED] pf_negotiate_base_newer
[15:01:40] [PASSED] pf_negotiate_base_next
[15:01:40] [SKIPPED] pf_negotiate_base_older
[15:01:40] [PASSED] pf_negotiate_base_prev
[15:01:40] [PASSED] pf_negotiate_latest_match
[15:01:40] [PASSED] pf_negotiate_latest_newer
[15:01:40] [PASSED] pf_negotiate_latest_next
[15:01:40] [SKIPPED] pf_negotiate_latest_older
[15:01:40] [SKIPPED] pf_negotiate_latest_prev
[15:01:40] =================== [PASSED] pf_service ====================
[15:01:40] ================= xe_guc_g2g (2 subtests) ==================
[15:01:40] ============== xe_live_guc_g2g_kunit_default  ==============
[15:01:40] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[15:01:40] ============== xe_live_guc_g2g_kunit_allmem  ===============
[15:01:40] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[15:01:40] =================== [SKIPPED] xe_guc_g2g ===================
[15:01:40] =================== xe_mocs (2 subtests) ===================
[15:01:40] ================ xe_live_mocs_kernel_kunit  ================
[15:01:40] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[15:01:40] ================ xe_live_mocs_reset_kunit  =================
[15:01:40] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[15:01:40] ==================== [SKIPPED] xe_mocs =====================
[15:01:40] ================= xe_migrate (2 subtests) ==================
[15:01:40] ================= xe_migrate_sanity_kunit  =================
[15:01:40] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[15:01:40] ================== xe_validate_ccs_kunit  ==================
[15:01:40] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[15:01:40] =================== [SKIPPED] xe_migrate ===================
[15:01:40] ================== xe_dma_buf (1 subtest) ==================
[15:01:40] ==================== xe_dma_buf_kunit  =====================
[15:01:40] ================ [SKIPPED] xe_dma_buf_kunit ================
[15:01:40] =================== [SKIPPED] xe_dma_buf ===================
[15:01:40] ================= xe_bo_shrink (1 subtest) =================
[15:01:40] =================== xe_bo_shrink_kunit  ====================
[15:01:40] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[15:01:40] ================== [SKIPPED] xe_bo_shrink ==================
[15:01:40] ==================== xe_bo (2 subtests) ====================
[15:01:40] ================== xe_ccs_migrate_kunit  ===================
[15:01:40] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[15:01:40] ==================== xe_bo_evict_kunit  ====================
[15:01:40] =============== [SKIPPED] xe_bo_evict_kunit ================
[15:01:40] ===================== [SKIPPED] xe_bo ======================
[15:01:40] ==================== args (13 subtests) ====================
[15:01:40] [PASSED] count_args_test
[15:01:40] [PASSED] call_args_example
[15:01:40] [PASSED] call_args_test
[15:01:40] [PASSED] drop_first_arg_example
[15:01:40] [PASSED] drop_first_arg_test
[15:01:40] [PASSED] first_arg_example
[15:01:40] [PASSED] first_arg_test
[15:01:40] [PASSED] last_arg_example
[15:01:40] [PASSED] last_arg_test
[15:01:40] [PASSED] pick_arg_example
[15:01:40] [PASSED] if_args_example
[15:01:40] [PASSED] if_args_test
[15:01:40] [PASSED] sep_comma_example
[15:01:40] ====================== [PASSED] args =======================
[15:01:40] =================== xe_pci (3 subtests) ====================
[15:01:40] ==================== check_graphics_ip  ====================
[15:01:40] [PASSED] 12.00 Xe_LP
[15:01:40] [PASSED] 12.10 Xe_LP+
[15:01:40] [PASSED] 12.55 Xe_HPG
[15:01:40] [PASSED] 12.60 Xe_HPC
[15:01:40] [PASSED] 12.70 Xe_LPG
[15:01:40] [PASSED] 12.71 Xe_LPG
[15:01:40] [PASSED] 12.74 Xe_LPG+
[15:01:40] [PASSED] 20.01 Xe2_HPG
[15:01:40] [PASSED] 20.02 Xe2_HPG
[15:01:40] [PASSED] 20.04 Xe2_LPG
[15:01:40] [PASSED] 30.00 Xe3_LPG
[15:01:40] [PASSED] 30.01 Xe3_LPG
[15:01:40] [PASSED] 30.03 Xe3_LPG
[15:01:40] [PASSED] 30.04 Xe3_LPG
[15:01:40] [PASSED] 30.05 Xe3_LPG
[15:01:40] [PASSED] 35.10 Xe3p_LPG
[15:01:40] [PASSED] 35.11 Xe3p_XPC
[15:01:40] ================ [PASSED] check_graphics_ip ================
[15:01:40] ===================== check_media_ip  ======================
[15:01:40] [PASSED] 12.00 Xe_M
[15:01:40] [PASSED] 12.55 Xe_HPM
[15:01:40] [PASSED] 13.00 Xe_LPM+
[15:01:40] [PASSED] 13.01 Xe2_HPM
[15:01:40] [PASSED] 20.00 Xe2_LPM
[15:01:40] [PASSED] 30.00 Xe3_LPM
[15:01:40] [PASSED] 30.02 Xe3_LPM
[15:01:40] [PASSED] 35.00 Xe3p_LPM
[15:01:40] [PASSED] 35.03 Xe3p_HPM
[15:01:40] ================= [PASSED] check_media_ip ==================
[15:01:40] =================== check_platform_desc  ===================
[15:01:40] [PASSED] 0x9A60 (TIGERLAKE)
[15:01:40] [PASSED] 0x9A68 (TIGERLAKE)
[15:01:40] [PASSED] 0x9A70 (TIGERLAKE)
[15:01:40] [PASSED] 0x9A40 (TIGERLAKE)
[15:01:40] [PASSED] 0x9A49 (TIGERLAKE)
[15:01:40] [PASSED] 0x9A59 (TIGERLAKE)
[15:01:40] [PASSED] 0x9A78 (TIGERLAKE)
[15:01:40] [PASSED] 0x9AC0 (TIGERLAKE)
[15:01:40] [PASSED] 0x9AC9 (TIGERLAKE)
[15:01:40] [PASSED] 0x9AD9 (TIGERLAKE)
[15:01:40] [PASSED] 0x9AF8 (TIGERLAKE)
[15:01:40] [PASSED] 0x4C80 (ROCKETLAKE)
[15:01:40] [PASSED] 0x4C8A (ROCKETLAKE)
[15:01:40] [PASSED] 0x4C8B (ROCKETLAKE)
[15:01:40] [PASSED] 0x4C8C (ROCKETLAKE)
[15:01:40] [PASSED] 0x4C90 (ROCKETLAKE)
[15:01:40] [PASSED] 0x4C9A (ROCKETLAKE)
[15:01:40] [PASSED] 0x4680 (ALDERLAKE_S)
[15:01:40] [PASSED] 0x4682 (ALDERLAKE_S)
[15:01:40] [PASSED] 0x4688 (ALDERLAKE_S)
[15:01:40] [PASSED] 0x468A (ALDERLAKE_S)
[15:01:40] [PASSED] 0x468B (ALDERLAKE_S)
[15:01:40] [PASSED] 0x4690 (ALDERLAKE_S)
[15:01:40] [PASSED] 0x4692 (ALDERLAKE_S)
[15:01:40] [PASSED] 0x4693 (ALDERLAKE_S)
[15:01:40] [PASSED] 0x46A0 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46A1 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46A2 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46A3 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46A6 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46A8 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46AA (ALDERLAKE_P)
[15:01:40] [PASSED] 0x462A (ALDERLAKE_P)
[15:01:40] [PASSED] 0x4626 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x4628 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46B0 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46B1 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46B2 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46B3 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46C0 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46C1 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46C2 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46C3 (ALDERLAKE_P)
[15:01:40] [PASSED] 0x46D0 (ALDERLAKE_N)
[15:01:40] [PASSED] 0x46D1 (ALDERLAKE_N)
[15:01:40] [PASSED] 0x46D2 (ALDERLAKE_N)
[15:01:40] [PASSED] 0x46D3 (ALDERLAKE_N)
[15:01:40] [PASSED] 0x46D4 (ALDERLAKE_N)
[15:01:40] [PASSED] 0xA721 (ALDERLAKE_P)
[15:01:40] [PASSED] 0xA7A1 (ALDERLAKE_P)
[15:01:40] [PASSED] 0xA7A9 (ALDERLAKE_P)
[15:01:40] [PASSED] 0xA7AC (ALDERLAKE_P)
[15:01:40] [PASSED] 0xA7AD (ALDERLAKE_P)
[15:01:40] [PASSED] 0xA720 (ALDERLAKE_P)
[15:01:40] [PASSED] 0xA7A0 (ALDERLAKE_P)
[15:01:40] [PASSED] 0xA7A8 (ALDERLAKE_P)
[15:01:40] [PASSED] 0xA7AA (ALDERLAKE_P)
[15:01:40] [PASSED] 0xA7AB (ALDERLAKE_P)
[15:01:40] [PASSED] 0xA780 (ALDERLAKE_S)
[15:01:40] [PASSED] 0xA781 (ALDERLAKE_S)
[15:01:40] [PASSED] 0xA782 (ALDERLAKE_S)
[15:01:40] [PASSED] 0xA783 (ALDERLAKE_S)
[15:01:40] [PASSED] 0xA788 (ALDERLAKE_S)
[15:01:40] [PASSED] 0xA789 (ALDERLAKE_S)
[15:01:40] [PASSED] 0xA78A (ALDERLAKE_S)
[15:01:40] [PASSED] 0xA78B (ALDERLAKE_S)
[15:01:40] [PASSED] 0x4905 (DG1)
[15:01:40] [PASSED] 0x4906 (DG1)
[15:01:40] [PASSED] 0x4907 (DG1)
[15:01:40] [PASSED] 0x4908 (DG1)
[15:01:40] [PASSED] 0x4909 (DG1)
[15:01:40] [PASSED] 0x56C0 (DG2)
[15:01:40] [PASSED] 0x56C2 (DG2)
[15:01:40] [PASSED] 0x56C1 (DG2)
[15:01:40] [PASSED] 0x7D51 (METEORLAKE)
[15:01:40] [PASSED] 0x7DD1 (METEORLAKE)
[15:01:40] [PASSED] 0x7D41 (METEORLAKE)
[15:01:40] [PASSED] 0x7D67 (METEORLAKE)
[15:01:40] [PASSED] 0xB640 (METEORLAKE)
[15:01:40] [PASSED] 0x56A0 (DG2)
[15:01:40] [PASSED] 0x56A1 (DG2)
[15:01:40] [PASSED] 0x56A2 (DG2)
[15:01:40] [PASSED] 0x56BE (DG2)
[15:01:40] [PASSED] 0x56BF (DG2)
[15:01:40] [PASSED] 0x5690 (DG2)
[15:01:40] [PASSED] 0x5691 (DG2)
[15:01:40] [PASSED] 0x5692 (DG2)
[15:01:40] [PASSED] 0x56A5 (DG2)
[15:01:40] [PASSED] 0x56A6 (DG2)
[15:01:40] [PASSED] 0x56B0 (DG2)
[15:01:40] [PASSED] 0x56B1 (DG2)
[15:01:40] [PASSED] 0x56BA (DG2)
[15:01:40] [PASSED] 0x56BB (DG2)
[15:01:40] [PASSED] 0x56BC (DG2)
[15:01:40] [PASSED] 0x56BD (DG2)
[15:01:40] [PASSED] 0x5693 (DG2)
[15:01:40] [PASSED] 0x5694 (DG2)
[15:01:40] [PASSED] 0x5695 (DG2)
[15:01:40] [PASSED] 0x56A3 (DG2)
[15:01:40] [PASSED] 0x56A4 (DG2)
[15:01:40] [PASSED] 0x56B2 (DG2)
[15:01:40] [PASSED] 0x56B3 (DG2)
[15:01:40] [PASSED] 0x5696 (DG2)
[15:01:40] [PASSED] 0x5697 (DG2)
[15:01:40] [PASSED] 0xB69 (PVC)
[15:01:40] [PASSED] 0xB6E (PVC)
[15:01:40] [PASSED] 0xBD4 (PVC)
[15:01:40] [PASSED] 0xBD5 (PVC)
[15:01:40] [PASSED] 0xBD6 (PVC)
[15:01:40] [PASSED] 0xBD7 (PVC)
[15:01:40] [PASSED] 0xBD8 (PVC)
[15:01:40] [PASSED] 0xBD9 (PVC)
[15:01:40] [PASSED] 0xBDA (PVC)
[15:01:40] [PASSED] 0xBDB (PVC)
[15:01:40] [PASSED] 0xBE0 (PVC)
[15:01:40] [PASSED] 0xBE1 (PVC)
[15:01:40] [PASSED] 0xBE5 (PVC)
[15:01:40] [PASSED] 0x7D40 (METEORLAKE)
[15:01:40] [PASSED] 0x7D45 (METEORLAKE)
[15:01:40] [PASSED] 0x7D55 (METEORLAKE)
[15:01:40] [PASSED] 0x7D60 (METEORLAKE)
[15:01:40] [PASSED] 0x7DD5 (METEORLAKE)
[15:01:40] [PASSED] 0x6420 (LUNARLAKE)
[15:01:40] [PASSED] 0x64A0 (LUNARLAKE)
[15:01:40] [PASSED] 0x64B0 (LUNARLAKE)
[15:01:40] [PASSED] 0xE202 (BATTLEMAGE)
[15:01:40] [PASSED] 0xE209 (BATTLEMAGE)
[15:01:40] [PASSED] 0xE20B (BATTLEMAGE)
[15:01:40] [PASSED] 0xE20C (BATTLEMAGE)
[15:01:40] [PASSED] 0xE20D (BATTLEMAGE)
[15:01:40] [PASSED] 0xE210 (BATTLEMAGE)
[15:01:40] [PASSED] 0xE211 (BATTLEMAGE)
[15:01:40] [PASSED] 0xE212 (BATTLEMAGE)
[15:01:40] [PASSED] 0xE216 (BATTLEMAGE)
[15:01:40] [PASSED] 0xE220 (BATTLEMAGE)
[15:01:40] [PASSED] 0xE221 (BATTLEMAGE)
[15:01:40] [PASSED] 0xE222 (BATTLEMAGE)
[15:01:40] [PASSED] 0xE223 (BATTLEMAGE)
[15:01:40] [PASSED] 0xB080 (PANTHERLAKE)
[15:01:40] [PASSED] 0xB081 (PANTHERLAKE)
[15:01:40] [PASSED] 0xB082 (PANTHERLAKE)
[15:01:40] [PASSED] 0xB083 (PANTHERLAKE)
[15:01:40] [PASSED] 0xB084 (PANTHERLAKE)
[15:01:40] [PASSED] 0xB085 (PANTHERLAKE)
[15:01:40] [PASSED] 0xB086 (PANTHERLAKE)
[15:01:40] [PASSED] 0xB087 (PANTHERLAKE)
[15:01:40] [PASSED] 0xB08F (PANTHERLAKE)
[15:01:40] [PASSED] 0xB090 (PANTHERLAKE)
[15:01:40] [PASSED] 0xB0A0 (PANTHERLAKE)
[15:01:40] [PASSED] 0xB0B0 (PANTHERLAKE)
[15:01:40] [PASSED] 0xFD80 (PANTHERLAKE)
[15:01:40] [PASSED] 0xFD81 (PANTHERLAKE)
[15:01:40] [PASSED] 0xD740 (NOVALAKE_S)
[15:01:40] [PASSED] 0xD741 (NOVALAKE_S)
[15:01:40] [PASSED] 0xD742 (NOVALAKE_S)
[15:01:40] [PASSED] 0xD743 (NOVALAKE_S)
[15:01:40] [PASSED] 0xD744 (NOVALAKE_S)
[15:01:40] [PASSED] 0xD745 (NOVALAKE_S)
[15:01:40] [PASSED] 0x674C (CRESCENTISLAND)
[15:01:40] [PASSED] 0x674D (CRESCENTISLAND)
[15:01:40] [PASSED] 0x674E (CRESCENTISLAND)
[15:01:40] [PASSED] 0x674F (CRESCENTISLAND)
[15:01:40] [PASSED] 0x6750 (CRESCENTISLAND)
[15:01:40] [PASSED] 0xD750 (NOVALAKE_P)
[15:01:40] [PASSED] 0xD751 (NOVALAKE_P)
[15:01:40] [PASSED] 0xD752 (NOVALAKE_P)
[15:01:40] [PASSED] 0xD753 (NOVALAKE_P)
[15:01:40] [PASSED] 0xD754 (NOVALAKE_P)
[15:01:40] [PASSED] 0xD755 (NOVALAKE_P)
[15:01:40] [PASSED] 0xD756 (NOVALAKE_P)
[15:01:40] [PASSED] 0xD757 (NOVALAKE_P)
[15:01:40] [PASSED] 0xD75F (NOVALAKE_P)
[15:01:40] =============== [PASSED] check_platform_desc ===============
[15:01:40] ===================== [PASSED] xe_pci ======================
[15:01:40] =================== xe_rtp (3 subtests) ====================
[15:01:40] =================== xe_rtp_rules_tests  ====================
[15:01:40] [PASSED] no
[15:01:40] [PASSED] yes
[15:01:40] [PASSED] no-and-no
[15:01:40] [PASSED] no-and-yes
[15:01:40] [PASSED] yes-and-no
[15:01:40] [PASSED] yes-and-yes
[15:01:40] [PASSED] no-or-no
[15:01:40] [PASSED] no-or-yes
[15:01:40] [PASSED] yes-or-no
[15:01:40] [PASSED] yes-or-yes
[15:01:40] [PASSED] no-yes-or-yes-no
[15:01:40] [PASSED] no-yes-or-yes-yes
[15:01:40] [PASSED] yes-yes-or-no-yes
[15:01:40] [PASSED] yes-yes-or-yes-yes
[15:01:40] [PASSED] no-no-or-yes-or-no
[15:01:40] [PASSED] or
[15:01:40] [PASSED] or-yes
[15:01:40] [PASSED] or-no
[15:01:40] [PASSED] yes-or
[15:01:40] [PASSED] no-or
[15:01:40] [PASSED] no-or-or-yes
[15:01:40] [PASSED] yes-or-or-no
[15:01:40] [PASSED] no-or-or-no
[15:01:40] [PASSED] missing-context-engine-class
[15:01:40] [PASSED] missing-context-engine-class-or-yes
[15:01:40] [PASSED] missing-context-engine-class-or-or-yes
[15:01:40] =============== [PASSED] xe_rtp_rules_tests ================
[15:01:40] =============== xe_rtp_process_to_sr_tests  ================
[15:01:40] [PASSED] coalesce-same-reg
[15:01:40] [PASSED] no-match-no-add
[15:01:40] [PASSED] two-regs-two-entries
[15:01:40] [PASSED] clr-one-set-other
[15:01:40] [PASSED] set-field
[15:01:40] [PASSED] conflict-duplicate
[15:01:40] [PASSED] conflict-not-disjoint
[15:01:40] [PASSED] conflict-reg-type
[15:01:40] [PASSED] bad-mcr-reg-forced-to-regular
[15:01:40] [PASSED] bad-regular-reg-forced-to-mcr
[15:01:40] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[15:01:40] ================== xe_rtp_process_tests  ===================
[15:01:40] [PASSED] active1
[15:01:40] [PASSED] active2
[15:01:40] [PASSED] active-inactive
[15:01:40] [PASSED] inactive-active
[15:01:40] [PASSED] inactive-active-inactive
[15:01:40] [PASSED] inactive-inactive-inactive
[15:01:40] ============== [PASSED] xe_rtp_process_tests ===============
[15:01:40] ===================== [PASSED] xe_rtp ======================
[15:01:40] ==================== xe_wa (1 subtest) =====================
[15:01:40] ======================== xe_wa_gt  =========================
[15:01:40] [PASSED] TIGERLAKE B0
[15:01:40] [PASSED] DG1 A0
[15:01:40] [PASSED] DG1 B0
[15:01:40] [PASSED] ALDERLAKE_S A0
[15:01:40] [PASSED] ALDERLAKE_S B0
[15:01:40] [PASSED] ALDERLAKE_S C0
[15:01:40] [PASSED] ALDERLAKE_S D0
[15:01:40] [PASSED] ALDERLAKE_P A0
[15:01:40] [PASSED] ALDERLAKE_P B0
[15:01:40] [PASSED] ALDERLAKE_P C0
[15:01:40] [PASSED] ALDERLAKE_S RPLS D0
[15:01:40] [PASSED] ALDERLAKE_P RPLU E0
[15:01:40] [PASSED] DG2 G10 C0
[15:01:40] [PASSED] DG2 G11 B1
[15:01:40] [PASSED] DG2 G12 A1
[15:01:40] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:01:40] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:01:40] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[15:01:40] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[15:01:40] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[15:01:40] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[15:01:40] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[15:01:40] ==================== [PASSED] xe_wa_gt =====================
[15:01:40] ====================== [PASSED] xe_wa ======================
[15:01:40] ============================================================
[15:01:40] Testing complete. Ran 624 tests: passed: 606, skipped: 18
[15:01:40] Elapsed time: 36.323s total, 4.275s configuring, 31.380s building, 0.632s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[15:01:40] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:01:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:02:07] Starting KUnit Kernel (1/1)...
[15:02:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:02:07] ============ drm_test_pick_cmdline (2 subtests) ============
[15:02:07] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[15:02:07] =============== drm_test_pick_cmdline_named  ===============
[15:02:07] [PASSED] NTSC
[15:02:07] [PASSED] NTSC-J
[15:02:07] [PASSED] PAL
[15:02:07] [PASSED] PAL-M
[15:02:07] =========== [PASSED] drm_test_pick_cmdline_named ===========
[15:02:07] ============== [PASSED] drm_test_pick_cmdline ==============
[15:02:07] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[15:02:07] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[15:02:07] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[15:02:07] =========== drm_validate_clone_mode (2 subtests) ===========
[15:02:07] ============== drm_test_check_in_clone_mode  ===============
[15:02:07] [PASSED] in_clone_mode
[15:02:07] [PASSED] not_in_clone_mode
[15:02:07] ========== [PASSED] drm_test_check_in_clone_mode ===========
[15:02:07] =============== drm_test_check_valid_clones  ===============
[15:02:07] [PASSED] not_in_clone_mode
[15:02:07] [PASSED] valid_clone
[15:02:07] [PASSED] invalid_clone
[15:02:07] =========== [PASSED] drm_test_check_valid_clones ===========
[15:02:07] ============= [PASSED] drm_validate_clone_mode =============
[15:02:07] ============= drm_validate_modeset (1 subtest) =============
[15:02:07] [PASSED] drm_test_check_connector_changed_modeset
[15:02:07] ============== [PASSED] drm_validate_modeset ===============
[15:02:07] ====== drm_test_bridge_get_current_state (2 subtests) ======
[15:02:07] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[15:02:07] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[15:02:07] ======== [PASSED] drm_test_bridge_get_current_state ========
[15:02:07] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[15:02:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[15:02:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[15:02:07] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[15:02:07] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[15:02:07] ============== drm_bridge_alloc (2 subtests) ===============
[15:02:07] [PASSED] drm_test_drm_bridge_alloc_basic
[15:02:07] [PASSED] drm_test_drm_bridge_alloc_get_put
[15:02:07] ================ [PASSED] drm_bridge_alloc =================
[15:02:07] ============= drm_cmdline_parser (40 subtests) =============
[15:02:07] [PASSED] drm_test_cmdline_force_d_only
[15:02:07] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:02:07] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:02:07] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:02:07] [PASSED] drm_test_cmdline_force_e_only
[15:02:07] [PASSED] drm_test_cmdline_res
[15:02:07] [PASSED] drm_test_cmdline_res_vesa
[15:02:07] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:02:07] [PASSED] drm_test_cmdline_res_rblank
[15:02:07] [PASSED] drm_test_cmdline_res_bpp
[15:02:07] [PASSED] drm_test_cmdline_res_refresh
[15:02:07] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:02:07] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:02:07] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:02:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:02:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:02:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:02:07] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:02:07] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:02:07] [PASSED] drm_test_cmdline_res_margins_force_on
[15:02:07] [PASSED] drm_test_cmdline_res_vesa_margins
[15:02:07] [PASSED] drm_test_cmdline_name
[15:02:07] [PASSED] drm_test_cmdline_name_bpp
[15:02:07] [PASSED] drm_test_cmdline_name_option
[15:02:07] [PASSED] drm_test_cmdline_name_bpp_option
[15:02:07] [PASSED] drm_test_cmdline_rotate_0
[15:02:07] [PASSED] drm_test_cmdline_rotate_90
[15:02:07] [PASSED] drm_test_cmdline_rotate_180
[15:02:07] [PASSED] drm_test_cmdline_rotate_270
[15:02:07] [PASSED] drm_test_cmdline_hmirror
[15:02:07] [PASSED] drm_test_cmdline_vmirror
[15:02:07] [PASSED] drm_test_cmdline_margin_options
[15:02:07] [PASSED] drm_test_cmdline_multiple_options
[15:02:07] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:02:07] [PASSED] drm_test_cmdline_extra_and_option
[15:02:07] [PASSED] drm_test_cmdline_freestanding_options
[15:02:07] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:02:07] [PASSED] drm_test_cmdline_panel_orientation
[15:02:07] ================ drm_test_cmdline_invalid  =================
[15:02:07] [PASSED] margin_only
[15:02:07] [PASSED] interlace_only
[15:02:07] [PASSED] res_missing_x
[15:02:07] [PASSED] res_missing_y
[15:02:07] [PASSED] res_bad_y
[15:02:07] [PASSED] res_missing_y_bpp
[15:02:07] [PASSED] res_bad_bpp
[15:02:07] [PASSED] res_bad_refresh
[15:02:07] [PASSED] res_bpp_refresh_force_on_off
[15:02:07] [PASSED] res_invalid_mode
[15:02:07] [PASSED] res_bpp_wrong_place_mode
[15:02:07] [PASSED] name_bpp_refresh
[15:02:07] [PASSED] name_refresh
[15:02:07] [PASSED] name_refresh_wrong_mode
[15:02:07] [PASSED] name_refresh_invalid_mode
[15:02:07] [PASSED] rotate_multiple
[15:02:07] [PASSED] rotate_invalid_val
[15:02:07] [PASSED] rotate_truncated
[15:02:07] [PASSED] invalid_option
[15:02:07] [PASSED] invalid_tv_option
[15:02:07] [PASSED] truncated_tv_option
[15:02:07] ============ [PASSED] drm_test_cmdline_invalid =============
[15:02:07] =============== drm_test_cmdline_tv_options  ===============
[15:02:07] [PASSED] NTSC
[15:02:07] [PASSED] NTSC_443
[15:02:07] [PASSED] NTSC_J
[15:02:07] [PASSED] PAL
[15:02:07] [PASSED] PAL_M
[15:02:07] [PASSED] PAL_N
[15:02:07] [PASSED] SECAM
[15:02:07] [PASSED] MONO_525
[15:02:07] [PASSED] MONO_625
[15:02:07] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:02:07] =============== [PASSED] drm_cmdline_parser ================
[15:02:07] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:02:07] [PASSED] drm_test_connector_hdmi_init_valid
[15:02:07] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:02:07] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:02:07] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:02:07] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:02:07] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:02:07] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:02:07] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:02:07] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[15:02:07] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:02:07] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:02:07] [PASSED] supported_formats=0x5 yuv420_allowed=1
[15:02:07] [PASSED] supported_formats=0x5 yuv420_allowed=0
[15:02:07] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:02:07] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:02:07] [PASSED] drm_test_connector_hdmi_init_null_product
[15:02:07] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:02:07] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:02:07] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:02:07] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:02:07] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:02:07] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:02:07] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:02:07] ========= drm_test_connector_hdmi_init_type_valid  =========
[15:02:07] [PASSED] HDMI-A
[15:02:07] [PASSED] HDMI-B
[15:02:07] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:02:07] ======== drm_test_connector_hdmi_init_type_invalid  ========
[15:02:07] [PASSED] Unknown
[15:02:07] [PASSED] VGA
[15:02:07] [PASSED] DVI-I
[15:02:07] [PASSED] DVI-D
[15:02:07] [PASSED] DVI-A
[15:02:07] [PASSED] Composite
[15:02:07] [PASSED] SVIDEO
[15:02:07] [PASSED] LVDS
[15:02:07] [PASSED] Component
[15:02:07] [PASSED] DIN
[15:02:07] [PASSED] DP
[15:02:07] [PASSED] TV
[15:02:07] [PASSED] eDP
[15:02:07] [PASSED] Virtual
[15:02:07] [PASSED] DSI
[15:02:07] [PASSED] DPI
[15:02:07] [PASSED] Writeback
[15:02:07] [PASSED] SPI
[15:02:07] [PASSED] USB
[15:02:07] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:02:07] ============ [PASSED] drmm_connector_hdmi_init =============
[15:02:07] ============= drmm_connector_init (3 subtests) =============
[15:02:07] [PASSED] drm_test_drmm_connector_init
[15:02:07] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:02:07] ========= drm_test_drmm_connector_init_type_valid  =========
[15:02:07] [PASSED] Unknown
[15:02:07] [PASSED] VGA
[15:02:07] [PASSED] DVI-I
[15:02:07] [PASSED] DVI-D
[15:02:07] [PASSED] DVI-A
[15:02:07] [PASSED] Composite
[15:02:07] [PASSED] SVIDEO
[15:02:07] [PASSED] LVDS
[15:02:07] [PASSED] Component
[15:02:07] [PASSED] DIN
[15:02:07] [PASSED] DP
[15:02:07] [PASSED] HDMI-A
[15:02:07] [PASSED] HDMI-B
[15:02:07] [PASSED] TV
[15:02:07] [PASSED] eDP
[15:02:07] [PASSED] Virtual
[15:02:07] [PASSED] DSI
[15:02:07] [PASSED] DPI
[15:02:07] [PASSED] Writeback
[15:02:07] [PASSED] SPI
[15:02:07] [PASSED] USB
[15:02:07] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:02:07] =============== [PASSED] drmm_connector_init ===============
[15:02:07] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_init
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:02:07] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[15:02:07] [PASSED] Unknown
[15:02:07] [PASSED] VGA
[15:02:07] [PASSED] DVI-I
[15:02:07] [PASSED] DVI-D
[15:02:07] [PASSED] DVI-A
[15:02:07] [PASSED] Composite
[15:02:07] [PASSED] SVIDEO
[15:02:07] [PASSED] LVDS
[15:02:07] [PASSED] Component
[15:02:07] [PASSED] DIN
[15:02:07] [PASSED] DP
[15:02:07] [PASSED] HDMI-A
[15:02:07] [PASSED] HDMI-B
[15:02:07] [PASSED] TV
[15:02:07] [PASSED] eDP
[15:02:07] [PASSED] Virtual
[15:02:07] [PASSED] DSI
[15:02:07] [PASSED] DPI
[15:02:07] [PASSED] Writeback
[15:02:07] [PASSED] SPI
[15:02:07] [PASSED] USB
[15:02:07] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:02:07] ======== drm_test_drm_connector_dynamic_init_name  =========
[15:02:07] [PASSED] Unknown
[15:02:07] [PASSED] VGA
[15:02:07] [PASSED] DVI-I
[15:02:07] [PASSED] DVI-D
[15:02:07] [PASSED] DVI-A
[15:02:07] [PASSED] Composite
[15:02:07] [PASSED] SVIDEO
[15:02:07] [PASSED] LVDS
[15:02:07] [PASSED] Component
[15:02:07] [PASSED] DIN
[15:02:07] [PASSED] DP
[15:02:07] [PASSED] HDMI-A
[15:02:07] [PASSED] HDMI-B
[15:02:07] [PASSED] TV
[15:02:07] [PASSED] eDP
[15:02:07] [PASSED] Virtual
[15:02:07] [PASSED] DSI
[15:02:07] [PASSED] DPI
[15:02:07] [PASSED] Writeback
[15:02:07] [PASSED] SPI
[15:02:07] [PASSED] USB
[15:02:07] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:02:07] =========== [PASSED] drm_connector_dynamic_init ============
[15:02:07] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:02:07] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:02:07] ======= drm_connector_dynamic_register (7 subtests) ========
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:02:07] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:02:07] ========= [PASSED] drm_connector_dynamic_register ==========
[15:02:07] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:02:07] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:02:07] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:02:07] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:02:07] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:02:07] ========== drm_test_get_tv_mode_from_name_valid  ===========
[15:02:07] [PASSED] NTSC
[15:02:07] [PASSED] NTSC-443
[15:02:07] [PASSED] NTSC-J
[15:02:07] [PASSED] PAL
[15:02:07] [PASSED] PAL-M
[15:02:07] [PASSED] PAL-N
[15:02:07] [PASSED] SECAM
[15:02:07] [PASSED] Mono
[15:02:07] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:02:07] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:02:07] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:02:07] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:02:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:02:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:02:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:02:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:02:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:02:07] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:02:07] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[15:02:07] [PASSED] VIC 96
[15:02:07] [PASSED] VIC 97
[15:02:07] [PASSED] VIC 101
[15:02:07] [PASSED] VIC 102
[15:02:07] [PASSED] VIC 106
[15:02:07] [PASSED] VIC 107
[15:02:07] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:02:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:02:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:02:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:02:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:02:07] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:02:07] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:02:07] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:02:07] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[15:02:07] [PASSED] Automatic
[15:02:07] [PASSED] Full
[15:02:07] [PASSED] Limited 16:235
[15:02:07] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:02:07] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:02:07] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:02:07] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:02:07] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[15:02:07] [PASSED] RGB
[15:02:07] [PASSED] YUV 4:2:0
[15:02:07] [PASSED] YUV 4:2:2
[15:02:07] [PASSED] YUV 4:4:4
[15:02:07] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:02:07] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:02:07] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:02:07] ============= drm_damage_helper (21 subtests) ==============
[15:02:07] [PASSED] drm_test_damage_iter_no_damage
[15:02:07] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:02:07] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:02:07] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:02:07] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:02:07] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:02:07] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:02:07] [PASSED] drm_test_damage_iter_simple_damage
[15:02:07] [PASSED] drm_test_damage_iter_single_damage
[15:02:07] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:02:07] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:02:07] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:02:07] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:02:07] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:02:07] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:02:07] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:02:07] [PASSED] drm_test_damage_iter_damage
[15:02:07] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:02:07] [PASSED] drm_test_damage_iter_damage_one_outside
[15:02:07] [PASSED] drm_test_damage_iter_damage_src_moved
[15:02:07] [PASSED] drm_test_damage_iter_damage_not_visible
[15:02:07] ================ [PASSED] drm_damage_helper ================
[15:02:07] ============== drm_dp_mst_helper (3 subtests) ==============
[15:02:07] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[15:02:07] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:02:07] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:02:07] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:02:07] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:02:07] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:02:07] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:02:07] ============== drm_test_dp_mst_calc_pbn_div  ===============
[15:02:07] [PASSED] Link rate 2000000 lane count 4
[15:02:07] [PASSED] Link rate 2000000 lane count 2
[15:02:07] [PASSED] Link rate 2000000 lane count 1
[15:02:07] [PASSED] Link rate 1350000 lane count 4
[15:02:07] [PASSED] Link rate 1350000 lane count 2
[15:02:07] [PASSED] Link rate 1350000 lane count 1
[15:02:07] [PASSED] Link rate 1000000 lane count 4
[15:02:07] [PASSED] Link rate 1000000 lane count 2
[15:02:07] [PASSED] Link rate 1000000 lane count 1
[15:02:07] [PASSED] Link rate 810000 lane count 4
[15:02:07] [PASSED] Link rate 810000 lane count 2
[15:02:07] [PASSED] Link rate 810000 lane count 1
[15:02:07] [PASSED] Link rate 540000 lane count 4
[15:02:07] [PASSED] Link rate 540000 lane count 2
[15:02:07] [PASSED] Link rate 540000 lane count 1
[15:02:07] [PASSED] Link rate 270000 lane count 4
[15:02:07] [PASSED] Link rate 270000 lane count 2
[15:02:07] [PASSED] Link rate 270000 lane count 1
[15:02:07] [PASSED] Link rate 162000 lane count 4
[15:02:07] [PASSED] Link rate 162000 lane count 2
[15:02:07] [PASSED] Link rate 162000 lane count 1
[15:02:07] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:02:07] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[15:02:07] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:02:07] [PASSED] DP_POWER_UP_PHY with port number
[15:02:07] [PASSED] DP_POWER_DOWN_PHY with port number
[15:02:07] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:02:07] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:02:07] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:02:07] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:02:07] [PASSED] DP_QUERY_PAYLOAD with port number
[15:02:07] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:02:07] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:02:07] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:02:07] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:02:07] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:02:07] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:02:07] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:02:07] [PASSED] DP_REMOTE_I2C_READ with port number
[15:02:07] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:02:07] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:02:07] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:02:07] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:02:07] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:02:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:02:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:02:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:02:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:02:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:02:07] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:02:07] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:02:07] ================ [PASSED] drm_dp_mst_helper ================
[15:02:07] ================== drm_exec (7 subtests) ===================
[15:02:07] [PASSED] sanitycheck
[15:02:07] [PASSED] test_lock
[15:02:07] [PASSED] test_lock_unlock
[15:02:07] [PASSED] test_duplicates
[15:02:07] [PASSED] test_prepare
[15:02:07] [PASSED] test_prepare_array
[15:02:07] [PASSED] test_multiple_loops
[15:02:07] ==================== [PASSED] drm_exec =====================
[15:02:07] =========== drm_format_helper_test (17 subtests) ===========
[15:02:07] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:02:07] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:02:07] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:02:07] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:02:07] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:02:07] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:02:07] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:02:07] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:02:07] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:02:07] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:02:07] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:02:07] ============== drm_test_fb_xrgb8888_to_mono  ===============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:02:07] ==================== drm_test_fb_swab  =====================
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ================ [PASSED] drm_test_fb_swab =================
[15:02:07] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:02:07] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[15:02:07] [PASSED] single_pixel_source_buffer
[15:02:07] [PASSED] single_pixel_clip_rectangle
[15:02:07] [PASSED] well_known_colors
[15:02:07] [PASSED] destination_pitch
[15:02:07] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:02:07] ================= drm_test_fb_clip_offset  =================
[15:02:07] [PASSED] pass through
[15:02:07] [PASSED] horizontal offset
[15:02:07] [PASSED] vertical offset
[15:02:07] [PASSED] horizontal and vertical offset
[15:02:07] [PASSED] horizontal offset (custom pitch)
[15:02:07] [PASSED] vertical offset (custom pitch)
[15:02:07] [PASSED] horizontal and vertical offset (custom pitch)
[15:02:07] ============= [PASSED] drm_test_fb_clip_offset =============
[15:02:07] =================== drm_test_fb_memcpy  ====================
[15:02:07] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:02:07] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:02:07] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:02:07] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:02:07] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:02:07] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:02:07] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:02:07] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:02:07] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:02:07] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:02:07] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:02:07] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:02:07] =============== [PASSED] drm_test_fb_memcpy ================
[15:02:07] ============= [PASSED] drm_format_helper_test ==============
[15:02:07] ================= drm_format (18 subtests) =================
[15:02:07] [PASSED] drm_test_format_block_width_invalid
[15:02:07] [PASSED] drm_test_format_block_width_one_plane
[15:02:07] [PASSED] drm_test_format_block_width_two_plane
[15:02:07] [PASSED] drm_test_format_block_width_three_plane
[15:02:07] [PASSED] drm_test_format_block_width_tiled
[15:02:07] [PASSED] drm_test_format_block_height_invalid
[15:02:07] [PASSED] drm_test_format_block_height_one_plane
[15:02:07] [PASSED] drm_test_format_block_height_two_plane
[15:02:07] [PASSED] drm_test_format_block_height_three_plane
[15:02:07] [PASSED] drm_test_format_block_height_tiled
[15:02:07] [PASSED] drm_test_format_min_pitch_invalid
[15:02:07] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:02:07] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:02:07] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:02:07] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:02:07] [PASSED] drm_test_format_min_pitch_two_plane
[15:02:07] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:02:07] [PASSED] drm_test_format_min_pitch_tiled
[15:02:07] =================== [PASSED] drm_format ====================
[15:02:07] ============== drm_framebuffer (10 subtests) ===============
[15:02:07] ========== drm_test_framebuffer_check_src_coords  ==========
[15:02:07] [PASSED] Success: source fits into fb
[15:02:07] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:02:07] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:02:07] [PASSED] Fail: overflowing fb with source width
[15:02:07] [PASSED] Fail: overflowing fb with source height
[15:02:07] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:02:07] [PASSED] drm_test_framebuffer_cleanup
[15:02:07] =============== drm_test_framebuffer_create  ===============
[15:02:07] [PASSED] ABGR8888 normal sizes
[15:02:07] [PASSED] ABGR8888 max sizes
[15:02:07] [PASSED] ABGR8888 pitch greater than min required
[15:02:07] [PASSED] ABGR8888 pitch less than min required
[15:02:07] [PASSED] ABGR8888 Invalid width
[15:02:07] [PASSED] ABGR8888 Invalid buffer handle
[15:02:07] [PASSED] No pixel format
[15:02:07] [PASSED] ABGR8888 Width 0
[15:02:07] [PASSED] ABGR8888 Height 0
[15:02:07] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:02:07] [PASSED] ABGR8888 Large buffer offset
[15:02:07] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:02:07] [PASSED] ABGR8888 Invalid flag
[15:02:07] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:02:07] [PASSED] ABGR8888 Valid buffer modifier
[15:02:07] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:02:07] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:02:07] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:02:07] [PASSED] NV12 Normal sizes
[15:02:07] [PASSED] NV12 Max sizes
[15:02:07] [PASSED] NV12 Invalid pitch
[15:02:07] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:02:07] [PASSED] NV12 different  modifier per-plane
[15:02:07] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:02:07] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:02:07] [PASSED] NV12 Modifier for inexistent plane
[15:02:07] [PASSED] NV12 Handle for inexistent plane
[15:02:07] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:02:07] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:02:07] [PASSED] YVU420 Normal sizes
[15:02:07] [PASSED] YVU420 Max sizes
[15:02:07] [PASSED] YVU420 Invalid pitch
[15:02:07] [PASSED] YVU420 Different pitches
[15:02:07] [PASSED] YVU420 Different buffer offsets/pitches
[15:02:07] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:02:07] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:02:07] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:02:07] [PASSED] YVU420 Valid modifier
[15:02:07] [PASSED] YVU420 Different modifiers per plane
[15:02:07] [PASSED] YVU420 Modifier for inexistent plane
[15:02:07] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:02:07] [PASSED] X0L2 Normal sizes
[15:02:07] [PASSED] X0L2 Max sizes
[15:02:07] [PASSED] X0L2 Invalid pitch
[15:02:07] [PASSED] X0L2 Pitch greater than minimum required
[15:02:07] [PASSED] X0L2 Handle for inexistent plane
[15:02:07] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:02:07] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:02:07] [PASSED] X0L2 Valid modifier
[15:02:07] [PASSED] X0L2 Modifier for inexistent plane
[15:02:07] =========== [PASSED] drm_test_framebuffer_create ===========
[15:02:07] [PASSED] drm_test_framebuffer_free
[15:02:07] [PASSED] drm_test_framebuffer_init
[15:02:07] [PASSED] drm_test_framebuffer_init_bad_format
[15:02:07] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:02:07] [PASSED] drm_test_framebuffer_lookup
[15:02:07] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:02:07] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:02:07] ================= [PASSED] drm_framebuffer =================
[15:02:07] ================ drm_gem_shmem (8 subtests) ================
[15:02:07] [PASSED] drm_gem_shmem_test_obj_create
[15:02:07] [PASSED] drm_gem_shmem_test_obj_create_private
[15:02:07] [PASSED] drm_gem_shmem_test_pin_pages
[15:02:07] [PASSED] drm_gem_shmem_test_vmap
[15:02:07] [PASSED] drm_gem_shmem_test_get_sg_table
[15:02:07] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:02:07] [PASSED] drm_gem_shmem_test_madvise
[15:02:07] [PASSED] drm_gem_shmem_test_purge
[15:02:07] ================== [PASSED] drm_gem_shmem ==================
[15:02:07] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[15:02:07] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:02:07] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:02:07] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:02:07] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:02:07] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:02:07] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:02:07] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[15:02:07] [PASSED] Automatic
[15:02:07] [PASSED] Full
[15:02:07] [PASSED] Limited 16:235
[15:02:07] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:02:07] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:02:07] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:02:07] [PASSED] drm_test_check_disable_connector
[15:02:07] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:02:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:02:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:02:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:02:07] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:02:07] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:02:07] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:02:07] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:02:07] [PASSED] drm_test_check_output_bpc_dvi
[15:02:07] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:02:07] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:02:07] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:02:07] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:02:07] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:02:07] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:02:07] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:02:07] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:02:07] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:02:07] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:02:07] [PASSED] drm_test_check_broadcast_rgb_value
[15:02:07] [PASSED] drm_test_check_bpc_8_value
[15:02:07] [PASSED] drm_test_check_bpc_10_value
[15:02:07] [PASSED] drm_test_check_bpc_12_value
[15:02:07] [PASSED] drm_test_check_format_value
[15:02:07] [PASSED] drm_test_check_tmds_char_value
[15:02:07] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:02:07] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[15:02:07] [PASSED] drm_test_check_mode_valid
[15:02:07] [PASSED] drm_test_check_mode_valid_reject
[15:02:07] [PASSED] drm_test_check_mode_valid_reject_rate
[15:02:07] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:02:07] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:02:07] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[15:02:07] [PASSED] drm_test_check_infoframes
[15:02:07] [PASSED] drm_test_check_reject_avi_infoframe
[15:02:07] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[15:02:07] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[15:02:07] [PASSED] drm_test_check_reject_audio_infoframe
[15:02:07] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[15:02:07] ================= drm_managed (2 subtests) =================
[15:02:07] [PASSED] drm_test_managed_release_action
[15:02:07] [PASSED] drm_test_managed_run_action
[15:02:07] =================== [PASSED] drm_managed ===================
[15:02:07] =================== drm_mm (6 subtests) ====================
[15:02:07] [PASSED] drm_test_mm_init
[15:02:07] [PASSED] drm_test_mm_debug
[15:02:07] [PASSED] drm_test_mm_align32
[15:02:07] [PASSED] drm_test_mm_align64
[15:02:07] [PASSED] drm_test_mm_lowest
[15:02:07] [PASSED] drm_test_mm_highest
[15:02:07] ===================== [PASSED] drm_mm ======================
[15:02:07] ============= drm_modes_analog_tv (5 subtests) =============
[15:02:07] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:02:07] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:02:07] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:02:07] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:02:07] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:02:07] =============== [PASSED] drm_modes_analog_tv ===============
[15:02:07] ============== drm_plane_helper (2 subtests) ===============
[15:02:07] =============== drm_test_check_plane_state  ================
[15:02:07] [PASSED] clipping_simple
[15:02:07] [PASSED] clipping_rotate_reflect
[15:02:07] [PASSED] positioning_simple
[15:02:07] [PASSED] upscaling
[15:02:07] [PASSED] downscaling
[15:02:07] [PASSED] rounding1
[15:02:07] [PASSED] rounding2
[15:02:07] [PASSED] rounding3
[15:02:07] [PASSED] rounding4
[15:02:07] =========== [PASSED] drm_test_check_plane_state ============
[15:02:07] =========== drm_test_check_invalid_plane_state  ============
[15:02:07] [PASSED] positioning_invalid
[15:02:07] [PASSED] upscaling_invalid
[15:02:07] [PASSED] downscaling_invalid
[15:02:07] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:02:07] ================ [PASSED] drm_plane_helper =================
[15:02:07] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:02:07] ====== drm_test_connector_helper_tv_get_modes_check  =======
[15:02:07] [PASSED] None
[15:02:07] [PASSED] PAL
[15:02:07] [PASSED] NTSC
[15:02:07] [PASSED] Both, NTSC Default
[15:02:07] [PASSED] Both, PAL Default
[15:02:07] [PASSED] Both, NTSC Default, with PAL on command-line
[15:02:07] [PASSED] Both, PAL Default, with NTSC on command-line
[15:02:07] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:02:07] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:02:07] ================== drm_rect (9 subtests) ===================
[15:02:07] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:02:07] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:02:07] [PASSED] drm_test_rect_clip_scaled_clipped
[15:02:07] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:02:07] ================= drm_test_rect_intersect  =================
[15:02:07] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:02:07] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:02:07] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:02:07] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:02:07] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:02:07] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:02:07] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:02:07] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:02:07] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:02:07] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:02:07] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:02:07] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:02:07] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:02:07] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:02:07] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[15:02:07] ============= [PASSED] drm_test_rect_intersect =============
[15:02:07] ================ drm_test_rect_calc_hscale  ================
[15:02:07] [PASSED] normal use
[15:02:07] [PASSED] out of max range
[15:02:07] [PASSED] out of min range
[15:02:07] [PASSED] zero dst
[15:02:07] [PASSED] negative src
[15:02:07] [PASSED] negative dst
[15:02:07] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:02:07] ================ drm_test_rect_calc_vscale  ================
[15:02:07] [PASSED] normal use
[15:02:07] [PASSED] out of max range
[15:02:07] [PASSED] out of min range
[15:02:07] [PASSED] zero dst
[15:02:07] [PASSED] negative src
[15:02:07] [PASSED] negative dst
[15:02:07] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:02:07] ================== drm_test_rect_rotate  ===================
[15:02:07] [PASSED] reflect-x
[15:02:07] [PASSED] reflect-y
[15:02:07] [PASSED] rotate-0
[15:02:07] [PASSED] rotate-90
[15:02:07] [PASSED] rotate-180
[15:02:07] [PASSED] rotate-270
[15:02:07] ============== [PASSED] drm_test_rect_rotate ===============
[15:02:07] ================ drm_test_rect_rotate_inv  =================
[15:02:07] [PASSED] reflect-x
[15:02:07] [PASSED] reflect-y
[15:02:07] [PASSED] rotate-0
[15:02:07] [PASSED] rotate-90
[15:02:07] [PASSED] rotate-180
[15:02:07] [PASSED] rotate-270
[15:02:07] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:02:07] ==================== [PASSED] drm_rect =====================
[15:02:07] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:02:07] ============ drm_test_sysfb_build_fourcc_list  =============
[15:02:07] [PASSED] no native formats
[15:02:07] [PASSED] XRGB8888 as native format
[15:02:07] [PASSED] remove duplicates
[15:02:07] [PASSED] convert alpha formats
[15:02:07] [PASSED] random formats
[15:02:07] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:02:07] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:02:07] ================== drm_fixp (2 subtests) ===================
[15:02:07] [PASSED] drm_test_int2fixp
[15:02:07] [PASSED] drm_test_sm2fixp
[15:02:07] ==================== [PASSED] drm_fixp =====================
[15:02:07] ============================================================
[15:02:07] Testing complete. Ran 621 tests: passed: 621
[15:02:07] Elapsed time: 26.241s total, 1.735s configuring, 24.375s building, 0.130s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:02:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:02:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:02:18] Starting KUnit Kernel (1/1)...
[15:02:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:02:18] ================= ttm_device (5 subtests) ==================
[15:02:18] [PASSED] ttm_device_init_basic
[15:02:18] [PASSED] ttm_device_init_multiple
[15:02:18] [PASSED] ttm_device_fini_basic
[15:02:18] [PASSED] ttm_device_init_no_vma_man
[15:02:18] ================== ttm_device_init_pools  ==================
[15:02:18] [PASSED] No DMA allocations, no DMA32 required
[15:02:18] [PASSED] DMA allocations, DMA32 required
[15:02:18] [PASSED] No DMA allocations, DMA32 required
[15:02:18] [PASSED] DMA allocations, no DMA32 required
[15:02:18] ============== [PASSED] ttm_device_init_pools ==============
[15:02:18] =================== [PASSED] ttm_device ====================
[15:02:18] ================== ttm_pool (8 subtests) ===================
[15:02:18] ================== ttm_pool_alloc_basic  ===================
[15:02:18] [PASSED] One page
[15:02:18] [PASSED] More than one page
[15:02:18] [PASSED] Above the allocation limit
[15:02:18] [PASSED] One page, with coherent DMA mappings enabled
[15:02:18] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:02:18] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:02:18] ============== ttm_pool_alloc_basic_dma_addr  ==============
[15:02:18] [PASSED] One page
[15:02:18] [PASSED] More than one page
[15:02:18] [PASSED] Above the allocation limit
[15:02:18] [PASSED] One page, with coherent DMA mappings enabled
[15:02:18] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:02:18] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:02:18] [PASSED] ttm_pool_alloc_order_caching_match
[15:02:18] [PASSED] ttm_pool_alloc_caching_mismatch
[15:02:18] [PASSED] ttm_pool_alloc_order_mismatch
[15:02:18] [PASSED] ttm_pool_free_dma_alloc
[15:02:18] [PASSED] ttm_pool_free_no_dma_alloc
[15:02:18] [PASSED] ttm_pool_fini_basic
[15:02:18] ==================== [PASSED] ttm_pool =====================
[15:02:18] ================ ttm_resource (8 subtests) =================
[15:02:18] ================= ttm_resource_init_basic  =================
[15:02:18] [PASSED] Init resource in TTM_PL_SYSTEM
[15:02:18] [PASSED] Init resource in TTM_PL_VRAM
[15:02:18] [PASSED] Init resource in a private placement
[15:02:18] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:02:18] ============= [PASSED] ttm_resource_init_basic =============
[15:02:18] [PASSED] ttm_resource_init_pinned
[15:02:18] [PASSED] ttm_resource_fini_basic
[15:02:18] [PASSED] ttm_resource_manager_init_basic
[15:02:18] [PASSED] ttm_resource_manager_usage_basic
[15:02:18] [PASSED] ttm_resource_manager_set_used_basic
[15:02:18] [PASSED] ttm_sys_man_alloc_basic
[15:02:18] [PASSED] ttm_sys_man_free_basic
[15:02:18] ================== [PASSED] ttm_resource ===================
[15:02:18] =================== ttm_tt (15 subtests) ===================
[15:02:18] ==================== ttm_tt_init_basic  ====================
[15:02:18] [PASSED] Page-aligned size
[15:02:18] [PASSED] Extra pages requested
[15:02:18] ================ [PASSED] ttm_tt_init_basic ================
[15:02:18] [PASSED] ttm_tt_init_misaligned
[15:02:18] [PASSED] ttm_tt_fini_basic
[15:02:18] [PASSED] ttm_tt_fini_sg
[15:02:18] [PASSED] ttm_tt_fini_shmem
[15:02:18] [PASSED] ttm_tt_create_basic
[15:02:18] [PASSED] ttm_tt_create_invalid_bo_type
[15:02:18] [PASSED] ttm_tt_create_ttm_exists
[15:02:18] [PASSED] ttm_tt_create_failed
[15:02:18] [PASSED] ttm_tt_destroy_basic
[15:02:18] [PASSED] ttm_tt_populate_null_ttm
[15:02:18] [PASSED] ttm_tt_populate_populated_ttm
[15:02:18] [PASSED] ttm_tt_unpopulate_basic
[15:02:18] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:02:18] [PASSED] ttm_tt_swapin_basic
[15:02:18] ===================== [PASSED] ttm_tt ======================
[15:02:18] =================== ttm_bo (14 subtests) ===================
[15:02:18] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[15:02:18] [PASSED] Cannot be interrupted and sleeps
[15:02:18] [PASSED] Cannot be interrupted, locks straight away
[15:02:18] [PASSED] Can be interrupted, sleeps
[15:02:18] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:02:18] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:02:18] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:02:18] [PASSED] ttm_bo_reserve_double_resv
[15:02:18] [PASSED] ttm_bo_reserve_interrupted
[15:02:18] [PASSED] ttm_bo_reserve_deadlock
[15:02:18] [PASSED] ttm_bo_unreserve_basic
[15:02:18] [PASSED] ttm_bo_unreserve_pinned
[15:02:18] [PASSED] ttm_bo_unreserve_bulk
[15:02:18] [PASSED] ttm_bo_fini_basic
[15:02:18] [PASSED] ttm_bo_fini_shared_resv
[15:02:18] [PASSED] ttm_bo_pin_basic
[15:02:18] [PASSED] ttm_bo_pin_unpin_resource
[15:02:18] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:02:18] ===================== [PASSED] ttm_bo ======================
[15:02:18] ============== ttm_bo_validate (22 subtests) ===============
[15:02:18] ============== ttm_bo_init_reserved_sys_man  ===============
[15:02:18] [PASSED] Buffer object for userspace
[15:02:18] [PASSED] Kernel buffer object
[15:02:18] [PASSED] Shared buffer object
[15:02:18] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:02:18] ============== ttm_bo_init_reserved_mock_man  ==============
[15:02:18] [PASSED] Buffer object for userspace
[15:02:18] [PASSED] Kernel buffer object
[15:02:18] [PASSED] Shared buffer object
[15:02:18] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:02:18] [PASSED] ttm_bo_init_reserved_resv
[15:02:18] ================== ttm_bo_validate_basic  ==================
[15:02:18] [PASSED] Buffer object for userspace
[15:02:18] [PASSED] Kernel buffer object
[15:02:18] [PASSED] Shared buffer object
[15:02:18] ============== [PASSED] ttm_bo_validate_basic ==============
[15:02:18] [PASSED] ttm_bo_validate_invalid_placement
[15:02:18] ============= ttm_bo_validate_same_placement  ==============
[15:02:18] [PASSED] System manager
[15:02:18] [PASSED] VRAM manager
[15:02:18] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:02:18] [PASSED] ttm_bo_validate_failed_alloc
[15:02:18] [PASSED] ttm_bo_validate_pinned
[15:02:18] [PASSED] ttm_bo_validate_busy_placement
[15:02:18] ================ ttm_bo_validate_multihop  =================
[15:02:18] [PASSED] Buffer object for userspace
[15:02:18] [PASSED] Kernel buffer object
[15:02:18] [PASSED] Shared buffer object
[15:02:18] ============ [PASSED] ttm_bo_validate_multihop =============
[15:02:18] ========== ttm_bo_validate_no_placement_signaled  ==========
[15:02:18] [PASSED] Buffer object in system domain, no page vector
[15:02:18] [PASSED] Buffer object in system domain with an existing page vector
[15:02:18] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:02:18] ======== ttm_bo_validate_no_placement_not_signaled  ========
[15:02:18] [PASSED] Buffer object for userspace
[15:02:18] [PASSED] Kernel buffer object
[15:02:18] [PASSED] Shared buffer object
[15:02:18] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:02:18] [PASSED] ttm_bo_validate_move_fence_signaled
[15:02:18] ========= ttm_bo_validate_move_fence_not_signaled  =========
[15:02:18] [PASSED] Waits for GPU
[15:02:18] [PASSED] Tries to lock straight away
[15:02:18] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:02:18] [PASSED] ttm_bo_validate_swapout
[15:02:18] [PASSED] ttm_bo_validate_happy_evict
[15:02:18] [PASSED] ttm_bo_validate_all_pinned_evict
[15:02:18] [PASSED] ttm_bo_validate_allowed_only_evict
[15:02:18] [PASSED] ttm_bo_validate_deleted_evict
[15:02:18] [PASSED] ttm_bo_validate_busy_domain_evict
[15:02:18] [PASSED] ttm_bo_validate_evict_gutting
[15:02:18] [PASSED] ttm_bo_validate_recrusive_evict
[15:02:18] ================= [PASSED] ttm_bo_validate =================
[15:02:18] ============================================================
[15:02:18] Testing complete. Ran 102 tests: passed: 102
[15:02:18] Elapsed time: 11.475s total, 1.765s configuring, 9.495s building, 0.182s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for CMTG enablement (rev8)

[Patchwork]

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== Series Details ==

Series: CMTG enablement (rev8)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

CI Bug Log - changes from xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33_BAT -> xe-pw-157663v8_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33 -> xe-pw-157663v8

  IGT_8937: 8937
  xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33: ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33
  xe-pw-157663v8: 157663v8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/index.html

[-- Attachment #2: Type: text/html, Size: 1393 bytes --]

✓ i915.CI.BAT: success for CMTG enablement (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4976 bytes --]

== Series Details ==

Series: CMTG enablement (rev7)
URL   : https://patchwork.freedesktop.org/series/157664/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18556 -> Patchwork_157664v7
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

New tests
---------

  New tests have been introduced between CI_DRM_18556 and Patchwork_157664v7:

### New IGT tests (36) ###

  * igt@kms_flip@basic-flip-vs-dpms@a-hdmi-a1:
    - Statuses : 7 pass(s)
    - Exec time: [0.68, 1.45] s

  * igt@kms_flip@basic-flip-vs-dpms@a-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [0.76, 0.94] s

  * igt@kms_flip@basic-flip-vs-dpms@a-vga1:
    - Statuses : 5 pass(s)
    - Exec time: [0.88, 1.66] s

  * igt@kms_flip@basic-flip-vs-dpms@b-hdmi-a1:
    - Statuses : 7 pass(s)
    - Exec time: [0.70, 1.38] s

  * igt@kms_flip@basic-flip-vs-dpms@b-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [0.69, 0.83] s

  * igt@kms_flip@basic-flip-vs-dpms@b-vga1:
    - Statuses : 5 pass(s)
    - Exec time: [0.76, 1.66] s

  * igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
    - Statuses : 6 pass(s)
    - Exec time: [0.70, 1.41] s

  * igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a2:
    - Statuses : 5 pass(s)
    - Exec time: [0.69, 2.78] s

  * igt@kms_flip@basic-flip-vs-dpms@c-vga1:
    - Statuses : 2 pass(s)
    - Exec time: [0.91] s

  * igt@kms_flip@basic-flip-vs-modeset@a-hdmi-a1:
    - Statuses : 7 pass(s)
    - Exec time: [0.77, 1.60] s

  * igt@kms_flip@basic-flip-vs-modeset@a-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [0.79, 0.97] s

  * igt@kms_flip@basic-flip-vs-modeset@a-vga1:
    - Statuses : 5 pass(s)
    - Exec time: [0.86, 1.59] s

  * igt@kms_flip@basic-flip-vs-modeset@b-hdmi-a1:
    - Statuses : 7 pass(s)
    - Exec time: [0.63, 1.42] s

  * igt@kms_flip@basic-flip-vs-modeset@b-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [0.70, 0.85] s

  * igt@kms_flip@basic-flip-vs-modeset@b-vga1:
    - Statuses : 5 pass(s)
    - Exec time: [0.64, 1.39] s

  * igt@kms_flip@basic-flip-vs-modeset@c-hdmi-a1:
    - Statuses : 6 pass(s)
    - Exec time: [0.62, 1.40] s

  * igt@kms_flip@basic-flip-vs-modeset@c-hdmi-a2:
    - Statuses : 5 pass(s)
    - Exec time: [0.72, 2.72] s

  * igt@kms_flip@basic-flip-vs-modeset@c-vga1:
    - Statuses : 2 pass(s)
    - Exec time: [0.94, 0.95] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a1:
    - Statuses : 7 pass(s)
    - Exec time: [0.84, 1.58] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [1.05, 1.16] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1:
    - Statuses : 5 pass(s)
    - Exec time: [1.07, 1.90] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-hdmi-a1:
    - Statuses : 7 pass(s)
    - Exec time: [0.81, 1.45] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [1.03, 1.23] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-vga1:
    - Statuses : 5 pass(s)
    - Exec time: [1.0, 1.80] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a1:
    - Statuses : 6 pass(s)
    - Exec time: [0.81, 1.45] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2:
    - Statuses : 5 pass(s)
    - Exec time: [1.03, 2.92] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-vga1:
    - Statuses : 2 pass(s)
    - Exec time: [1.15, 1.17] s

  * igt@kms_flip@basic-plain-flip@a-hdmi-a1:
    - Statuses : 7 pass(s)
    - Exec time: [0.71, 1.23] s

  * igt@kms_flip@basic-plain-flip@a-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [0.78, 0.88] s

  * igt@kms_flip@basic-plain-flip@a-vga1:
    - Statuses : 5 pass(s)
    - Exec time: [0.79, 1.60] s

  * igt@kms_flip@basic-plain-flip@b-hdmi-a1:
    - Statuses : 7 pass(s)
    - Exec time: [0.68, 1.16] s

  * igt@kms_flip@basic-plain-flip@b-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [0.73, 0.82] s

  * igt@kms_flip@basic-plain-flip@b-vga1:
    - Statuses : 5 pass(s)
    - Exec time: [0.73, 1.49] s

  * igt@kms_flip@basic-plain-flip@c-hdmi-a1:
    - Statuses : 6 pass(s)
    - Exec time: [0.68, 1.17] s

  * igt@kms_flip@basic-plain-flip@c-hdmi-a2:
    - Statuses : 5 pass(s)
    - Exec time: [0.75, 2.64] s

  * igt@kms_flip@basic-plain-flip@c-vga1:
    - Statuses : 2 pass(s)
    - Exec time: [0.88, 0.89] s

  


Changes
-------

  No changes found


Build changes
-------------

  * Linux: CI_DRM_18556 -> Patchwork_157664v7

  CI-20190529: 20190529
  CI_DRM_18556: 1e5fbf0d628cd02dced6cfb1ebe39717f121fb4c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8937: 8937
  Patchwork_157664v7: 1e5fbf0d628cd02dced6cfb1ebe39717f121fb4c @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/index.html

[-- Attachment #2: Type: text/html, Size: 6630 bytes --]

✓ Xe.CI.FULL: success for CMTG enablement (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 25162 bytes --]

== Series Details ==

Series: CMTG enablement (rev8)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

CI Bug Log - changes from xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33_FULL -> xe-pw-157663v8_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

New tests
---------

  New tests have been introduced between xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33_FULL and xe-pw-157663v8_FULL:

### New IGT tests (1) ###

  * igt@kms_flip@flip-vs-modeset-vs-hang@c-edp1:
    - Statuses : 1 pass(s)
    - Exec time: [2.34] s

  

Known issues
------------

  Here are the changes found in xe-pw-157663v8_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-bmg:          NOTRUN -> [DMESG-FAIL][1] ([Intel XE#5545] / [Intel XE#7774]) +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][2] ([Intel XE#3658] / [Intel XE#7360])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2327])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#1124]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html

  * igt@kms_bw@linear-tiling-1-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#367])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2887])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs.html

  * igt@kms_cdclk@mode-transition@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#4417] / [Intel XE#5447]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_cdclk@mode-transition@pipe-b-edp-1.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#306] / [Intel XE#7358])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#373])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_content_protection@srm:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#7642])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-rapid-movement-max-size:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#1424]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#2244])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][13] -> [FAIL][14] ([Intel XE#301]) +1 other test fail
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#7178] / [Intel XE#7351])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#7178] / [Intel XE#7351])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#7179])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#4141])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#6312]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2311])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-plflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#656] / [Intel XE#7905]) +8 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#6312] / [Intel XE#651])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7061] / [Intel XE#7356])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#7905]) +4 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#7061])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2313]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_frontbuffer_tracking@psrhdr-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#7865])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][28] -> [SKIP][29] ([Intel XE#1503])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-6/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [PASS][30] -> [SKIP][31] ([Intel XE#7922]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-bmg-1/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-6/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_hdr@static-swap:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#1503] / [Intel XE#7915])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-swap@pipe-a-edp-1-xrgb2101010:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#7915]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_hdr@static-swap@pipe-a-edp-1-xrgb2101010.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [PASS][34] -> [SKIP][35] ([Intel XE#7915]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-bmg-4/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-8/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#6900] / [Intel XE#7362])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#309] / [Intel XE#7343])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#2893] / [Intel XE#7304])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#1128] / [Intel XE#7413])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@kms_psr@fbc-pr-no-drrs.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][43] -> [FAIL][44] ([Intel XE#2142]) +1 other test fail
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-lnl-5/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-8/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#7319] / [Intel XE#7350] / [Intel XE#944])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_eudebug@basic-vm-access-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#7636])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@xe_eudebug@basic-vm-access-userptr.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#7636])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@xe_eudebug_online@single-step.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][48] -> [INCOMPLETE][49] ([Intel XE#6321])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-6/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_balancer@twice-cm-virtual-basic:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#7482]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@xe_exec_balancer@twice-cm-virtual-basic.html

  * igt@xe_exec_compute_mode@twice-basic:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#6557] / [Intel XE#6703]) +6 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@xe_exec_compute_mode@twice-basic.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#7136])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind-prefetch.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#7136]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#6874]) +3 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-userptr.html

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#6874]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@xe_exec_multi_queue@max-queues-preempt-mode-userptr-invalidate.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#6703]) +189 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#7138])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#7138])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-userptr-invalidate-race.html

  * igt@xe_multigpu_svm@mgpu-coherency-conflict:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#6964])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-2/igt@xe_multigpu_svm@mgpu-coherency-conflict.html

  * igt@xe_multigpu_svm@mgpu-migration-basic:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#6964])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@xe_multigpu_svm@mgpu-migration-basic.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#944])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_sriov_admin@sched-priority-vf-write-denied:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#7174])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-5/igt@xe_sriov_admin@sched-priority-vf-write-denied.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-lnl:          [PASS][63] -> [ABORT][64] ([Intel XE#8007])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-lnl-4/igt@xe_wedged@wedged-mode-toggle.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-4/igt@xe_wedged@wedged-mode-toggle.html

  
#### Possible fixes ####

  * igt@kms_cursor_crc@cursor-random-256x256@pipe-d-dp-2:
    - shard-bmg:          [FAIL][65] -> [PASS][66] +1 other test pass
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-bmg-2/igt@kms_cursor_crc@cursor-random-256x256@pipe-d-dp-2.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-1/igt@kms_cursor_crc@cursor-random-256x256@pipe-d-dp-2.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][67] ([Intel XE#301]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [SKIP][69] ([Intel XE#7915]) -> [PASS][70] +1 other test pass
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-bmg-8/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-5/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_vrr@flipline:
    - shard-lnl:          [FAIL][71] ([Intel XE#4227] / [Intel XE#7397]) -> [PASS][72] +1 other test pass
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-lnl-5/igt@kms_vrr@flipline.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-lnl-4/igt@kms_vrr@flipline.html

  
#### Warnings ####

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][73] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][74] ([Intel XE#2426] / [Intel XE#5848])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
  [Intel XE#5447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5447
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7319
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7350
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
  [Intel XE#7362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7362
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7774]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7774
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#7922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7922
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33 -> xe-pw-157663v8

  IGT_8937: 8937
  xe-5131-ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33: ba2b29e3db52fcd75c2dc6d76d81f26eb59b7e33
  xe-pw-157663v8: 157663v8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v8/index.html

[-- Attachment #2: Type: text/html, Size: 28245 bytes --]

✗ i915.CI.Full: failure for CMTG enablement (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 106394 bytes --]

== Series Details ==

Series: CMTG enablement (rev7)
URL   : https://patchwork.freedesktop.org/series/157664/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18556_full -> Patchwork_157664v7_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_157664v7_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_157664v7_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_157664v7_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_lmem_swapping@parallel-random@lmem0:
    - shard-dg2:          [PASS][1] -> [ABORT][2] +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-3/igt@gem_lmem_swapping@parallel-random@lmem0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-8/igt@gem_lmem_swapping@parallel-random@lmem0.html

  
Known issues
------------

  Here are the changes found in Patchwork_157664v7_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][3] ([i915#3555] / [i915#9323])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-rkl:          NOTRUN -> [SKIP][4] ([i915#7697])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_ctx_persistence@engines-mixed-process:
    - shard-snb:          NOTRUN -> [SKIP][5] ([i915#1099])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-snb4/igt@gem_ctx_persistence@engines-mixed-process.html

  * igt@gem_ctx_persistence@heartbeat-hostile:
    - shard-dg2:          NOTRUN -> [SKIP][6] ([i915#8555])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-5/igt@gem_ctx_persistence@heartbeat-hostile.html

  * igt@gem_eio@in-flight-suspend:
    - shard-rkl:          [PASS][7] -> [INCOMPLETE][8] ([i915#13390])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@gem_eio@in-flight-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@gem_eio@in-flight-suspend.html
    - shard-glk:          NOTRUN -> [INCOMPLETE][9] ([i915#13390])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk2/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#4525]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@gem_exec_balancer@parallel-balancer.html
    - shard-tglu-1:       NOTRUN -> [SKIP][11] ([i915#4525])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-glk:          NOTRUN -> [SKIP][12] ([i915#6334]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk5/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-rkl:          NOTRUN -> [SKIP][13] ([i915#6344])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-4/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_fence@concurrent:
    - shard-dg2:          NOTRUN -> [SKIP][14] ([i915#4812])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_exec_fence@concurrent.html

  * igt@gem_exec_flush@basic-uc-set-default:
    - shard-dg2:          NOTRUN -> [SKIP][15] ([i915#3539])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_exec_flush@basic-uc-set-default.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - shard-rkl:          NOTRUN -> [SKIP][16] ([i915#3281]) +5 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_exec_reloc@basic-write-wc-active:
    - shard-dg2:          NOTRUN -> [SKIP][17] ([i915#3281]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_exec_reloc@basic-write-wc-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain:
    - shard-dg2:          NOTRUN -> [SKIP][18] ([i915#4537] / [i915#4812])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_exec_schedule@preempt-queue-contexts-chain.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-dg2:          [PASS][19] -> [INCOMPLETE][20] ([i915#13356]) +1 other test incomplete
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-8/igt@gem_exec_suspend@basic-s0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-rkl:          [PASS][21] -> [INCOMPLETE][22] ([i915#13356]) +1 other test incomplete
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_exec_suspend@basic-s3.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_fence_thrash@bo-copy:
    - shard-dg2:          NOTRUN -> [SKIP][23] ([i915#4860])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_fence_thrash@bo-copy.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][24] ([i915#4613]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-rkl:          NOTRUN -> [SKIP][25] ([i915#4613]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@random:
    - shard-glk:          NOTRUN -> [SKIP][26] ([i915#4613]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk9/igt@gem_lmem_swapping@random.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#4077]) +5 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_mmap_gtt@fault-concurrent-y.html

  * igt@gem_mmap_wc@invalid-flags:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#4083]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_mmap_wc@invalid-flags.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-rkl:          NOTRUN -> [SKIP][29] ([i915#3282]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_pread@display:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#3282])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_pread@display.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-tglu-1:       NOTRUN -> [WARN][31] ([i915#2658])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-rkl:          NOTRUN -> [SKIP][32] ([i915#4270])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@fail-invalid-protected-context:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#4270])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_pxp@fail-invalid-protected-context.html

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - shard-rkl:          NOTRUN -> [SKIP][34] ([i915#13717])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@gem_pxp@hw-rejects-pxp-buffer.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#5190] / [i915#8428]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html

  * igt@gem_softpin@noreloc-s3:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][36] ([i915#13809] / [i915#16193])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk11/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][37] ([i915#3297]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-glk:          NOTRUN -> [SKIP][38] ([i915#3323])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk5/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#3297] / [i915#4880])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-glk:          NOTRUN -> [INCOMPLETE][40] ([i915#13356] / [i915#14586])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk5/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-dg2:          NOTRUN -> [SKIP][41] ([i915#2856])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-tglu-1:       NOTRUN -> [SKIP][42] ([i915#2527] / [i915#2856])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@gen9_exec_parse@bb-start-out.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglu:         NOTRUN -> [SKIP][43] ([i915#2527] / [i915#2856])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_freq_api@freq-basic-api:
    - shard-tglu:         NOTRUN -> [SKIP][44] ([i915#8399])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@i915_pm_freq_api@freq-basic-api.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-tglu-1:       NOTRUN -> [SKIP][45] ([i915#6590]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglu-1:       NOTRUN -> [SKIP][46] ([i915#4387])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@i915_pm_sseu@full-enable.html

  * igt@i915_power@sanity:
    - shard-rkl:          NOTRUN -> [SKIP][47] ([i915#7984])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@i915_power@sanity.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          NOTRUN -> [SKIP][48] ([i915#5723])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][49] ([i915#16182] / [i915#4817])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk11/igt@i915_suspend@fence-restore-tiled2untiled.html
    - shard-rkl:          [PASS][50] -> [INCOMPLETE][51] ([i915#4817])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-5/igt@i915_suspend@fence-restore-tiled2untiled.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-glk:          NOTRUN -> [INCOMPLETE][52] ([i915#16182] / [i915#4817])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk5/igt@i915_suspend@fence-restore-untiled.html

  * igt@i915_suspend@forcewake:
    - shard-rkl:          [PASS][53] -> [ABORT][54] ([i915#15140])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@i915_suspend@forcewake.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-1/igt@i915_suspend@forcewake.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-rkl:          NOTRUN -> [SKIP][55] ([i915#12454] / [i915#12712])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][56] ([i915#12761])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk10/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-2:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][57] ([i915#12761] / [i915#14995])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk10/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-2.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-tglu-1:       NOTRUN -> [SKIP][58] ([i915#9531])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-snb:          NOTRUN -> [SKIP][59] ([i915#1769])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1:
    - shard-mtlp:         [PASS][60] -> [FAIL][61] ([i915#5956]) +1 other test fail
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-7/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-mtlp-8/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][62] +4 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-5/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-tglu:         NOTRUN -> [SKIP][63] ([i915#5286])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][64] ([i915#5286]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-tglu-1:       NOTRUN -> [SKIP][65] ([i915#5286]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][66] ([i915#3638]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][67] ([i915#3828])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-dg2:          NOTRUN -> [SKIP][68] ([i915#4538] / [i915#5190])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][69] ([i915#14098] / [i915#6095]) +34 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][70] ([i915#6095]) +247 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-16/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([i915#12313])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][72] ([i915#12313])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][73] ([i915#6095]) +19 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][74] ([i915#12805])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][75] ([i915#6095]) +7 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-glk:          NOTRUN -> [INCOMPLETE][76] ([i915#15582] / [i915#16205]) +1 other test incomplete
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk9/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][77] ([i915#6095]) +19 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#6095]) +53 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][79] ([i915#10307] / [i915#6095]) +86 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-4/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-4/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][81] +479 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk5/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition@pipe-b-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#13781]) +3 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-b-dp-3.html

  * igt@kms_cdclk@plane-scaling:
    - shard-tglu:         NOTRUN -> [SKIP][83] ([i915#3742])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-rkl:          NOTRUN -> [SKIP][84] ([i915#11151] / [i915#7828]) +2 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_frames@dp-crc-multiple:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([i915#11151] / [i915#7828]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_chamelium_frames@dp-crc-multiple.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([i915#11151] / [i915#7828]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-tglu-1:       NOTRUN -> [SKIP][87] ([i915#11151] / [i915#7828]) +3 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_content_protection@atomic:
    - shard-tglu-1:       NOTRUN -> [SKIP][88] ([i915#15865]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][89] ([i915#15865]) +2 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-type-0-suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][90] ([i915#15330])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#15865])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-rkl:          NOTRUN -> [SKIP][92] ([i915#13049]) +2 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-tglu:         [PASS][93] -> [FAIL][94] ([i915#13566]) +1 other test fail
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-tglu-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-6/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][95] ([i915#3555]) +3 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
    - shard-tglu-1:       NOTRUN -> [SKIP][96] ([i915#3555]) +2 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-tglu-1:       NOTRUN -> [SKIP][97] ([i915#13049])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][98] ([i915#13566]) +1 other test fail
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#13046] / [i915#5354]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-5/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-rkl:          NOTRUN -> [SKIP][100] ([i915#4103])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-rkl:          NOTRUN -> [SKIP][101] ([i915#9723])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-4/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_aux_dev@basic:
    - shard-tglu-1:       NOTRUN -> [SKIP][102] ([i915#1257])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_dp_aux_dev@basic.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          NOTRUN -> [SKIP][103] ([i915#13707])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-basic:
    - shard-tglu-1:       NOTRUN -> [SKIP][104] ([i915#3555] / [i915#3840])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#3840])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-rkl:          NOTRUN -> [SKIP][106] ([i915#3555] / [i915#3840])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-4/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][107] ([i915#9878])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk4/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2:          NOTRUN -> [SKIP][108] ([i915#16081])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@psr1:
    - shard-tglu:         NOTRUN -> [SKIP][109] ([i915#658])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#9934]) +2 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][111] ([i915#3637] / [i915#9934])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][112] ([i915#3637] / [i915#9934]) +3 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-dg2:          NOTRUN -> [SKIP][113] ([i915#9934]) +3 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#15643])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][115] ([i915#15643] / [i915#5190])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][116] ([i915#15643]) +2 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][117] ([i915#15643]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][118] ([i915#15643]) +2 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_force_connector_basic@force-connector-state:
    - shard-mtlp:         [PASS][119] -> [SKIP][120] ([i915#15672])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-7/igt@kms_force_connector_basic@force-connector-state.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-mtlp-1/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([i915#15104] / [i915#15990])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-indfb-draw-blt:
    - shard-snb:          NOTRUN -> [SKIP][122] +88 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-snb4/igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-plflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][123] ([i915#15989]) +14 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#15989]) +5 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbchdr-tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][125] ([i915#5439])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_frontbuffer_tracking@fbchdr-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-glk10:        NOTRUN -> [SKIP][126] +118 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-tglu-1:       NOTRUN -> [SKIP][127] +53 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#1825]) +3 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][129] ([i915#15990] / [i915#8708]) +5 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][130] ([i915#15991] / [i915#5354]) +5 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-pri-indfb-multidraw:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#15102]) +9 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][132] +51 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-shrfb-draw-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][133] ([i915#15989]) +5 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-rkl:          [PASS][134] -> [SKIP][135] ([i915#15989]) +13 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][136] ([i915#15990]) +5 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][137] +23 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_frontbuffer_tracking@hdr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-gtt:
    - shard-glk:          [PASS][138] -> [SKIP][139] +28 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-glk8/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-gtt.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk9/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][140] ([i915#15989]) +10 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][141] ([i915#15102]) +17 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
    - shard-tglu-1:       NOTRUN -> [SKIP][142] ([i915#15102]) +22 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][143] ([i915#15102] / [i915#3023]) +11 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-spr-indfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][144] ([i915#15991]) +14 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][145] ([i915#15102]) +8 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-mmap-gtt:
    - shard-glk11:        NOTRUN -> [SKIP][146] +13 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk11/igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-2-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][147] ([i915#16012]) +3 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-2-xrgb2101010.html

  * igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-4-xrgb2101010:
    - shard-dg1:          NOTRUN -> [SKIP][148] ([i915#16011]) +7 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-19/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-4-xrgb2101010.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-4-xrgb2101010:
    - shard-dg1:          NOTRUN -> [SKIP][149] ([i915#16012]) +5 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-19/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-4-xrgb2101010.html

  * igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-1-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][150] ([i915#16011]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-1-xrgb2101010.html

  * igt@kms_hdr@static-swap:
    - shard-tglu-1:       NOTRUN -> [SKIP][151] ([i915#16011] / [i915#3555] / [i915#8228])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-swap@pipe-a-hdmi-a-1-xrgb2101010:
    - shard-tglu-1:       NOTRUN -> [SKIP][152] ([i915#16011]) +1 other test skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_hdr@static-swap@pipe-a-hdmi-a-1-xrgb2101010.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][153] ([i915#15460])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][154] ([i915#15459])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][155] ([i915#13688])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_joiner@basic-max-non-joiner.html
    - shard-tglu-1:       NOTRUN -> [SKIP][156] ([i915#13688])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][157] ([i915#15458])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-tglu:         NOTRUN -> [SKIP][158] ([i915#6301])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#14712])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
    - shard-tglu-1:       NOTRUN -> [SKIP][160] ([i915#15709]) +3 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-rkl:          NOTRUN -> [SKIP][161] ([i915#15709]) +4 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7:
    - shard-tglu:         NOTRUN -> [SKIP][162] ([i915#15608]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier:
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#15709])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_plane@pixel-format-yf-tiled-modifier.html

  * igt@kms_plane_alpha_blend@alpha-basic:
    - shard-glk:          NOTRUN -> [FAIL][164] ([i915#12178])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk9/igt@kms_plane_alpha_blend@alpha-basic.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][165] ([i915#7862]) +1 other test fail
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk9/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-hdmi-a-1.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][166] ([i915#10647] / [i915#12169])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk5/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][167] ([i915#10647]) +1 other test fail
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk5/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a:
    - shard-rkl:          NOTRUN -> [SKIP][168] ([i915#15329]) +3 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-tglu:         NOTRUN -> [SKIP][169] ([i915#12343] / [i915#9812])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-rkl:          NOTRUN -> [SKIP][170] ([i915#15948])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_pm_dc@dc3co-vpb-simulation.html
    - shard-tglu-1:       NOTRUN -> [SKIP][171] ([i915#15948])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][172] ([i915#15739])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-dg2:          NOTRUN -> [SKIP][173] ([i915#8430])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][174] ([i915#15073]) +1 other test skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg1:          [PASS][175] -> [SKIP][176] ([i915#15073]) +2 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-13/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-15/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-snb:          NOTRUN -> [SKIP][177] ([i915#11520])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-snb4/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([i915#11520]) +2 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-tglu:         NOTRUN -> [SKIP][179] ([i915#11520]) +1 other test skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][180] ([i915#11520]) +3 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][181] ([i915#11520]) +4 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][182] ([i915#11520]) +8 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk5/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
    - shard-glk10:        NOTRUN -> [SKIP][183] ([i915#11520]) +2 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk10/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-glk11:        NOTRUN -> [SKIP][184] ([i915#11520])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk11/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-tglu-1:       NOTRUN -> [SKIP][185] ([i915#9683])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          NOTRUN -> [SKIP][186] ([i915#9683])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr-cursor-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][187] ([i915#1072] / [i915#9732]) +8 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_psr@fbc-psr-cursor-mmap-gtt.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#1072] / [i915#9732]) +10 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_psr@psr2-cursor-blt:
    - shard-tglu:         NOTRUN -> [SKIP][189] ([i915#9732]) +4 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_psr@psr2-cursor-blt.html

  * igt@kms_psr@psr2-sprite-mmap-gtt:
    - shard-tglu-1:       NOTRUN -> [SKIP][190] ([i915#9732]) +8 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_psr@psr2-sprite-mmap-gtt.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglu-1:       NOTRUN -> [SKIP][191] ([i915#15949])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][192] ([i915#12755] / [i915#15867])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][193] ([i915#15500] / [i915#16184])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk10/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-tglu:         NOTRUN -> [SKIP][194] ([i915#5289])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([i915#5190]) +1 other test skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-glk10:        NOTRUN -> [ABORT][196] ([i915#13179]) +1 other test abort
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk10/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-dg2:          NOTRUN -> [SKIP][197] ([i915#3555]) +2 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-tglu:         NOTRUN -> [SKIP][198] ([i915#3555])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-2/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-tglu-1:       NOTRUN -> [SKIP][199] ([i915#8623])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-tglu-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][200] ([i915#15243] / [i915#3555])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@kms_vrr@flip-dpms.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-rkl:          NOTRUN -> [SKIP][201] ([i915#8516])
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_vgem@basic-write:
    - shard-rkl:          NOTRUN -> [SKIP][202] ([i915#3291] / [i915#3708])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-4/igt@prime_vgem@basic-write.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-rkl:          NOTRUN -> [SKIP][203] ([i915#9917])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-4/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-dg2:          NOTRUN -> [SKIP][204] ([i915#4818])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-7/igt@tools_test@sysfs_l3_parity.html

  
#### Possible fixes ####

  * igt@gem_eio@suspend:
    - shard-rkl:          [ABORT][205] ([i915#15131]) -> [PASS][206]
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@gem_eio@suspend.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-4/igt@gem_eio@suspend.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-rkl:          [INCOMPLETE][207] ([i915#13356]) -> [PASS][208]
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@i915_pm_rpm@system-suspend.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [TIMEOUT][209] ([i915#16162]) -> [PASS][210]
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-snb4/igt@i915_pm_rps@reset.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-snb4/igt@i915_pm_rps@reset.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3:
    - shard-dg2:          [FAIL][211] ([i915#5956]) -> [PASS][212] +1 other test pass
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-5/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          [INCOMPLETE][213] ([i915#15582]) -> [PASS][214] +1 other test pass
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_color@deep-color:
    - shard-dg2:          [SKIP][215] ([i915#12655] / [i915#3555]) -> [PASS][216]
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-3/igt@kms_color@deep-color.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-10/igt@kms_color@deep-color.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2:
    - shard-rkl:          [FAIL][217] ([i915#13566]) -> [PASS][218] +1 other test pass
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-4/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-rkl:          [INCOMPLETE][219] ([i915#10056]) -> [PASS][220]
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move:
    - shard-glk:          [SKIP][221] -> [PASS][222] +21 other tests pass
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-glk6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk8/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-cur-indfb-draw-blt:
    - shard-rkl:          [SKIP][223] ([i915#15989]) -> [PASS][224] +16 other tests pass
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-cur-indfb-draw-blt.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-shrfb-scaledprimary:
    - shard-dg2:          [SKIP][225] ([i915#15989]) -> [PASS][226] +7 other tests pass
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-4/igt@kms_frontbuffer_tracking@hdr-shrfb-scaledprimary.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-10/igt@kms_frontbuffer_tracking@hdr-shrfb-scaledprimary.html

  * igt@kms_hdr@static-swap:
    - shard-rkl:          [SKIP][227] ([i915#16011] / [i915#3555] / [i915#8228]) -> [PASS][228]
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-5/igt@kms_hdr@static-swap.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-1/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-dg2:          [SKIP][229] ([i915#16011] / [i915#3555] / [i915#8228]) -> [PASS][230] +1 other test pass
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-4/igt@kms_hdr@static-toggle-suspend.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-10/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg1:          [SKIP][231] ([i915#15073]) -> [PASS][232] +1 other test pass
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-14/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-17/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@i2c:
    - shard-dg1:          [DMESG-WARN][233] ([i915#4423]) -> [PASS][234] +1 other test pass
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-19/igt@kms_pm_rpm@i2c.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-14/igt@kms_pm_rpm@i2c.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-rkl:          [SKIP][235] ([i915#15073]) -> [PASS][236] +2 other tests pass
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-dg2:          [ABORT][237] ([i915#15132]) -> [PASS][238]
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-10/igt@kms_vblank@ts-continuation-suspend.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-5/igt@kms_vblank@ts-continuation-suspend.html

  
#### Warnings ####

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-rkl:          [SKIP][239] ([i915#8411]) -> [SKIP][240] ([i915#14544] / [i915#8411])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@api_intel_bb@object-reloc-purge-cache.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-rkl:          [SKIP][241] ([i915#14544] / [i915#3555] / [i915#9323]) -> [SKIP][242] ([i915#3555] / [i915#9323])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_ccs@block-copy-compressed.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          [SKIP][243] ([i915#14544] / [i915#7697]) -> [SKIP][244] ([i915#7697])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_exec_balancer@parallel-bb-first:
    - shard-rkl:          [SKIP][245] ([i915#4525]) -> [SKIP][246] ([i915#14544] / [i915#4525])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@gem_exec_balancer@parallel-bb-first.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@gem_exec_balancer@parallel-bb-first.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-rkl:          [SKIP][247] ([i915#14544] / [i915#4525]) -> [SKIP][248] ([i915#4525]) +1 other test skip
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_exec_balancer@parallel-out-fence.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_reloc@basic-cpu-noreloc:
    - shard-rkl:          [SKIP][249] ([i915#14544] / [i915#3281]) -> [SKIP][250] ([i915#3281]) +6 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-noreloc.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-5/igt@gem_exec_reloc@basic-cpu-noreloc.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - shard-rkl:          [SKIP][251] ([i915#3281]) -> [SKIP][252] ([i915#14544] / [i915#3281]) +4 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@gem_exec_reloc@basic-write-read-noreloc.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-rkl:          [SKIP][253] ([i915#4613]) -> [SKIP][254] ([i915#14544] / [i915#4613])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@gem_lmem_swapping@parallel-multi.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_lmem_swapping@verify:
    - shard-rkl:          [SKIP][255] ([i915#14544] / [i915#4613]) -> [SKIP][256] ([i915#4613])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_lmem_swapping@verify.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@gem_lmem_swapping@verify.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-rkl:          [SKIP][257] ([i915#3282]) -> [SKIP][258] ([i915#14544] / [i915#3282])
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_pread@snoop:
    - shard-rkl:          [SKIP][259] ([i915#14544] / [i915#3282]) -> [SKIP][260] ([i915#3282]) +3 other tests skip
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_pread@snoop.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@gem_pread@snoop.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-rkl:          [SKIP][261] ([i915#14544] / [i915#8411]) -> [SKIP][262] ([i915#8411])
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-rkl:          [SKIP][263] ([i915#14544] / [i915#3297]) -> [SKIP][264] ([i915#3297]) +2 other tests skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_userptr_blits@create-destroy-unsync.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_workarounds@suspend-resume:
    - shard-rkl:          [ABORT][265] ([i915#15152]) -> [INCOMPLETE][266] ([i915#13356])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@gem_workarounds@suspend-resume.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@gem_workarounds@suspend-resume.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-rkl:          [SKIP][267] ([i915#2527]) -> [SKIP][268] ([i915#14544] / [i915#2527])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@gen9_exec_parse@batch-invalid-length.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@i915_pm_freq_api@freq-basic-api:
    - shard-rkl:          [SKIP][269] ([i915#8399]) -> [SKIP][270] ([i915#14544] / [i915#8399])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@i915_pm_freq_api@freq-basic-api.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@i915_pm_freq_api@freq-basic-api.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          [SKIP][271] ([i915#14544] / [i915#8399]) -> [SKIP][272] ([i915#8399])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@i915_pm_freq_api@freq-suspend.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@i915_pm_freq_api@freq-suspend.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-rkl:          [SKIP][273] ([i915#14544] / [i915#9531]) -> [SKIP][274] ([i915#9531])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-rkl:          [SKIP][275] ([i915#1769] / [i915#3555]) -> [SKIP][276] ([i915#14544] / [i915#1769] / [i915#3555])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-270:
    - shard-rkl:          [SKIP][277] ([i915#5286]) -> [SKIP][278] ([i915#14544] / [i915#5286]) +2 other tests skip
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-rkl:          [SKIP][279] ([i915#14544] / [i915#5286]) -> [SKIP][280] ([i915#5286]) +2 other tests skip
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-rkl:          [SKIP][281] ([i915#14544] / [i915#3638]) -> [SKIP][282] ([i915#3638])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs:
    - shard-rkl:          [SKIP][283] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][284] ([i915#14098] / [i915#6095]) +7 other tests skip
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][285] ([i915#14544] / [i915#6095]) -> [SKIP][286] ([i915#6095]) +3 other tests skip
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][287] ([i915#12313] / [i915#14544]) -> [SKIP][288] ([i915#12313])
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][289] ([i915#6095]) -> [SKIP][290] ([i915#14544] / [i915#6095]) +12 other tests skip
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][291] ([i915#14098] / [i915#6095]) -> [SKIP][292] ([i915#14098] / [i915#14544] / [i915#6095]) +13 other tests skip
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_cdclk@plane-scaling:
    - shard-rkl:          [SKIP][293] ([i915#3742]) -> [SKIP][294] ([i915#14544] / [i915#3742])
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_cdclk@plane-scaling.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-rkl:          [SKIP][295] ([i915#11151] / [i915#7828]) -> [SKIP][296] ([i915#11151] / [i915#14544] / [i915#7828]) +3 other tests skip
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_chamelium_hpd@dp-hpd-storm.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-rkl:          [SKIP][297] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][298] ([i915#11151] / [i915#7828]) +5 other tests skip
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_content_protection@dp-mst-type-0-suspend-resume:
    - shard-rkl:          [SKIP][299] ([i915#15330]) -> [SKIP][300] ([i915#14544] / [i915#15330])
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html

  * igt@kms_content_protection@type1:
    - shard-rkl:          [SKIP][301] ([i915#14544] / [i915#15865]) -> [SKIP][302] ([i915#15865])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_content_protection@type1.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-dg1:          [SKIP][303] ([i915#3555] / [i915#4423]) -> [SKIP][304] ([i915#3555])
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-18/igt@kms_cursor_crc@cursor-sliding-32x10.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-17/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-dg2:          [SKIP][305] ([i915#13049]) -> [SKIP][306] ([i915#13049] / [i915#3359])
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-3/igt@kms_cursor_crc@cursor-sliding-512x170.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-10/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-rkl:          [SKIP][307] ([i915#4103]) -> [SKIP][308] ([i915#14544] / [i915#4103])
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-rkl:          [SKIP][309] -> [SKIP][310] ([i915#14544]) +34 other tests skip
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_dsc@dsc-basic:
    - shard-rkl:          [SKIP][311] ([i915#14544] / [i915#3555] / [i915#3840]) -> [SKIP][312] ([i915#3555] / [i915#3840])
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_dsc@dsc-basic.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_dsc@dsc-basic.html

  * igt@kms_feature_discovery@display-4x:
    - shard-rkl:          [SKIP][313] ([i915#14544] / [i915#16081]) -> [SKIP][314] ([i915#16081])
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_feature_discovery@display-4x.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@psr1:
    - shard-rkl:          [SKIP][315] ([i915#658]) -> [SKIP][316] ([i915#14544] / [i915#658])
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_feature_discovery@psr1.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-rkl:          [SKIP][317] ([i915#9934]) -> [SKIP][318] ([i915#14544] / [i915#9934]) +1 other test skip
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_flip@2x-flip-vs-fences-interruptible.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-rkl:          [SKIP][319] ([i915#14544] / [i915#9934]) -> [SKIP][320] ([i915#9934]) +2 other tests skip
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-rkl:          [SKIP][321] ([i915#14544] / [i915#15643]) -> [SKIP][322] ([i915#15643])
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg1:          [SKIP][323] ([i915#15643] / [i915#4423]) -> [SKIP][324] ([i915#15643])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-rkl:          [SKIP][325] ([i915#15643]) -> [SKIP][326] ([i915#14544] / [i915#15643]) +1 other test skip
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-mtlp:         [SKIP][327] -> [SKIP][328] ([i915#15672])
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-7/igt@kms_force_connector_basic@force-load-detect.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-mtlp-1/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][329] ([i915#14544] / [i915#1825]) -> [SKIP][330] ([i915#1825]) +4 other tests skip
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-onoff:
    - shard-rkl:          [SKIP][331] ([i915#14544]) -> [SKIP][332] +41 other tests skip
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-onoff.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbchdr-suspend:
    - shard-dg2:          [SKIP][333] ([i915#15989]) -> [ABORT][334] ([i915#15132])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-4/igt@kms_frontbuffer_tracking@fbchdr-suspend.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-10/igt@kms_frontbuffer_tracking@fbchdr-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt:
    - shard-rkl:          [SKIP][335] ([i915#15102]) -> [SKIP][336] ([i915#14544] / [i915#15102]) +12 other tests skip
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt:
    - shard-dg1:          [SKIP][337] ([i915#15990] / [i915#4423] / [i915#8708]) -> [SKIP][338] ([i915#15990] / [i915#8708]) +1 other test skip
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][339] ([i915#1825]) -> [SKIP][340] ([i915#14544] / [i915#1825])
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite:
    - shard-dg1:          [SKIP][341] ([i915#15102]) -> [SKIP][342] ([i915#15102] / [i915#4423])
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-19/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-dg2:          [SKIP][343] ([i915#15102]) -> [SKIP][344] ([i915#10433] / [i915#15102])
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-rkl:          [SKIP][345] ([i915#15102] / [i915#3023]) -> [SKIP][346] ([i915#14544] / [i915#15102] / [i915#3023]) +7 other tests skip
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-dg2:          [SKIP][347] ([i915#10433] / [i915#15102]) -> [SKIP][348] ([i915#15102]) +1 other test skip
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
    - shard-rkl:          [SKIP][349] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][350] ([i915#15102] / [i915#3023]) +7 other tests skip
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][351] ([i915#14544] / [i915#15102]) -> [SKIP][352] ([i915#15102]) +13 other tests skip
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-onoff:
    - shard-dg1:          [SKIP][353] -> [SKIP][354] ([i915#4423]) +2 other tests skip
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-14/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-onoff.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-16/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_hdr@invalid-hdr:
    - shard-rkl:          [SKIP][355] ([i915#14544] / [i915#3555] / [i915#8228]) -> [SKIP][356] ([i915#16012] / [i915#3555] / [i915#8228])
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_hdr@invalid-hdr.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-rkl:          [SKIP][357] ([i915#15460]) -> [SKIP][358] ([i915#14544] / [i915#15460])
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_joiner@basic-big-joiner.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-dg1:          [SKIP][359] ([i915#4423] / [i915#6301]) -> [SKIP][360] ([i915#6301])
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-13/igt@kms_panel_fitting@atomic-fastset.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-17/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          [SKIP][361] ([i915#6301]) -> [SKIP][362] ([i915#14544] / [i915#6301])
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_panel_fitting@legacy.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-4tiled:
    - shard-rkl:          [SKIP][363] ([i915#14712]) -> [SKIP][364] ([i915#14544] / [i915#14712])
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html
    - shard-dg1:          [SKIP][365] ([i915#14712]) -> [SKIP][366] ([i915#14712] / [i915#4423])
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-13/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-17/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-rkl:          [SKIP][367] ([i915#14544] / [i915#15709]) -> [SKIP][368] ([i915#15709]) +1 other test skip
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
    - shard-dg1:          [SKIP][369] ([i915#15709]) -> [SKIP][370] ([i915#15709] / [i915#4423])
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-15/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-19/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-dg1:          [SKIP][371] ([i915#13958] / [i915#4423]) -> [SKIP][372] ([i915#13958])
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-12/igt@kms_plane_multiple@2x-tiling-x.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg1-16/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-rkl:          [SKIP][373] ([i915#13958]) -> [SKIP][374] ([i915#13958] / [i915#14544])
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@kms_plane_multiple@2x-tiling-yf.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-rkl:          [SKIP][375] ([i915#12343] / [i915#5354]) -> [SKIP][376] ([i915#12343] / [i915#14544] / [i915#5354])
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_pm_backlight@bad-brightness.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          [SKIP][377] ([i915#14544] / [i915#3828]) -> [SKIP][378] ([i915#3828])
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_pm_dc@dc5-retention-flops.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          [SKIP][379] ([i915#6524]) -> [SKIP][380] ([i915#14544] / [i915#6524])
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@kms_prime@basic-modeset-hybrid.html
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-rkl:          [SKIP][381] ([i915#14544] / [i915#6524]) -> [SKIP][382] ([i915#6524])
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_prime@d3hot.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
    - shard-rkl:          [SKIP][383] ([i915#11520] / [i915#14544]) -> [SKIP][384] ([i915#11520]) +2 other tests skip
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-rkl:          [SKIP][385] ([i915#11520]) -> [SKIP][386] ([i915#11520] / [i915#14544]) +3 other tests skip
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-rkl:          [SKIP][387] ([i915#14544] / [i915#9683]) -> [SKIP][388] ([i915#9683])
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_psr2_su@page_flip-nv12.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@pr-cursor-plane-onoff:
    - shard-rkl:          [SKIP][389] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][390] ([i915#1072] / [i915#9732]) +10 other tests skip
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_psr@pr-cursor-plane-onoff.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_psr@pr-cursor-plane-onoff.html

  * igt@kms_psr@psr2-cursor-blt:
    - shard-rkl:          [SKIP][391] ([i915#1072] / [i915#9732]) -> [SKIP][392] ([i915#1072] / [i915#14544] / [i915#9732]) +7 other tests skip
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-7/igt@kms_psr@psr2-cursor-blt.html
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_psr@psr2-cursor-blt.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg2:          [SKIP][393] ([i915#12755] / [i915#15867] / [i915#5190]) -> [SKIP][394] ([i915#15867] / [i915#5190])
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-dg2-10/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-rkl:          [SKIP][395] ([i915#3555]) -> [SKIP][396] ([i915#14544] / [i915#3555]) +1 other test skip
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@kms_scaling_modes@scaling-mode-none.html
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-rkl:          [SKIP][397] ([i915#14544] / [i915#3555]) -> [SKIP][398] ([i915#3555]) +1 other test skip
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_setmode@clone-exclusive-crtc.html
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-2/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_vrr@flip-basic:
    - shard-rkl:          [SKIP][399] ([i915#15243] / [i915#3555]) -> [SKIP][400] ([i915#14544] / [i915#15243] / [i915#3555])
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@kms_vrr@flip-basic.html
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@kms_vrr@flip-basic.html

  * igt@perf@mi-rpc:
    - shard-rkl:          [SKIP][401] ([i915#14544] / [i915#2434]) -> [SKIP][402] ([i915#2434])
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@perf@mi-rpc.html
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-3/igt@perf@mi-rpc.html

  * igt@perf_pmu@rc6-suspend:
    - shard-glk:          [INCOMPLETE][403] ([i915#13356] / [i915#14242] / [i915#16236]) -> [INCOMPLETE][404] ([i915#13356] / [i915#16236])
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-glk4/igt@perf_pmu@rc6-suspend.html
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-glk3/igt@perf_pmu@rc6-suspend.html

  * igt@prime_vgem@coherency-gtt:
    - shard-rkl:          [SKIP][405] ([i915#3708]) -> [SKIP][406] ([i915#14544] / [i915#3708])
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@prime_vgem@coherency-gtt.html
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@prime_vgem@coherency-gtt.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each:
    - shard-rkl:          [SKIP][407] ([i915#9917]) -> [SKIP][408] ([i915#14544] / [i915#9917])
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@sriov_basic@enable-vfs-bind-unbind-each.html
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/shard-rkl-6/igt@sriov_basic@enable-vfs-bind-unbind-each.html

  
  [i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12178]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12178
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
  [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13809
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14242]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14242
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14586]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14586
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#14995]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14995
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#15140]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15140
  [i915#15152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15152
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
  [i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
  [i915#15500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15500
  [i915#15582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15582
  [i915#15608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15608
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15672
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#15739]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15739
  [i915#15865]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15865
  [i915#15867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15867
  [i915#15948]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15948
  [i915#15949]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15949
  [i915#15989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15989
  [i915#15990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15990
  [i915#15991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15991
  [i915#16011]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16011
  [i915#16012]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16012
  [i915#16081]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16081
  [i915#16162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16162
  [i915#16182]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16182
  [i915#16184]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16184
  [i915#16193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16193
  [i915#16205]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16205
  [i915#16236]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16236
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4818
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7862]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7862
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9878]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9878
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_18556 -> Patchwork_157664v7

  CI-20190529: 20190529
  CI_DRM_18556: 1e5fbf0d628cd02dced6cfb1ebe39717f121fb4c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8937: 8937
  Patchwork_157664v7: 1e5fbf0d628cd02dced6cfb1ebe39717f121fb4c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v7/index.html

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