* [PATCH 01/24] target/riscv: Remove unused tcg/tcg.h include
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-27 11:03 ` Chao Liu
2026-06-22 19:31 ` [PATCH 02/24] target/riscv: move TCG only files to tcg subdir Daniel Henrique Barboza
` (23 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier, Zephyr Li,
Daniel Henrique Barboza, Palmer Dabbelt
From: Zephyr Li <fritchleybohrer@gmail.com>
Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bff3ed5de1..4e96bbeb60 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -38,7 +38,6 @@
#include "system/tcg.h"
#include "kvm/kvm_riscv.h"
#include "tcg/tcg-cpu.h"
-#include "tcg/tcg.h"
#if !defined(CONFIG_USER_ONLY)
#include "target/riscv/debug.h"
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 01/24] target/riscv: Remove unused tcg/tcg.h include
2026-06-22 19:31 ` [PATCH 01/24] target/riscv: Remove unused tcg/tcg.h include Daniel Henrique Barboza
@ 2026-06-27 11:03 ` Chao Liu
0 siblings, 0 replies; 71+ messages in thread
From: Chao Liu @ 2026-06-27 11:03 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
philmd, pierrick.bouvier, Zephyr Li, Palmer Dabbelt
On Mon, Jun 22, 2026 at 04:31:17PM +0800, Daniel Henrique Barboza wrote:
> From: Zephyr Li <fritchleybohrer@gmail.com>
>
> Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> ---
> target/riscv/cpu.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index bff3ed5de1..4e96bbeb60 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -38,7 +38,6 @@
> #include "system/tcg.h"
> #include "kvm/kvm_riscv.h"
> #include "tcg/tcg-cpu.h"
> -#include "tcg/tcg.h"
> #if !defined(CONFIG_USER_ONLY)
> #include "target/riscv/debug.h"
> #endif
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 02/24] target/riscv: move TCG only files to tcg subdir
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 01/24] target/riscv: Remove unused tcg/tcg.h include Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 20:52 ` Philippe Mathieu-Daudé
2026-06-27 11:04 ` Chao Liu
2026-06-22 19:31 ` [PATCH 03/24] target/riscv/machine.c: do not migrate pmp state with kvm Daniel Henrique Barboza
` (22 subsequent siblings)
24 siblings, 2 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
We have *way* too much TCG-only code hanging around in target/riscv,
where ideally we would have things that are shared between accelerators.
We'll follow the example of other targets like i386 and loongarch and
move everything to the tcg subir. This will not only cleanup target/riscv
but it will also expose what is common code but it's buried inside a TCG
helper.
We're leaving some stuff behind because these require a little more
case to not end up breaking KVM. We'll take care of them next.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/meson.build | 16 ----------
target/riscv/{ => tcg}/bitmanip_helper.c | 0
target/riscv/{ => tcg}/cpu_helper.c | 0
target/riscv/{ => tcg}/crypto_helper.c | 0
target/riscv/{ => tcg}/csr.c | 0
target/riscv/{ => tcg}/debug.c | 0
target/riscv/{ => tcg}/fpu_helper.c | 0
.../insn_trans/trans_privileged.c.inc | 0
.../{ => tcg}/insn_trans/trans_rva.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvb.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvbf16.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvd.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvf.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvh.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvi.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvk.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvm.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvv.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvvk.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzabha.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzacas.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzalasr.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzawrs.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzce.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzcmop.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzfa.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzfh.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzicbo.c.inc | 0
.../insn_trans/trans_rvzicfiss.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzicond.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzimop.c.inc | 0
.../{ => tcg}/insn_trans/trans_svinval.c.inc | 0
.../{ => tcg}/insn_trans/trans_xlrbr.c.inc | 0
.../{ => tcg}/insn_trans/trans_xmips.c.inc | 0
.../{ => tcg}/insn_trans/trans_xthead.c.inc | 0
.../insn_trans/trans_xventanacondops.c.inc | 0
.../{ => tcg}/insn_trans/trans_zilsd.c.inc | 0
target/riscv/{ => tcg}/m128_helper.c | 0
target/riscv/tcg/meson.build | 30 +++++++++++++++++--
target/riscv/{ => tcg}/mips_csr.c | 0
target/riscv/{ => tcg}/op_helper.c | 0
target/riscv/{ => tcg}/pmu.c | 0
target/riscv/{ => tcg}/th_csr.c | 0
target/riscv/{ => tcg}/translate.c | 0
target/riscv/{ => tcg}/vcrypto_helper.c | 0
target/riscv/{ => tcg}/vector_helper.c | 0
target/riscv/{ => tcg}/vector_internals.c | 0
target/riscv/{ => tcg}/vector_internals.h | 0
target/riscv/{ => tcg}/zce_helper.c | 0
49 files changed, 28 insertions(+), 18 deletions(-)
rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
rename target/riscv/{ => tcg}/cpu_helper.c (100%)
rename target/riscv/{ => tcg}/crypto_helper.c (100%)
rename target/riscv/{ => tcg}/csr.c (100%)
rename target/riscv/{ => tcg}/debug.c (100%)
rename target/riscv/{ => tcg}/fpu_helper.c (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rva.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvb.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvbf16.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvd.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvf.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvh.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvi.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvk.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvm.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvv.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvvk.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzabha.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzacas.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzalasr.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzawrs.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzce.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzcmop.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzfa.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzfh.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzicbo.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzicfiss.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzicond.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzimop.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_svinval.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xlrbr.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xmips.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xthead.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xventanacondops.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_zilsd.c.inc (100%)
rename target/riscv/{ => tcg}/m128_helper.c (100%)
rename target/riscv/{ => tcg}/mips_csr.c (100%)
rename target/riscv/{ => tcg}/op_helper.c (100%)
rename target/riscv/{ => tcg}/pmu.c (100%)
rename target/riscv/{ => tcg}/th_csr.c (100%)
rename target/riscv/{ => tcg}/translate.c (100%)
rename target/riscv/{ => tcg}/vcrypto_helper.c (100%)
rename target/riscv/{ => tcg}/vector_helper.c (100%)
rename target/riscv/{ => tcg}/vector_internals.c (100%)
rename target/riscv/{ => tcg}/vector_internals.h (100%)
rename target/riscv/{ => tcg}/zce_helper.c (100%)
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 79f36abd63..61874ed0af 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -16,31 +16,15 @@ riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',
riscv_ss.add(files(
'cpu.c',
- 'cpu_helper.c',
- 'csr.c',
- 'fpu_helper.c',
'gdbstub.c',
- 'op_helper.c',
- 'vector_helper.c',
- 'vector_internals.c',
- 'bitmanip_helper.c',
- 'translate.c',
- 'm128_helper.c',
- 'crypto_helper.c',
- 'zce_helper.c',
- 'vcrypto_helper.c'
))
riscv_system_ss = ss.source_set()
riscv_system_ss.add(files(
'arch_dump.c',
'pmp.c',
- 'debug.c',
'monitor.c',
'machine.c',
- 'mips_csr.c',
- 'pmu.c',
- 'th_csr.c',
'time_helper.c',
'riscv-qmp-cmds.c',
))
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/tcg/bitmanip_helper.c
similarity index 100%
rename from target/riscv/bitmanip_helper.c
rename to target/riscv/tcg/bitmanip_helper.c
diff --git a/target/riscv/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
similarity index 100%
rename from target/riscv/cpu_helper.c
rename to target/riscv/tcg/cpu_helper.c
diff --git a/target/riscv/crypto_helper.c b/target/riscv/tcg/crypto_helper.c
similarity index 100%
rename from target/riscv/crypto_helper.c
rename to target/riscv/tcg/crypto_helper.c
diff --git a/target/riscv/csr.c b/target/riscv/tcg/csr.c
similarity index 100%
rename from target/riscv/csr.c
rename to target/riscv/tcg/csr.c
diff --git a/target/riscv/debug.c b/target/riscv/tcg/debug.c
similarity index 100%
rename from target/riscv/debug.c
rename to target/riscv/tcg/debug.c
diff --git a/target/riscv/fpu_helper.c b/target/riscv/tcg/fpu_helper.c
similarity index 100%
rename from target/riscv/fpu_helper.c
rename to target/riscv/tcg/fpu_helper.c
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/tcg/insn_trans/trans_privileged.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_privileged.c.inc
rename to target/riscv/tcg/insn_trans/trans_privileged.c.inc
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/tcg/insn_trans/trans_rva.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rva.c.inc
rename to target/riscv/tcg/insn_trans/trans_rva.c.inc
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/tcg/insn_trans/trans_rvb.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvb.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvb.c.inc
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/tcg/insn_trans/trans_rvbf16.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvbf16.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvbf16.c.inc
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/tcg/insn_trans/trans_rvd.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvd.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvd.c.inc
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/tcg/insn_trans/trans_rvf.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvf.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvf.c.inc
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/tcg/insn_trans/trans_rvh.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvh.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvh.c.inc
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/tcg/insn_trans/trans_rvi.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvi.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvi.c.inc
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/tcg/insn_trans/trans_rvk.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvk.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvk.c.inc
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/tcg/insn_trans/trans_rvm.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvm.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvm.c.inc
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvv.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvv.c.inc
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/tcg/insn_trans/trans_rvvk.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvvk.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvvk.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/tcg/insn_trans/trans_rvzabha.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzabha.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzabha.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/tcg/insn_trans/trans_rvzacas.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzacas.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzacas.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzalasr.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzawrs.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/tcg/insn_trans/trans_rvzce.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzce.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzce.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzcmop.c.inc b/target/riscv/tcg/insn_trans/trans_rvzcmop.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzcmop.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzcmop.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/tcg/insn_trans/trans_rvzfa.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzfa.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzfa.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzfh.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzfh.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/tcg/insn_trans/trans_rvzicbo.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzicbo.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzicbo.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzicfiss.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzicond.c.inc b/target/riscv/tcg/insn_trans/trans_rvzicond.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzicond.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzicond.c.inc
diff --git a/target/riscv/insn_trans/trans_rvzimop.c.inc b/target/riscv/tcg/insn_trans/trans_rvzimop.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvzimop.c.inc
rename to target/riscv/tcg/insn_trans/trans_rvzimop.c.inc
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_svinval.c.inc
rename to target/riscv/tcg/insn_trans/trans_svinval.c.inc
diff --git a/target/riscv/insn_trans/trans_xlrbr.c.inc b/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_xlrbr.c.inc
rename to target/riscv/tcg/insn_trans/trans_xlrbr.c.inc
diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/tcg/insn_trans/trans_xmips.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_xmips.c.inc
rename to target/riscv/tcg/insn_trans/trans_xmips.c.inc
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_xthead.c.inc
rename to target/riscv/tcg/insn_trans/trans_xthead.c.inc
diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/tcg/insn_trans/trans_xventanacondops.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_xventanacondops.c.inc
rename to target/riscv/tcg/insn_trans/trans_xventanacondops.c.inc
diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/tcg/insn_trans/trans_zilsd.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_zilsd.c.inc
rename to target/riscv/tcg/insn_trans/trans_zilsd.c.inc
diff --git a/target/riscv/m128_helper.c b/target/riscv/tcg/m128_helper.c
similarity index 100%
rename from target/riscv/m128_helper.c
rename to target/riscv/tcg/m128_helper.c
diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
index 061df3d74a..5684fcf985 100644
--- a/target/riscv/tcg/meson.build
+++ b/target/riscv/tcg/meson.build
@@ -1,2 +1,28 @@
-riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
- 'tcg-cpu.c'))
+if 'CONFIG_TCG' not in config_all_accel
+ subdir_done()
+endif
+
+riscv_ss.add(files(
+ 'bitmanip_helper.c',
+ 'cpu_helper.c',
+ 'csr.c',
+ 'crypto_helper.c',
+ 'fpu_helper.c',
+ 'm128_helper.c',
+ 'op_helper.c',
+ 'translate.c',
+ 'tcg-cpu.c',
+ 'vcrypto_helper.c',
+ 'vector_helper.c',
+ 'vector_internals.c',
+ 'zce_helper.c'))
+
+
+riscv_system_ss.add(files(
+ 'debug.c',
+ 'mips_csr.c',
+ 'pmu.c',
+ 'th_csr.c',
+))
+
+
diff --git a/target/riscv/mips_csr.c b/target/riscv/tcg/mips_csr.c
similarity index 100%
rename from target/riscv/mips_csr.c
rename to target/riscv/tcg/mips_csr.c
diff --git a/target/riscv/op_helper.c b/target/riscv/tcg/op_helper.c
similarity index 100%
rename from target/riscv/op_helper.c
rename to target/riscv/tcg/op_helper.c
diff --git a/target/riscv/pmu.c b/target/riscv/tcg/pmu.c
similarity index 100%
rename from target/riscv/pmu.c
rename to target/riscv/tcg/pmu.c
diff --git a/target/riscv/th_csr.c b/target/riscv/tcg/th_csr.c
similarity index 100%
rename from target/riscv/th_csr.c
rename to target/riscv/tcg/th_csr.c
diff --git a/target/riscv/translate.c b/target/riscv/tcg/translate.c
similarity index 100%
rename from target/riscv/translate.c
rename to target/riscv/tcg/translate.c
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/tcg/vcrypto_helper.c
similarity index 100%
rename from target/riscv/vcrypto_helper.c
rename to target/riscv/tcg/vcrypto_helper.c
diff --git a/target/riscv/vector_helper.c b/target/riscv/tcg/vector_helper.c
similarity index 100%
rename from target/riscv/vector_helper.c
rename to target/riscv/tcg/vector_helper.c
diff --git a/target/riscv/vector_internals.c b/target/riscv/tcg/vector_internals.c
similarity index 100%
rename from target/riscv/vector_internals.c
rename to target/riscv/tcg/vector_internals.c
diff --git a/target/riscv/vector_internals.h b/target/riscv/tcg/vector_internals.h
similarity index 100%
rename from target/riscv/vector_internals.h
rename to target/riscv/tcg/vector_internals.h
diff --git a/target/riscv/zce_helper.c b/target/riscv/tcg/zce_helper.c
similarity index 100%
rename from target/riscv/zce_helper.c
rename to target/riscv/tcg/zce_helper.c
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 02/24] target/riscv: move TCG only files to tcg subdir
2026-06-22 19:31 ` [PATCH 02/24] target/riscv: move TCG only files to tcg subdir Daniel Henrique Barboza
@ 2026-06-22 20:52 ` Philippe Mathieu-Daudé
2026-06-27 11:04 ` Chao Liu
1 sibling, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 20:52 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> We have *way* too much TCG-only code hanging around in target/riscv,
> where ideally we would have things that are shared between accelerators.
>
> We'll follow the example of other targets like i386 and loongarch and
> move everything to the tcg subir. This will not only cleanup target/riscv
> but it will also expose what is common code but it's buried inside a TCG
> helper.
>
> We're leaving some stuff behind because these require a little more
> case to not end up breaking KVM. We'll take care of them next.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/meson.build | 16 ----------
> target/riscv/{ => tcg}/bitmanip_helper.c | 0
> target/riscv/{ => tcg}/cpu_helper.c | 0
> target/riscv/{ => tcg}/crypto_helper.c | 0
> target/riscv/{ => tcg}/csr.c | 0
> target/riscv/{ => tcg}/debug.c | 0
> target/riscv/{ => tcg}/fpu_helper.c | 0
> .../insn_trans/trans_privileged.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rva.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvb.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvbf16.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvd.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvf.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvh.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvi.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvk.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvm.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvv.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvvk.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzabha.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzacas.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzalasr.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzawrs.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzce.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzcmop.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzfa.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzfh.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzicbo.c.inc | 0
> .../insn_trans/trans_rvzicfiss.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzicond.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzimop.c.inc | 0
> .../{ => tcg}/insn_trans/trans_svinval.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xlrbr.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xmips.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xthead.c.inc | 0
> .../insn_trans/trans_xventanacondops.c.inc | 0
> .../{ => tcg}/insn_trans/trans_zilsd.c.inc | 0
> target/riscv/{ => tcg}/m128_helper.c | 0
> target/riscv/tcg/meson.build | 30 +++++++++++++++++--
> target/riscv/{ => tcg}/mips_csr.c | 0
> target/riscv/{ => tcg}/op_helper.c | 0
> target/riscv/{ => tcg}/pmu.c | 0
> target/riscv/{ => tcg}/th_csr.c | 0
> target/riscv/{ => tcg}/translate.c | 0
> target/riscv/{ => tcg}/vcrypto_helper.c | 0
> target/riscv/{ => tcg}/vector_helper.c | 0
> target/riscv/{ => tcg}/vector_internals.c | 0
> target/riscv/{ => tcg}/vector_internals.h | 0
> target/riscv/{ => tcg}/zce_helper.c | 0
> 49 files changed, 28 insertions(+), 18 deletions(-)
> rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
> rename target/riscv/{ => tcg}/cpu_helper.c (100%)
> rename target/riscv/{ => tcg}/crypto_helper.c (100%)
> rename target/riscv/{ => tcg}/csr.c (100%)
> rename target/riscv/{ => tcg}/debug.c (100%)
> rename target/riscv/{ => tcg}/fpu_helper.c (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rva.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvb.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvbf16.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvd.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvf.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvh.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvi.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvk.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvm.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvv.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvvk.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzabha.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzacas.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzalasr.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzawrs.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzce.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzcmop.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzfa.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzfh.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicbo.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicfiss.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicond.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzimop.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_svinval.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xlrbr.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xmips.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xthead.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xventanacondops.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_zilsd.c.inc (100%)
> rename target/riscv/{ => tcg}/m128_helper.c (100%)
> rename target/riscv/{ => tcg}/mips_csr.c (100%)
> rename target/riscv/{ => tcg}/op_helper.c (100%)
> rename target/riscv/{ => tcg}/pmu.c (100%)
> rename target/riscv/{ => tcg}/th_csr.c (100%)
> rename target/riscv/{ => tcg}/translate.c (100%)
> rename target/riscv/{ => tcg}/vcrypto_helper.c (100%)
> rename target/riscv/{ => tcg}/vector_helper.c (100%)
> rename target/riscv/{ => tcg}/vector_internals.c (100%)
> rename target/riscv/{ => tcg}/vector_internals.h (100%)
> rename target/riscv/{ => tcg}/zce_helper.c (100%)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 02/24] target/riscv: move TCG only files to tcg subdir
2026-06-22 19:31 ` [PATCH 02/24] target/riscv: move TCG only files to tcg subdir Daniel Henrique Barboza
2026-06-22 20:52 ` Philippe Mathieu-Daudé
@ 2026-06-27 11:04 ` Chao Liu
1 sibling, 0 replies; 71+ messages in thread
From: Chao Liu @ 2026-06-27 11:04 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
philmd, pierrick.bouvier, Palmer Dabbelt
On Mon, Jun 22, 2026 at 04:31:18PM +0800, Daniel Henrique Barboza wrote:
> We have *way* too much TCG-only code hanging around in target/riscv,
> where ideally we would have things that are shared between accelerators.
>
> We'll follow the example of other targets like i386 and loongarch and
> move everything to the tcg subir. This will not only cleanup target/riscv
> but it will also expose what is common code but it's buried inside a TCG
> helper.
>
> We're leaving some stuff behind because these require a little more
> case to not end up breaking KVM. We'll take care of them next.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> ---
> target/riscv/meson.build | 16 ----------
> target/riscv/{ => tcg}/bitmanip_helper.c | 0
> target/riscv/{ => tcg}/cpu_helper.c | 0
> target/riscv/{ => tcg}/crypto_helper.c | 0
> target/riscv/{ => tcg}/csr.c | 0
> target/riscv/{ => tcg}/debug.c | 0
> target/riscv/{ => tcg}/fpu_helper.c | 0
> .../insn_trans/trans_privileged.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rva.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvb.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvbf16.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvd.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvf.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvh.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvi.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvk.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvm.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvv.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvvk.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzabha.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzacas.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzalasr.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzawrs.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzce.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzcmop.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzfa.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzfh.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzicbo.c.inc | 0
> .../insn_trans/trans_rvzicfiss.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzicond.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzimop.c.inc | 0
> .../{ => tcg}/insn_trans/trans_svinval.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xlrbr.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xmips.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xthead.c.inc | 0
> .../insn_trans/trans_xventanacondops.c.inc | 0
> .../{ => tcg}/insn_trans/trans_zilsd.c.inc | 0
> target/riscv/{ => tcg}/m128_helper.c | 0
> target/riscv/tcg/meson.build | 30 +++++++++++++++++--
> target/riscv/{ => tcg}/mips_csr.c | 0
> target/riscv/{ => tcg}/op_helper.c | 0
> target/riscv/{ => tcg}/pmu.c | 0
> target/riscv/{ => tcg}/th_csr.c | 0
> target/riscv/{ => tcg}/translate.c | 0
> target/riscv/{ => tcg}/vcrypto_helper.c | 0
> target/riscv/{ => tcg}/vector_helper.c | 0
> target/riscv/{ => tcg}/vector_internals.c | 0
> target/riscv/{ => tcg}/vector_internals.h | 0
> target/riscv/{ => tcg}/zce_helper.c | 0
> 49 files changed, 28 insertions(+), 18 deletions(-)
> rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
> rename target/riscv/{ => tcg}/cpu_helper.c (100%)
> rename target/riscv/{ => tcg}/crypto_helper.c (100%)
> rename target/riscv/{ => tcg}/csr.c (100%)
> rename target/riscv/{ => tcg}/debug.c (100%)
> rename target/riscv/{ => tcg}/fpu_helper.c (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rva.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvb.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvbf16.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvd.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvf.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvh.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvi.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvk.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvm.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvv.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvvk.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzabha.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzacas.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzalasr.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzawrs.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzce.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzcmop.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzfa.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzfh.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicbo.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicfiss.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicond.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzimop.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_svinval.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xlrbr.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xmips.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xthead.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xventanacondops.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_zilsd.c.inc (100%)
> rename target/riscv/{ => tcg}/m128_helper.c (100%)
> rename target/riscv/{ => tcg}/mips_csr.c (100%)
> rename target/riscv/{ => tcg}/op_helper.c (100%)
> rename target/riscv/{ => tcg}/pmu.c (100%)
> rename target/riscv/{ => tcg}/th_csr.c (100%)
> rename target/riscv/{ => tcg}/translate.c (100%)
> rename target/riscv/{ => tcg}/vcrypto_helper.c (100%)
> rename target/riscv/{ => tcg}/vector_helper.c (100%)
> rename target/riscv/{ => tcg}/vector_internals.c (100%)
> rename target/riscv/{ => tcg}/vector_internals.h (100%)
> rename target/riscv/{ => tcg}/zce_helper.c (100%)
>
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 79f36abd63..61874ed0af 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -16,31 +16,15 @@ riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',
>
> riscv_ss.add(files(
> 'cpu.c',
> - 'cpu_helper.c',
> - 'csr.c',
> - 'fpu_helper.c',
> 'gdbstub.c',
> - 'op_helper.c',
> - 'vector_helper.c',
> - 'vector_internals.c',
> - 'bitmanip_helper.c',
> - 'translate.c',
> - 'm128_helper.c',
> - 'crypto_helper.c',
> - 'zce_helper.c',
> - 'vcrypto_helper.c'
> ))
>
> riscv_system_ss = ss.source_set()
> riscv_system_ss.add(files(
> 'arch_dump.c',
> 'pmp.c',
> - 'debug.c',
> 'monitor.c',
> 'machine.c',
> - 'mips_csr.c',
> - 'pmu.c',
> - 'th_csr.c',
> 'time_helper.c',
> 'riscv-qmp-cmds.c',
> ))
> diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/tcg/bitmanip_helper.c
> similarity index 100%
> rename from target/riscv/bitmanip_helper.c
> rename to target/riscv/tcg/bitmanip_helper.c
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
> similarity index 100%
> rename from target/riscv/cpu_helper.c
> rename to target/riscv/tcg/cpu_helper.c
> diff --git a/target/riscv/crypto_helper.c b/target/riscv/tcg/crypto_helper.c
> similarity index 100%
> rename from target/riscv/crypto_helper.c
> rename to target/riscv/tcg/crypto_helper.c
> diff --git a/target/riscv/csr.c b/target/riscv/tcg/csr.c
> similarity index 100%
> rename from target/riscv/csr.c
> rename to target/riscv/tcg/csr.c
> diff --git a/target/riscv/debug.c b/target/riscv/tcg/debug.c
> similarity index 100%
> rename from target/riscv/debug.c
> rename to target/riscv/tcg/debug.c
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/tcg/fpu_helper.c
> similarity index 100%
> rename from target/riscv/fpu_helper.c
> rename to target/riscv/tcg/fpu_helper.c
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/tcg/insn_trans/trans_privileged.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_privileged.c.inc
> rename to target/riscv/tcg/insn_trans/trans_privileged.c.inc
> diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/tcg/insn_trans/trans_rva.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rva.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rva.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/tcg/insn_trans/trans_rvb.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvb.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvb.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/tcg/insn_trans/trans_rvbf16.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvbf16.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvbf16.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/tcg/insn_trans/trans_rvd.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvd.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvd.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/tcg/insn_trans/trans_rvf.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvf.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvf.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/tcg/insn_trans/trans_rvh.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvh.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvh.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/tcg/insn_trans/trans_rvi.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvi.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvi.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/tcg/insn_trans/trans_rvk.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvk.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvk.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/tcg/insn_trans/trans_rvm.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvm.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvm.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvv.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvv.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/tcg/insn_trans/trans_rvvk.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvvk.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvvk.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/tcg/insn_trans/trans_rvzabha.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzabha.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzabha.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/tcg/insn_trans/trans_rvzacas.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzacas.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzacas.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzalasr.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzawrs.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/tcg/insn_trans/trans_rvzce.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzce.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzce.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzcmop.c.inc b/target/riscv/tcg/insn_trans/trans_rvzcmop.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzcmop.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzcmop.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/tcg/insn_trans/trans_rvzfa.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzfa.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzfa.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzfh.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzfh.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/tcg/insn_trans/trans_rvzicbo.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzicbo.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzicbo.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzicfiss.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzicond.c.inc b/target/riscv/tcg/insn_trans/trans_rvzicond.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzicond.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzicond.c.inc
> diff --git a/target/riscv/insn_trans/trans_rvzimop.c.inc b/target/riscv/tcg/insn_trans/trans_rvzimop.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_rvzimop.c.inc
> rename to target/riscv/tcg/insn_trans/trans_rvzimop.c.inc
> diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_svinval.c.inc
> rename to target/riscv/tcg/insn_trans/trans_svinval.c.inc
> diff --git a/target/riscv/insn_trans/trans_xlrbr.c.inc b/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_xlrbr.c.inc
> rename to target/riscv/tcg/insn_trans/trans_xlrbr.c.inc
> diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/tcg/insn_trans/trans_xmips.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_xmips.c.inc
> rename to target/riscv/tcg/insn_trans/trans_xmips.c.inc
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_xthead.c.inc
> rename to target/riscv/tcg/insn_trans/trans_xthead.c.inc
> diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/tcg/insn_trans/trans_xventanacondops.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_xventanacondops.c.inc
> rename to target/riscv/tcg/insn_trans/trans_xventanacondops.c.inc
> diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/tcg/insn_trans/trans_zilsd.c.inc
> similarity index 100%
> rename from target/riscv/insn_trans/trans_zilsd.c.inc
> rename to target/riscv/tcg/insn_trans/trans_zilsd.c.inc
> diff --git a/target/riscv/m128_helper.c b/target/riscv/tcg/m128_helper.c
> similarity index 100%
> rename from target/riscv/m128_helper.c
> rename to target/riscv/tcg/m128_helper.c
> diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
> index 061df3d74a..5684fcf985 100644
> --- a/target/riscv/tcg/meson.build
> +++ b/target/riscv/tcg/meson.build
> @@ -1,2 +1,28 @@
> -riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
> - 'tcg-cpu.c'))
> +if 'CONFIG_TCG' not in config_all_accel
> + subdir_done()
> +endif
> +
> +riscv_ss.add(files(
> + 'bitmanip_helper.c',
> + 'cpu_helper.c',
> + 'csr.c',
> + 'crypto_helper.c',
> + 'fpu_helper.c',
> + 'm128_helper.c',
> + 'op_helper.c',
> + 'translate.c',
> + 'tcg-cpu.c',
> + 'vcrypto_helper.c',
> + 'vector_helper.c',
> + 'vector_internals.c',
> + 'zce_helper.c'))
> +
> +
> +riscv_system_ss.add(files(
> + 'debug.c',
> + 'mips_csr.c',
> + 'pmu.c',
> + 'th_csr.c',
> +))
> +
> +
> diff --git a/target/riscv/mips_csr.c b/target/riscv/tcg/mips_csr.c
> similarity index 100%
> rename from target/riscv/mips_csr.c
> rename to target/riscv/tcg/mips_csr.c
> diff --git a/target/riscv/op_helper.c b/target/riscv/tcg/op_helper.c
> similarity index 100%
> rename from target/riscv/op_helper.c
> rename to target/riscv/tcg/op_helper.c
> diff --git a/target/riscv/pmu.c b/target/riscv/tcg/pmu.c
> similarity index 100%
> rename from target/riscv/pmu.c
> rename to target/riscv/tcg/pmu.c
> diff --git a/target/riscv/th_csr.c b/target/riscv/tcg/th_csr.c
> similarity index 100%
> rename from target/riscv/th_csr.c
> rename to target/riscv/tcg/th_csr.c
> diff --git a/target/riscv/translate.c b/target/riscv/tcg/translate.c
> similarity index 100%
> rename from target/riscv/translate.c
> rename to target/riscv/tcg/translate.c
> diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/tcg/vcrypto_helper.c
> similarity index 100%
> rename from target/riscv/vcrypto_helper.c
> rename to target/riscv/tcg/vcrypto_helper.c
> diff --git a/target/riscv/vector_helper.c b/target/riscv/tcg/vector_helper.c
> similarity index 100%
> rename from target/riscv/vector_helper.c
> rename to target/riscv/tcg/vector_helper.c
> diff --git a/target/riscv/vector_internals.c b/target/riscv/tcg/vector_internals.c
> similarity index 100%
> rename from target/riscv/vector_internals.c
> rename to target/riscv/tcg/vector_internals.c
> diff --git a/target/riscv/vector_internals.h b/target/riscv/tcg/vector_internals.h
> similarity index 100%
> rename from target/riscv/vector_internals.h
> rename to target/riscv/tcg/vector_internals.h
> diff --git a/target/riscv/zce_helper.c b/target/riscv/tcg/zce_helper.c
> similarity index 100%
> rename from target/riscv/zce_helper.c
> rename to target/riscv/tcg/zce_helper.c
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 03/24] target/riscv/machine.c: do not migrate pmp state with kvm
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 01/24] target/riscv: Remove unused tcg/tcg.h include Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 02/24] target/riscv: move TCG only files to tcg subdir Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:25 ` Philippe Mathieu-Daudé
2026-06-27 11:45 ` Chao Liu
2026-06-22 19:31 ` [PATCH 04/24] target/riscv: move pmp files to tcg subdir Daniel Henrique Barboza
` (21 subsequent siblings)
24 siblings, 2 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
The PMP emulation isn't present in the KVM driver.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/machine.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index ba96ceceef..bd93d6f3a8 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -20,6 +20,7 @@
#include "cpu.h"
#include "qemu/error-report.h"
#include "system/kvm.h"
+#include "system/tcg.h"
#include "migration/cpu.h"
#include "exec/icount.h"
#include "target/riscv/debug.h"
@@ -29,6 +30,10 @@ static bool pmp_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
+ if (kvm_enabled()) {
+ return false;
+ }
+
return cpu->cfg.pmp;
}
@@ -39,10 +44,12 @@ static int pmp_post_load(void *opaque, int version_id)
int i;
uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
- for (i = 0; i < pmp_regions; i++) {
- pmp_update_rule_addr(env, i);
+ if (tcg_enabled()) {
+ for (i = 0; i < pmp_regions; i++) {
+ pmp_update_rule_addr(env, i);
+ }
+ pmp_update_rule_nums(env);
}
- pmp_update_rule_nums(env);
return 0;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 03/24] target/riscv/machine.c: do not migrate pmp state with kvm
2026-06-22 19:31 ` [PATCH 03/24] target/riscv/machine.c: do not migrate pmp state with kvm Daniel Henrique Barboza
@ 2026-06-22 21:25 ` Philippe Mathieu-Daudé
2026-06-23 10:25 ` Philippe Mathieu-Daudé
2026-06-23 14:59 ` Richard Henderson
2026-06-27 11:45 ` Chao Liu
1 sibling, 2 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:25 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> The PMP emulation isn't present in the KVM driver.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/machine.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index ba96ceceef..bd93d6f3a8 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -20,6 +20,7 @@
> #include "cpu.h"
> #include "qemu/error-report.h"
> #include "system/kvm.h"
> +#include "system/tcg.h"
> #include "migration/cpu.h"
> #include "exec/icount.h"
> #include "target/riscv/debug.h"
> @@ -29,6 +30,10 @@ static bool pmp_needed(void *opaque)
> {
> RISCVCPU *cpu = opaque;
>
> + if (kvm_enabled()) {
> + return false;
> + }
> +
> return cpu->cfg.pmp;
Here we want to keep logic parity, in case another RISCV
accelerator is added:
return tcg_enabled() ? cpu->cfg.pmp : false;
> }
>
> @@ -39,10 +44,12 @@ static int pmp_post_load(void *opaque, int version_id)
> int i;
> uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
>
> - for (i = 0; i < pmp_regions; i++) {
> - pmp_update_rule_addr(env, i);
> + if (tcg_enabled()) {
> + for (i = 0; i < pmp_regions; i++) {
> + pmp_update_rule_addr(env, i);
> + }
> + pmp_update_rule_nums(env);
> }
> - pmp_update_rule_nums(env);
>
> return 0;
> }
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 03/24] target/riscv/machine.c: do not migrate pmp state with kvm
2026-06-22 21:25 ` Philippe Mathieu-Daudé
@ 2026-06-23 10:25 ` Philippe Mathieu-Daudé
2026-06-23 14:59 ` Richard Henderson
1 sibling, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-23 10:25 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 23:25, Philippe Mathieu-Daudé wrote:
> On 22/6/26 21:31, Daniel Henrique Barboza wrote:
>> The PMP emulation isn't present in the KVM driver.
>>
>> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
>> ---
>> target/riscv/machine.c | 13 ++++++++++---
>> 1 file changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
>> index ba96ceceef..bd93d6f3a8 100644
>> --- a/target/riscv/machine.c
>> +++ b/target/riscv/machine.c
>> @@ -20,6 +20,7 @@
>> #include "cpu.h"
>> #include "qemu/error-report.h"
>> #include "system/kvm.h"
>> +#include "system/tcg.h"
>> #include "migration/cpu.h"
>> #include "exec/icount.h"
>> #include "target/riscv/debug.h"
>> @@ -29,6 +30,10 @@ static bool pmp_needed(void *opaque)
>> {
>> RISCVCPU *cpu = opaque;
>> + if (kvm_enabled()) {
>> + return false;
>> + }
>> +
>> return cpu->cfg.pmp;
>
> Here we want to keep logic parity, in case another RISCV
> accelerator is added:
>
> return tcg_enabled() ? cpu->cfg.pmp : false;
FYI there is also the hwaccel_enabled() helper, but I don't think
it applies here.
>
>> }
>> @@ -39,10 +44,12 @@ static int pmp_post_load(void *opaque, int
>> version_id)
>> int i;
>> uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
>> - for (i = 0; i < pmp_regions; i++) {
>> - pmp_update_rule_addr(env, i);
>> + if (tcg_enabled()) {
>> + for (i = 0; i < pmp_regions; i++) {
>> + pmp_update_rule_addr(env, i);
>> + }
>> + pmp_update_rule_nums(env);
>> }
>> - pmp_update_rule_nums(env);
>> return 0;
>> }
>
>
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 03/24] target/riscv/machine.c: do not migrate pmp state with kvm
2026-06-22 21:25 ` Philippe Mathieu-Daudé
2026-06-23 10:25 ` Philippe Mathieu-Daudé
@ 2026-06-23 14:59 ` Richard Henderson
1 sibling, 0 replies; 71+ messages in thread
From: Richard Henderson @ 2026-06-23 14:59 UTC (permalink / raw)
To: qemu-devel
On 6/22/26 14:25, Philippe Mathieu-Daudé wrote:
> Here we want to keep logic parity, in case another RISCV
> accelerator is added:
>
> return tcg_enabled() ? cpu->cfg.pmp : false;
tcg_enabled() && cpu->cfg.pmp
r~
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 03/24] target/riscv/machine.c: do not migrate pmp state with kvm
2026-06-22 19:31 ` [PATCH 03/24] target/riscv/machine.c: do not migrate pmp state with kvm Daniel Henrique Barboza
2026-06-22 21:25 ` Philippe Mathieu-Daudé
@ 2026-06-27 11:45 ` Chao Liu
1 sibling, 0 replies; 71+ messages in thread
From: Chao Liu @ 2026-06-27 11:45 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
philmd, pierrick.bouvier, Palmer Dabbelt
On Mon, Jun 22, 2026 at 04:31:19PM +0800, Daniel Henrique Barboza wrote:
> The PMP emulation isn't present in the KVM driver.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> ---
> target/riscv/machine.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index ba96ceceef..bd93d6f3a8 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -20,6 +20,7 @@
> #include "cpu.h"
> #include "qemu/error-report.h"
> #include "system/kvm.h"
> +#include "system/tcg.h"
> #include "migration/cpu.h"
> #include "exec/icount.h"
> #include "target/riscv/debug.h"
> @@ -29,6 +30,10 @@ static bool pmp_needed(void *opaque)
> {
> RISCVCPU *cpu = opaque;
>
> + if (kvm_enabled()) {
> + return false;
> + }
> +
> return cpu->cfg.pmp;
> }
>
> @@ -39,10 +44,12 @@ static int pmp_post_load(void *opaque, int version_id)
> int i;
> uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
>
> - for (i = 0; i < pmp_regions; i++) {
> - pmp_update_rule_addr(env, i);
> + if (tcg_enabled()) {
> + for (i = 0; i < pmp_regions; i++) {
> + pmp_update_rule_addr(env, i);
> + }
> + pmp_update_rule_nums(env);
> }
> - pmp_update_rule_nums(env);
>
> return 0;
> }
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 04/24] target/riscv: move pmp files to tcg subdir
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (2 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 03/24] target/riscv/machine.c: do not migrate pmp state with kvm Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 20:53 ` Philippe Mathieu-Daudé
2026-06-27 11:51 ` Chao Liu
2026-06-22 19:31 ` [PATCH 05/24] target/riscv: make some riscv_sysemu_ops TCG only Daniel Henrique Barboza
` (20 subsequent siblings)
24 siblings, 2 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
A trivial header change is required too.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/meson.build | 1 -
target/riscv/tcg/meson.build | 1 +
target/riscv/{ => tcg}/pmp.c | 0
target/riscv/{ => tcg}/pmp.h | 0
5 files changed, 2 insertions(+), 2 deletions(-)
rename target/riscv/{ => tcg}/pmp.c (100%)
rename target/riscv/{ => tcg}/pmp.h (100%)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bdd28d329b..f0c78c1474 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -183,7 +183,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[];
#define MMU_USER_IDX 3
#if !defined(CONFIG_USER_ONLY)
-#include "pmp.h"
+#include "tcg/pmp.h"
#endif
#define RV_VLEN_MAX 1024
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 61874ed0af..42d0f6d538 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -22,7 +22,6 @@ riscv_ss.add(files(
riscv_system_ss = ss.source_set()
riscv_system_ss.add(files(
'arch_dump.c',
- 'pmp.c',
'monitor.c',
'machine.c',
'time_helper.c',
diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
index 5684fcf985..a05ab642f4 100644
--- a/target/riscv/tcg/meson.build
+++ b/target/riscv/tcg/meson.build
@@ -21,6 +21,7 @@ riscv_ss.add(files(
riscv_system_ss.add(files(
'debug.c',
'mips_csr.c',
+ 'pmp.c',
'pmu.c',
'th_csr.c',
))
diff --git a/target/riscv/pmp.c b/target/riscv/tcg/pmp.c
similarity index 100%
rename from target/riscv/pmp.c
rename to target/riscv/tcg/pmp.c
diff --git a/target/riscv/pmp.h b/target/riscv/tcg/pmp.h
similarity index 100%
rename from target/riscv/pmp.h
rename to target/riscv/tcg/pmp.h
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 04/24] target/riscv: move pmp files to tcg subdir
2026-06-22 19:31 ` [PATCH 04/24] target/riscv: move pmp files to tcg subdir Daniel Henrique Barboza
@ 2026-06-22 20:53 ` Philippe Mathieu-Daudé
2026-06-27 11:51 ` Chao Liu
1 sibling, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 20:53 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> A trivial header change is required too.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.h | 2 +-
> target/riscv/meson.build | 1 -
> target/riscv/tcg/meson.build | 1 +
> target/riscv/{ => tcg}/pmp.c | 0
> target/riscv/{ => tcg}/pmp.h | 0
> 5 files changed, 2 insertions(+), 2 deletions(-)
> rename target/riscv/{ => tcg}/pmp.c (100%)
> rename target/riscv/{ => tcg}/pmp.h (100%)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 04/24] target/riscv: move pmp files to tcg subdir
2026-06-22 19:31 ` [PATCH 04/24] target/riscv: move pmp files to tcg subdir Daniel Henrique Barboza
2026-06-22 20:53 ` Philippe Mathieu-Daudé
@ 2026-06-27 11:51 ` Chao Liu
1 sibling, 0 replies; 71+ messages in thread
From: Chao Liu @ 2026-06-27 11:51 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
philmd, pierrick.bouvier, Palmer Dabbelt
On Mon, Jun 22, 2026 at 04:31:20PM +0800, Daniel Henrique Barboza wrote:
> A trivial header change is required too.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> ---
> target/riscv/cpu.h | 2 +-
> target/riscv/meson.build | 1 -
> target/riscv/tcg/meson.build | 1 +
> target/riscv/{ => tcg}/pmp.c | 0
> target/riscv/{ => tcg}/pmp.h | 0
> 5 files changed, 2 insertions(+), 2 deletions(-)
> rename target/riscv/{ => tcg}/pmp.c (100%)
> rename target/riscv/{ => tcg}/pmp.h (100%)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index bdd28d329b..f0c78c1474 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -183,7 +183,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[];
> #define MMU_USER_IDX 3
>
> #if !defined(CONFIG_USER_ONLY)
> -#include "pmp.h"
> +#include "tcg/pmp.h"
> #endif
>
> #define RV_VLEN_MAX 1024
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 61874ed0af..42d0f6d538 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -22,7 +22,6 @@ riscv_ss.add(files(
> riscv_system_ss = ss.source_set()
> riscv_system_ss.add(files(
> 'arch_dump.c',
> - 'pmp.c',
> 'monitor.c',
> 'machine.c',
> 'time_helper.c',
> diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
> index 5684fcf985..a05ab642f4 100644
> --- a/target/riscv/tcg/meson.build
> +++ b/target/riscv/tcg/meson.build
> @@ -21,6 +21,7 @@ riscv_ss.add(files(
> riscv_system_ss.add(files(
> 'debug.c',
> 'mips_csr.c',
> + 'pmp.c',
> 'pmu.c',
> 'th_csr.c',
> ))
> diff --git a/target/riscv/pmp.c b/target/riscv/tcg/pmp.c
> similarity index 100%
> rename from target/riscv/pmp.c
> rename to target/riscv/tcg/pmp.c
> diff --git a/target/riscv/pmp.h b/target/riscv/tcg/pmp.h
> similarity index 100%
> rename from target/riscv/pmp.h
> rename to target/riscv/tcg/pmp.h
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 05/24] target/riscv: make some riscv_sysemu_ops TCG only
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (3 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 04/24] target/riscv: move pmp files to tcg subdir Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:30 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 06/24] target/riscv: move pmu.h to tcg subdir Daniel Henrique Barboza
` (19 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
monitor_get_register and phys_add_debug are TCG only.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 6 ++++--
target/riscv/monitor.c | 2 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e96bbeb60..0a7e6f6ed0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2669,11 +2669,13 @@ static int64_t riscv_get_arch_id(CPUState *cs)
static const struct SysemuCPUOps riscv_sysemu_ops = {
.has_work = riscv_cpu_has_work,
- .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,
.write_elf64_note = riscv_cpu_write_elf64_note,
.write_elf32_note = riscv_cpu_write_elf32_note,
- .monitor_get_register = riscv_monitor_get_register_legacy,
.legacy_vmsd = &vmstate_riscv_cpu,
+#ifdef CONFIG_TCG
+ .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,
+ .monitor_get_register = riscv_monitor_get_register_legacy,
+#endif
};
#endif
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 3e89dcaf7c..7aacd1d89c 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -245,6 +245,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
mem_info_svxx(mon, env);
}
+#ifdef CONFIG_TCG
static bool reg_is_ulong_integer(CPURISCVState *env, const char *name,
target_ulong *val, bool is_gprh)
{
@@ -379,3 +380,4 @@ int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
return -EINVAL;
}
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 05/24] target/riscv: make some riscv_sysemu_ops TCG only
2026-06-22 19:31 ` [PATCH 05/24] target/riscv: make some riscv_sysemu_ops TCG only Daniel Henrique Barboza
@ 2026-06-22 21:30 ` Philippe Mathieu-Daudé
2026-06-23 15:02 ` Richard Henderson
2026-06-23 17:25 ` Daniel Henrique Barboza
0 siblings, 2 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:30 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> monitor_get_register and phys_add_debug are TCG only.
They aren't... And get_phys_addr_debug() seems mandatory.
Maybe it happens the RISCV implementation only considers TCG?
If so, maybe this patch is heading in the right direction,
but its description has to be reworded IMHO.
(while here, maybe we can convert to SysemuCPUOps::translate_for_debug?)
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.c | 6 ++++--
> target/riscv/monitor.c | 2 ++
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4e96bbeb60..0a7e6f6ed0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2669,11 +2669,13 @@ static int64_t riscv_get_arch_id(CPUState *cs)
>
> static const struct SysemuCPUOps riscv_sysemu_ops = {
> .has_work = riscv_cpu_has_work,
> - .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,
> .write_elf64_note = riscv_cpu_write_elf64_note,
> .write_elf32_note = riscv_cpu_write_elf32_note,
> - .monitor_get_register = riscv_monitor_get_register_legacy,
> .legacy_vmsd = &vmstate_riscv_cpu,
> +#ifdef CONFIG_TCG
> + .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,
> + .monitor_get_register = riscv_monitor_get_register_legacy,
> +#endif
> };
> #endif
>
> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
> index 3e89dcaf7c..7aacd1d89c 100644
> --- a/target/riscv/monitor.c
> +++ b/target/riscv/monitor.c
> @@ -245,6 +245,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
> mem_info_svxx(mon, env);
> }
>
> +#ifdef CONFIG_TCG
> static bool reg_is_ulong_integer(CPURISCVState *env, const char *name,
> target_ulong *val, bool is_gprh)
> {
> @@ -379,3 +380,4 @@ int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
>
> return -EINVAL;
> }
> +#endif
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 05/24] target/riscv: make some riscv_sysemu_ops TCG only
2026-06-22 21:30 ` Philippe Mathieu-Daudé
@ 2026-06-23 15:02 ` Richard Henderson
2026-06-23 17:25 ` Daniel Henrique Barboza
1 sibling, 0 replies; 71+ messages in thread
From: Richard Henderson @ 2026-06-23 15:02 UTC (permalink / raw)
To: qemu-devel
On 6/22/26 14:30, Philippe Mathieu-Daudé wrote:
> On 22/6/26 21:31, Daniel Henrique Barboza wrote:
>> monitor_get_register and phys_add_debug are TCG only.
>
> They aren't... And get_phys_addr_debug() seems mandatory.
Indeed, that hook is for gdb, and that's supposed to work with kvm too.
r~
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 05/24] target/riscv: make some riscv_sysemu_ops TCG only
2026-06-22 21:30 ` Philippe Mathieu-Daudé
2026-06-23 15:02 ` Richard Henderson
@ 2026-06-23 17:25 ` Daniel Henrique Barboza
2026-06-23 21:15 ` Daniel Henrique Barboza
1 sibling, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-23 17:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 6/22/2026 6:30 PM, Philippe Mathieu-Daudé wrote:
> On 22/6/26 21:31, Daniel Henrique Barboza wrote:
>> monitor_get_register and phys_add_debug are TCG only.
>
> They aren't... And get_phys_addr_debug() seems mandatory.
>
> Maybe it happens the RISCV implementation only considers TCG?
Yeah, the wording I used is bad. What I wanted to say is that the RISC-V
impls of these 2 interfaces are TCG only.
>
> If so, maybe this patch is heading in the right direction,
> but its description has to be reworded IMHO.
>
> (while here, maybe we can convert to SysemuCPUOps::translate_for_debug?)
Do you have an example? maybe we could squash it in this patch or, if needed,
we can add a prep patch.
Daniel
>
>> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
>> ---
>> target/riscv/cpu.c | 6 ++++--
>> target/riscv/monitor.c | 2 ++
>> 2 files changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 4e96bbeb60..0a7e6f6ed0 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -2669,11 +2669,13 @@ static int64_t riscv_get_arch_id(CPUState *cs)
>> static const struct SysemuCPUOps riscv_sysemu_ops = {
>> .has_work = riscv_cpu_has_work,
>> - .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,
>> .write_elf64_note = riscv_cpu_write_elf64_note,
>> .write_elf32_note = riscv_cpu_write_elf32_note,
>> - .monitor_get_register = riscv_monitor_get_register_legacy,
>> .legacy_vmsd = &vmstate_riscv_cpu,
>> +#ifdef CONFIG_TCG
>> + .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,
>> + .monitor_get_register = riscv_monitor_get_register_legacy,
>> +#endif
>> };
>> #endif
>> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
>> index 3e89dcaf7c..7aacd1d89c 100644
>> --- a/target/riscv/monitor.c
>> +++ b/target/riscv/monitor.c
>> @@ -245,6 +245,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
>> mem_info_svxx(mon, env);
>> }
>> +#ifdef CONFIG_TCG
>> static bool reg_is_ulong_integer(CPURISCVState *env, const char *name,
>> target_ulong *val, bool is_gprh)
>> {
>> @@ -379,3 +380,4 @@ int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
>> return -EINVAL;
>> }
>> +#endif
>
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 05/24] target/riscv: make some riscv_sysemu_ops TCG only
2026-06-23 17:25 ` Daniel Henrique Barboza
@ 2026-06-23 21:15 ` Daniel Henrique Barboza
0 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-23 21:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 6/23/2026 2:25 PM, Daniel Henrique Barboza wrote:
>
>
> On 6/22/2026 6:30 PM, Philippe Mathieu-Daudé wrote:
>> On 22/6/26 21:31, Daniel Henrique Barboza wrote:
>>> monitor_get_register and phys_add_debug are TCG only.
>>
>> They aren't... And get_phys_addr_debug() seems mandatory.
>>
>> Maybe it happens the RISCV implementation only considers TCG?
>
> Yeah, the wording I used is bad. What I wanted to say is that the RISC-V
> impls of these 2 interfaces are TCG only.
>
>>
>> If so, maybe this patch is heading in the right direction,
>> but its description has to be reworded IMHO.
>>
>> (while here, maybe we can convert to SysemuCPUOps::translate_for_debug?)
>
> Do you have an example? maybe we could squash it in this patch or, if needed,
> we can add a prep patch.
Just found an easy example in the microblaze code. I'll make the conversion
in this same patch.
Thanks,
Daniel
>
>
> Daniel
>
>>
>>> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
>>> ---
>>> target/riscv/cpu.c | 6 ++++--
>>> target/riscv/monitor.c | 2 ++
>>> 2 files changed, 6 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>>> index 4e96bbeb60..0a7e6f6ed0 100644
>>> --- a/target/riscv/cpu.c
>>> +++ b/target/riscv/cpu.c
>>> @@ -2669,11 +2669,13 @@ static int64_t riscv_get_arch_id(CPUState *cs)
>>> static const struct SysemuCPUOps riscv_sysemu_ops = {
>>> .has_work = riscv_cpu_has_work,
>>> - .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,
>>> .write_elf64_note = riscv_cpu_write_elf64_note,
>>> .write_elf32_note = riscv_cpu_write_elf32_note,
>>> - .monitor_get_register = riscv_monitor_get_register_legacy,
>>> .legacy_vmsd = &vmstate_riscv_cpu,
>>> +#ifdef CONFIG_TCG
>>> + .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,
>>> + .monitor_get_register = riscv_monitor_get_register_legacy,
>>> +#endif
>>> };
>>> #endif
>>> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
>>> index 3e89dcaf7c..7aacd1d89c 100644
>>> --- a/target/riscv/monitor.c
>>> +++ b/target/riscv/monitor.c
>>> @@ -245,6 +245,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
>>> mem_info_svxx(mon, env);
>>> }
>>> +#ifdef CONFIG_TCG
>>> static bool reg_is_ulong_integer(CPURISCVState *env, const char *name,
>>> target_ulong *val, bool is_gprh)
>>> {
>>> @@ -379,3 +380,4 @@ int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
>>> return -EINVAL;
>>> }
>>> +#endif
>>
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 06/24] target/riscv: move pmu.h to tcg subdir
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (4 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 05/24] target/riscv: make some riscv_sysemu_ops TCG only Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 07/24] target/riscv: move debug.h " Daniel Henrique Barboza
` (18 subsequent siblings)
24 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
riscv_pmu_generate_fdt_node() can be moved to fdt_common.c since it has
no PMU TCG internals.
With this change we can remove pmu.h from 'virt.c', which is now
becoming a tcg header since we're moving it to the tcg subdir.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
hw/riscv/fdt-common.c | 52 +++++++++++++++++++++++++++++++++++
hw/riscv/virt.c | 1 -
include/hw/riscv/fdt-common.h | 1 +
target/riscv/tcg/pmu.c | 52 -----------------------------------
target/riscv/{ => tcg}/pmu.h | 1 -
5 files changed, 53 insertions(+), 54 deletions(-)
rename target/riscv/{ => tcg}/pmu.h (95%)
diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c
index e0e31af09b..aa143a618b 100644
--- a/hw/riscv/fdt-common.c
+++ b/hw/riscv/fdt-common.c
@@ -230,3 +230,55 @@ void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size,
}
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
}
+
+/*
+ * To keep it simple, any event can be mapped to any programmable counters in
+ * QEMU. The generic cycle & instruction count events can also be monitored
+ * using programmable counters. In that case, mcycle & minstret must continue
+ * to provide the correct value as well. Heterogeneous PMU per hart is not
+ * supported yet. Thus, number of counters are same across all harts.
+ */
+void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name)
+{
+ uint32_t fdt_event_ctr_map[15] = {};
+
+ /*
+ * The event encoding is specified in the SBI specification
+ * Event idx is a 20bits wide number encoded as follows:
+ * event_idx[19:16] = type
+ * event_idx[15:0] = code
+ * The code field in cache events are encoded as follows:
+ * event_idx.code[15:3] = cache_id
+ * event_idx.code[2:1] = op_id
+ * event_idx.code[0:0] = result_id
+ */
+
+ /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */
+ fdt_event_ctr_map[0] = cpu_to_be32(0x00000001);
+ fdt_event_ctr_map[1] = cpu_to_be32(0x00000001);
+ fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0);
+
+ /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */
+ fdt_event_ctr_map[3] = cpu_to_be32(0x00000002);
+ fdt_event_ctr_map[4] = cpu_to_be32(0x00000002);
+ fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2);
+
+ /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */
+ fdt_event_ctr_map[6] = cpu_to_be32(0x00010019);
+ fdt_event_ctr_map[7] = cpu_to_be32(0x00010019);
+ fdt_event_ctr_map[8] = cpu_to_be32(cmask);
+
+ /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */
+ fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B);
+ fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B);
+ fdt_event_ctr_map[11] = cpu_to_be32(cmask);
+
+ /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */
+ fdt_event_ctr_map[12] = cpu_to_be32(0x00010021);
+ fdt_event_ctr_map[13] = cpu_to_be32(0x00010021);
+ fdt_event_ctr_map[14] = cpu_to_be32(cmask);
+
+ /* This a OpenSBI specific DT property documented in OpenSBI docs */
+ qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters",
+ fdt_event_ctr_map, sizeof(fdt_event_ctr_map));
+}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 92c30a6f4c..a1cf8210be 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -30,7 +30,6 @@
#include "hw/char/serial-mm.h"
#include "target/riscv/cpu.h"
#include "hw/core/sysbus-fdt.h"
-#include "target/riscv/pmu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/iommu.h"
#include "hw/riscv/riscv-iommu-bits.h"
diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h
index 017278b611..1729a6abc6 100644
--- a/include/hw/riscv/fdt-common.h
+++ b/include/hw/riscv/fdt-common.h
@@ -35,4 +35,5 @@ void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size,
uint32_t addr_cells, uint32_t *plic_cells,
uint32_t cells_size, uint32_t ndev_sources,
bool numa_enabled, int socket);
+void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
#endif
diff --git a/target/riscv/tcg/pmu.c b/target/riscv/tcg/pmu.c
index 3444400bd2..38ad2737e1 100644
--- a/target/riscv/tcg/pmu.c
+++ b/target/riscv/tcg/pmu.c
@@ -27,58 +27,6 @@
#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */
-/*
- * To keep it simple, any event can be mapped to any programmable counters in
- * QEMU. The generic cycle & instruction count events can also be monitored
- * using programmable counters. In that case, mcycle & minstret must continue
- * to provide the correct value as well. Heterogeneous PMU per hart is not
- * supported yet. Thus, number of counters are same across all harts.
- */
-void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name)
-{
- uint32_t fdt_event_ctr_map[15] = {};
-
- /*
- * The event encoding is specified in the SBI specification
- * Event idx is a 20bits wide number encoded as follows:
- * event_idx[19:16] = type
- * event_idx[15:0] = code
- * The code field in cache events are encoded as follows:
- * event_idx.code[15:3] = cache_id
- * event_idx.code[2:1] = op_id
- * event_idx.code[0:0] = result_id
- */
-
- /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */
- fdt_event_ctr_map[0] = cpu_to_be32(0x00000001);
- fdt_event_ctr_map[1] = cpu_to_be32(0x00000001);
- fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0);
-
- /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */
- fdt_event_ctr_map[3] = cpu_to_be32(0x00000002);
- fdt_event_ctr_map[4] = cpu_to_be32(0x00000002);
- fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2);
-
- /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */
- fdt_event_ctr_map[6] = cpu_to_be32(0x00010019);
- fdt_event_ctr_map[7] = cpu_to_be32(0x00010019);
- fdt_event_ctr_map[8] = cpu_to_be32(cmask);
-
- /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */
- fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B);
- fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B);
- fdt_event_ctr_map[11] = cpu_to_be32(cmask);
-
- /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */
- fdt_event_ctr_map[12] = cpu_to_be32(0x00010021);
- fdt_event_ctr_map[13] = cpu_to_be32(0x00010021);
- fdt_event_ctr_map[14] = cpu_to_be32(cmask);
-
- /* This a OpenSBI specific DT property documented in OpenSBI docs */
- qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters",
- fdt_event_ctr_map, sizeof(fdt_event_ctr_map));
-}
-
static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx)
{
if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS ||
diff --git a/target/riscv/pmu.h b/target/riscv/tcg/pmu.h
similarity index 95%
rename from target/riscv/pmu.h
rename to target/riscv/tcg/pmu.h
index b4f1e469a2..de2fae1fb4 100644
--- a/target/riscv/pmu.h
+++ b/target/riscv/tcg/pmu.h
@@ -31,7 +31,6 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp);
int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx);
int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
-void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx);
void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, privilege_mode_t newpriv,
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 07/24] target/riscv: move debug.h to tcg subdir
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (5 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 06/24] target/riscv: move pmu.h to tcg subdir Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 20:55 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 08/24] target/riscv: remove csr.h from kvm-cpu.c Daniel Henrique Barboza
` (17 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
riscv_trigger_* APIs are TCG only. Wrap the usages we have of them
in cpu.c with CONFIG_TCG.
After that we can move the header to the tcg subdir. This will be
enough to get this out of the way for the --disable-tcg build.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 8 +++++---
target/riscv/machine.c | 2 +-
target/riscv/tcg/cpu_helper.c | 2 +-
target/riscv/tcg/csr.c | 2 +-
target/riscv/tcg/debug.c | 2 +-
target/riscv/{ => tcg}/debug.h | 0
target/riscv/tcg/tcg-cpu.c | 2 +-
7 files changed, 10 insertions(+), 8 deletions(-)
rename target/riscv/{ => tcg}/debug.h (100%)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0a7e6f6ed0..f999042178 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -39,7 +39,7 @@
#include "kvm/kvm_riscv.h"
#include "tcg/tcg-cpu.h"
#if !defined(CONFIG_USER_ONLY)
-#include "target/riscv/debug.h"
+#include "target/riscv/tcg/debug.h"
#endif
/* RISC-V CPU definitions */
@@ -836,9 +836,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
env->vill = true;
#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_TCG
if (cpu->cfg.debug) {
riscv_trigger_reset_hold(env);
}
+#endif
if (cpu->cfg.ext_smrnmi) {
env->rnmip = 0;
@@ -996,7 +998,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
riscv_cpu_register_gdb_regs_for_features(cs);
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
if (cpu->cfg.debug) {
riscv_trigger_realize(&cpu->env);
}
@@ -1011,7 +1013,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
static void riscv_cpu_unrealize(DeviceState *dev)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
RISCVCPU *cpu = RISCV_CPU(dev);
if (cpu->cfg.debug) {
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index bd93d6f3a8..4d89486cad 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -23,7 +23,7 @@
#include "system/tcg.h"
#include "migration/cpu.h"
#include "exec/icount.h"
-#include "target/riscv/debug.h"
+#include "target/riscv/tcg/debug.h"
#include "hw/riscv/machines-qom.h"
static bool pmp_needed(void *opaque)
diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
index 59edcdd370..9293d61024 100644
--- a/target/riscv/tcg/cpu_helper.c
+++ b/target/riscv/tcg/cpu_helper.c
@@ -35,7 +35,7 @@
#include "semihosting/common-semi.h"
#include "exec/icount.h"
#include "cpu_bits.h"
-#include "target/riscv/debug.h"
+#include "target/riscv/tcg/debug.h"
#include "pmp.h"
#include "qemu/plugin.h"
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 7fb0ad5bc1..b460860409 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -34,7 +34,7 @@
#include "tcg/insn-start-words.h"
#include "internals.h"
#if !defined(CONFIG_USER_ONLY)
-#include "target/riscv/debug.h"
+#include "target/riscv/tcg/debug.h"
#endif
/* CSR function table public API */
diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
index ba5bc6ae13..3c0fe70101 100644
--- a/target/riscv/tcg/debug.c
+++ b/target/riscv/tcg/debug.c
@@ -28,7 +28,7 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "cpu.h"
-#include "target/riscv/debug.h"
+#include "target/riscv/tcg/debug.h"
#include "trace.h"
#include "exec/helper-proto.h"
#include "exec/watchpoint.h"
diff --git a/target/riscv/debug.h b/target/riscv/tcg/debug.h
similarity index 100%
rename from target/riscv/debug.h
rename to target/riscv/tcg/debug.h
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b73e3e9dd4..fe6350f497 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -37,7 +37,7 @@
#include "hw/core/boards.h"
#include "system/tcg.h"
#include "exec/icount.h"
-#include "target/riscv/debug.h"
+#include "target/riscv/tcg/debug.h"
#endif
/* Hash that stores user set extensions */
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 07/24] target/riscv: move debug.h to tcg subdir
2026-06-22 19:31 ` [PATCH 07/24] target/riscv: move debug.h " Daniel Henrique Barboza
@ 2026-06-22 20:55 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 20:55 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> riscv_trigger_* APIs are TCG only. Wrap the usages we have of them
> in cpu.c with CONFIG_TCG.
>
> After that we can move the header to the tcg subdir. This will be
> enough to get this out of the way for the --disable-tcg build.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.c | 8 +++++---
> target/riscv/machine.c | 2 +-
> target/riscv/tcg/cpu_helper.c | 2 +-
> target/riscv/tcg/csr.c | 2 +-
> target/riscv/tcg/debug.c | 2 +-
> target/riscv/{ => tcg}/debug.h | 0
> target/riscv/tcg/tcg-cpu.c | 2 +-
> 7 files changed, 10 insertions(+), 8 deletions(-)
> rename target/riscv/{ => tcg}/debug.h (100%)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 08/24] target/riscv: remove csr.h from kvm-cpu.c
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (6 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 07/24] target/riscv: move debug.h " Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 20:57 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 09/24] target/riscv: move csr.h to tcg subdir Daniel Henrique Barboza
` (16 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
Move riscv_new_csr_seed from csr.c to cpu.c since this function is
shared with KVM. With that we can remove the csr.h from kvm-cpu.c.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
target/riscv/cpu.h | 3 ++-
target/riscv/csr.h | 3 ---
target/riscv/kvm/kvm-cpu.c | 1 -
target/riscv/tcg/csr.c | 29 -----------------------------
5 files changed, 32 insertions(+), 34 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f999042178..8fe524be21 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -21,6 +21,7 @@
#include "qemu/qemu-print.h"
#include "qemu/ctype.h"
#include "qemu/log.h"
+#include "qemu/guest-random.h"
#include "cpu.h"
#include "cpu_vendorid.h"
#include "target/riscv/csr.h"
@@ -536,6 +537,35 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
}
#endif
+/* Used by csr.c and the KVM driver */
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+ target_ulong write_mask)
+{
+ uint16_t random_v;
+ Error *random_e = NULL;
+ int random_r;
+ target_ulong rval;
+
+ random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
+ if (unlikely(random_r < 0)) {
+ /*
+ * Failed, for unknown reasons in the crypto subsystem.
+ * The best we can do is log the reason and return a
+ * failure indication to the guest. There is no reason
+ * we know to expect the failure to be transitory, so
+ * indicate DEAD to avoid having the guest spin on WAIT.
+ */
+ qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
+ __func__, error_get_pretty(random_e));
+ error_free(random_e);
+ rval = SEED_OPST_DEAD;
+ } else {
+ rval = random_v | SEED_OPST_ES16;
+ }
+
+ return rval;
+}
+
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f0c78c1474..4fc82d2477 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -971,7 +971,8 @@ bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu);
extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
-
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+ target_ulong write_mask);
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
const char *priv_spec_to_str(int priv_version);
diff --git a/target/riscv/csr.h b/target/riscv/csr.h
index c791260f83..73d874ee98 100644
--- a/target/riscv/csr.h
+++ b/target/riscv/csr.h
@@ -12,9 +12,6 @@
#include "exec/target_long.h"
#include "cpu_bits.h"
-target_ulong riscv_new_csr_seed(target_ulong new_value,
- target_ulong write_mask);
-
RISCVException riscv_csrr(CPURISCVState *env, int csrno,
target_ulong *ret_value);
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 39d48a9db4..dcdaf7f2b3 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -31,7 +31,6 @@
#include "system/kvm.h"
#include "system/kvm_int.h"
#include "cpu.h"
-#include "target/riscv/csr.h"
#include "trace.h"
#include "accel/accel-cpu-target.h"
#include "hw/pci/pci.h"
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index b460860409..d447204721 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -29,7 +29,6 @@
#include "exec/icount.h"
#include "accel/tcg/cpu-loop.h"
#include "accel/tcg/getpc.h"
-#include "qemu/guest-random.h"
#include "qapi/error.h"
#include "tcg/insn-start-words.h"
#include "internals.h"
@@ -5577,34 +5576,6 @@ static RISCVException write_mnstatus(CPURISCVState *env, int csrno,
#endif
/* Crypto Extension */
-target_ulong riscv_new_csr_seed(target_ulong new_value,
- target_ulong write_mask)
-{
- uint16_t random_v;
- Error *random_e = NULL;
- int random_r;
- target_ulong rval;
-
- random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
- if (unlikely(random_r < 0)) {
- /*
- * Failed, for unknown reasons in the crypto subsystem.
- * The best we can do is log the reason and return a
- * failure indication to the guest. There is no reason
- * we know to expect the failure to be transitory, so
- * indicate DEAD to avoid having the guest spin on WAIT.
- */
- qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
- __func__, error_get_pretty(random_e));
- error_free(random_e);
- rval = SEED_OPST_DEAD;
- } else {
- rval = random_v | SEED_OPST_ES16;
- }
-
- return rval;
-}
-
static RISCVException rmw_seed(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value,
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 08/24] target/riscv: remove csr.h from kvm-cpu.c
2026-06-22 19:31 ` [PATCH 08/24] target/riscv: remove csr.h from kvm-cpu.c Daniel Henrique Barboza
@ 2026-06-22 20:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 20:57 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> Move riscv_new_csr_seed from csr.c to cpu.c since this function is
> shared with KVM. With that we can remove the csr.h from kvm-cpu.c.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
> target/riscv/cpu.h | 3 ++-
> target/riscv/csr.h | 3 ---
> target/riscv/kvm/kvm-cpu.c | 1 -
> target/riscv/tcg/csr.c | 29 -----------------------------
> 5 files changed, 32 insertions(+), 34 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 09/24] target/riscv: move csr.h to tcg subdir
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (7 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 08/24] target/riscv: remove csr.h from kvm-cpu.c Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 20:58 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 10/24] target/riscv: move custom_csrs logic to tcg-cpu.c Daniel Henrique Barboza
` (15 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
After KVM is no longer reliant on csr.h move it to the TGC only land.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/gdbstub.c | 2 +-
target/riscv/monitor.c | 2 +-
target/riscv/riscv-qmp-cmds.c | 2 +-
target/riscv/tcg/csr.c | 2 +-
target/riscv/{ => tcg}/csr.h | 0
target/riscv/tcg/mips_csr.c | 2 +-
target/riscv/tcg/op_helper.c | 2 +-
target/riscv/tcg/pmp.c | 2 +-
target/riscv/tcg/th_csr.c | 2 +-
10 files changed, 9 insertions(+), 9 deletions(-)
rename target/riscv/{ => tcg}/csr.h (100%)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8fe524be21..503b96bf2e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -24,7 +24,7 @@
#include "qemu/guest-random.h"
#include "cpu.h"
#include "cpu_vendorid.h"
-#include "target/riscv/csr.h"
+#include "target/riscv/tcg/csr.h"
#include "internals.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index a2bbaf7f07..f0a5e0d86f 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -21,7 +21,7 @@
#include "gdbstub/helpers.h"
#include "cpu.h"
#include "internals.h"
-#include "target/riscv/csr.h"
+#include "target/riscv/tcg/csr.h"
struct TypeSize {
const char *gdb_type;
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 7aacd1d89c..f8042db9cd 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -22,7 +22,7 @@
#include "qemu/ctype.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
-#include "target/riscv/csr.h"
+#include "target/riscv/tcg/csr.h"
#include "cpu_bits.h"
#include "monitor/monitor.h"
#include "monitor/hmp.h"
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
index b94e8391ed..2647deef91 100644
--- a/target/riscv/riscv-qmp-cmds.c
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -35,7 +35,7 @@
#include "system/tcg.h"
#include "cpu-qom.h"
#include "cpu.h"
-#include "target/riscv/csr.h"
+#include "target/riscv/tcg/csr.h"
static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
{
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index d447204721..572a39d660 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -21,7 +21,7 @@
#include "qemu/log.h"
#include "qemu/timer.h"
#include "cpu.h"
-#include "target/riscv/csr.h"
+#include "target/riscv/tcg/csr.h"
#include "tcg/tcg-cpu.h"
#include "pmu.h"
#include "time_helper.h"
diff --git a/target/riscv/csr.h b/target/riscv/tcg/csr.h
similarity index 100%
rename from target/riscv/csr.h
rename to target/riscv/tcg/csr.h
diff --git a/target/riscv/tcg/mips_csr.c b/target/riscv/tcg/mips_csr.c
index 609718f288..884030e91d 100644
--- a/target/riscv/tcg/mips_csr.c
+++ b/target/riscv/tcg/mips_csr.c
@@ -10,7 +10,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "cpu_vendorid.h"
-#include "target/riscv/csr.h"
+#include "target/riscv/tcg/csr.h"
/* Static MIPS CSR state storage */
static struct {
diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c
index 775fd431d6..003f6ebb31 100644
--- a/target/riscv/tcg/op_helper.c
+++ b/target/riscv/tcg/op_helper.c
@@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "target/riscv/csr.h"
+#include "target/riscv/tcg/csr.h"
#include "internals.h"
#include "exec/cputlb.h"
#include "accel/tcg/cpu-ldst.h"
diff --git a/target/riscv/tcg/pmp.c b/target/riscv/tcg/pmp.c
index d93563c36b..41b55519a8 100644
--- a/target/riscv/tcg/pmp.c
+++ b/target/riscv/tcg/pmp.c
@@ -23,7 +23,7 @@
#include "qemu/log.h"
#include "qapi/error.h"
#include "cpu.h"
-#include "target/riscv/csr.h"
+#include "target/riscv/tcg/csr.h"
#include "trace.h"
#include "exec/cputlb.h"
#include "exec/page-protection.h"
diff --git a/target/riscv/tcg/th_csr.c b/target/riscv/tcg/th_csr.c
index 431f4cc286..e6f642991c 100644
--- a/target/riscv/tcg/th_csr.c
+++ b/target/riscv/tcg/th_csr.c
@@ -22,7 +22,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "cpu_vendorid.h"
-#include "target/riscv/csr.h"
+#include "target/riscv/tcg/csr.h"
/* Extended M-mode control registers of T-Head */
#define CSR_TH_MXSTATUS 0x7c0
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 09/24] target/riscv: move csr.h to tcg subdir
2026-06-22 19:31 ` [PATCH 09/24] target/riscv: move csr.h to tcg subdir Daniel Henrique Barboza
@ 2026-06-22 20:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 20:58 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> After KVM is no longer reliant on csr.h move it to the TGC only land.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/gdbstub.c | 2 +-
> target/riscv/monitor.c | 2 +-
> target/riscv/riscv-qmp-cmds.c | 2 +-
> target/riscv/tcg/csr.c | 2 +-
> target/riscv/{ => tcg}/csr.h | 0
> target/riscv/tcg/mips_csr.c | 2 +-
> target/riscv/tcg/op_helper.c | 2 +-
> target/riscv/tcg/pmp.c | 2 +-
> target/riscv/tcg/th_csr.c | 2 +-
> 10 files changed, 9 insertions(+), 9 deletions(-)
> rename target/riscv/{ => tcg}/csr.h (100%)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 10/24] target/riscv: move custom_csrs logic to tcg-cpu.c
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (8 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 09/24] target/riscv: move csr.h to tcg subdir Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:02 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 11/24] target/riscv: move riscv_cpu_set_nmi() " Daniel Henrique Barboza
` (14 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
We have a couple of CPUs that has a set of custom CSRs that uses TCG
specific APIs. Move the related code to tcg-cpu.c and do not set
.custom_csrs if we're not in a TCG build.
What we'll end up doing, sooner or later, is punting all these CPUs to
tcg-cpu.c since they're all TCG specific and KVM has nothing to do with
them. Another time.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 24 +++---------------------
target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++
2 files changed, 24 insertions(+), 21 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 503b96bf2e..0c5e000f17 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -524,19 +524,6 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
}
#endif
-#ifndef CONFIG_USER_ONLY
-static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
-{
- for (size_t i = 0; csr_list[i].csr_ops.name; i++) {
- int csrno = csr_list[i].csrno;
- const riscv_csr_operations *csr_ops = &csr_list[i].csr_ops;
- if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)) {
- riscv_set_csr_ops(csrno, csr_ops);
- }
- }
-}
-#endif
-
/* Used by csr.c and the KVM driver */
target_ulong riscv_new_csr_seed(target_ulong new_value,
target_ulong write_mask)
@@ -1244,11 +1231,6 @@ static void riscv_cpu_init(Object *obj)
if (mcc->def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) {
cpu->env.vext_ver = mcc->def->vext_spec;
}
-#ifndef CONFIG_USER_ONLY
- if (mcc->def->custom_csrs) {
- riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);
- }
-#endif
accel_cpu_instance_init(CPU(obj));
}
@@ -3178,7 +3160,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.mvendorid = THEAD_VENDOR_ID,
.cfg.max_satp_mode = VM_1_10_SV39,
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
.custom_csrs = th_csr_list,
#endif
),
@@ -3224,7 +3206,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.marchid = 0x8d143000,
.cfg.mvendorid = THEAD_VENDOR_ID,
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
.custom_csrs = th_csr_list,
#endif
),
@@ -3429,7 +3411,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.ext_xmipscmov = true,
.cfg.marchid = 0x8000000000000201,
.cfg.mvendorid = MIPS_VENDOR_ID,
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
.custom_csrs = mips_csr_list,
#endif
),
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fe6350f497..fef66557c2 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -38,6 +38,7 @@
#include "system/tcg.h"
#include "exec/icount.h"
#include "target/riscv/tcg/debug.h"
+#include "target/riscv/tcg/csr.h"
#endif
/* Hash that stores user set extensions */
@@ -1650,10 +1651,30 @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
}
+#ifndef CONFIG_USER_ONLY
+static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
+{
+ for (size_t i = 0; csr_list[i].csr_ops.name; i++) {
+ int csrno = csr_list[i].csrno;
+ const riscv_csr_operations *csr_ops = &csr_list[i].csr_ops;
+ if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)) {
+ riscv_set_csr_ops(csrno, csr_ops);
+ }
+ }
+}
+#endif
+
static void riscv_tcg_cpu_instance_init(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
Object *obj = OBJECT(cpu);
+#ifndef CONFIG_USER_ONLY
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
+
+ if (mcc->def->custom_csrs) {
+ riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);
+ }
+#endif
misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 10/24] target/riscv: move custom_csrs logic to tcg-cpu.c
2026-06-22 19:31 ` [PATCH 10/24] target/riscv: move custom_csrs logic to tcg-cpu.c Daniel Henrique Barboza
@ 2026-06-22 21:02 ` Philippe Mathieu-Daudé
2026-06-23 19:19 ` Daniel Henrique Barboza
0 siblings, 1 reply; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:02 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> We have a couple of CPUs that has a set of custom CSRs that uses TCG
> specific APIs. Move the related code to tcg-cpu.c and do not set
> .custom_csrs if we're not in a TCG build.
>
> What we'll end up doing, sooner or later, is punting all these CPUs to
> tcg-cpu.c since they're all TCG specific and KVM has nothing to do with
> them. Another time.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.c | 24 +++---------------------
> target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++
> 2 files changed, 24 insertions(+), 21 deletions(-)
Squashing:
-- >8 --
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7582874c351..4e58a5daaba 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -570,7 +570,9 @@ typedef struct RISCVCPUDef {
int32_t vext_spec;
RISCVCPUConfig cfg;
bool bare;
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
const RISCVCSR *custom_csrs;
+#endif
} RISCVCPUDef;
---
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 10/24] target/riscv: move custom_csrs logic to tcg-cpu.c
2026-06-22 21:02 ` Philippe Mathieu-Daudé
@ 2026-06-23 19:19 ` Daniel Henrique Barboza
0 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-23 19:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 6/22/2026 6:02 PM, Philippe Mathieu-Daudé wrote:
> On 22/6/26 21:31, Daniel Henrique Barboza wrote:
>> We have a couple of CPUs that has a set of custom CSRs that uses TCG
>> specific APIs. Move the related code to tcg-cpu.c and do not set
>> .custom_csrs if we're not in a TCG build.
>>
>> What we'll end up doing, sooner or later, is punting all these CPUs to
>> tcg-cpu.c since they're all TCG specific and KVM has nothing to do with
>> them. Another time.
>>
>> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
>> ---
>> target/riscv/cpu.c | 24 +++---------------------
>> target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++
>> 2 files changed, 24 insertions(+), 21 deletions(-)
>
> Squashing:
>
> -- >8 --
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7582874c351..4e58a5daaba 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -570,7 +570,9 @@ typedef struct RISCVCPUDef {
> int32_t vext_spec;
> RISCVCPUConfig cfg;
> bool bare;
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> const RISCVCSR *custom_csrs;
> +#endif
> } RISCVCPUDef;
>
> ---
Squashed
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>
Ty sir!
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 11/24] target/riscv: move riscv_cpu_set_nmi() to tcg-cpu.c
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (9 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 10/24] target/riscv: move custom_csrs logic to tcg-cpu.c Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:04 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 12/24] target/riscv: move valid_vm_* satp arrays to cpu.c Daniel Henrique Barboza
` (13 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
This function is related to Smrnmi and non-masked interrupts, firing up
interrupts via env->rnmip from riscv_cpu_local_irq_pending().
This is all TCG only code.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 8 --------
target/riscv/tcg/tcg-cpu.c | 7 +++++++
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0c5e000f17..74b6daa76b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1160,11 +1160,6 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
g_assert_not_reached();
}
}
-
-static void riscv_cpu_set_nmi(void *opaque, int irq, int level)
-{
- riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level);
-}
#endif /* CONFIG_USER_ONLY */
static bool riscv_cpu_is_dynamic(Object *cpu_obj)
@@ -1183,9 +1178,6 @@ static void riscv_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
- qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi,
- "riscv.cpu.rnmi", RNMI_MAX);
-
if (mcc->def->num_triggers) {
env->num_triggers = mcc->def->num_triggers;
}
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fef66557c2..0d0a704179 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1662,6 +1662,11 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
}
}
}
+
+static void riscv_cpu_set_nmi(void *opaque, int irq, int level)
+{
+ riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level);
+}
#endif
static void riscv_tcg_cpu_instance_init(CPUState *cs)
@@ -1674,6 +1679,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs)
if (mcc->def->custom_csrs) {
riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);
}
+ qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi,
+ "riscv.cpu.rnmi", RNMI_MAX);
#endif
misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 11/24] target/riscv: move riscv_cpu_set_nmi() to tcg-cpu.c
2026-06-22 19:31 ` [PATCH 11/24] target/riscv: move riscv_cpu_set_nmi() " Daniel Henrique Barboza
@ 2026-06-22 21:04 ` Philippe Mathieu-Daudé
2026-06-23 19:59 ` Daniel Henrique Barboza
0 siblings, 1 reply; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:04 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> This function is related to Smrnmi and non-masked interrupts, firing up
> interrupts via env->rnmip from riscv_cpu_local_irq_pending().
>
> This is all TCG only code.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.c | 8 --------
> target/riscv/tcg/tcg-cpu.c | 7 +++++++
> 2 files changed, 7 insertions(+), 8 deletions(-)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index fef66557c2..0d0a704179 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -1662,6 +1662,11 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
> }
> }
> }
> +
> +static void riscv_cpu_set_nmi(void *opaque, int irq, int level)
> +{
> + riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level);
Preferably inlining riscv_cpu_set_rnmi() here:
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> +}
> #endif
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 11/24] target/riscv: move riscv_cpu_set_nmi() to tcg-cpu.c
2026-06-22 21:04 ` Philippe Mathieu-Daudé
@ 2026-06-23 19:59 ` Daniel Henrique Barboza
0 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-23 19:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 6/22/2026 6:04 PM, Philippe Mathieu-Daudé wrote:
> On 22/6/26 21:31, Daniel Henrique Barboza wrote:
>> This function is related to Smrnmi and non-masked interrupts, firing up
>> interrupts via env->rnmip from riscv_cpu_local_irq_pending().
>>
>> This is all TCG only code.
>>
>> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
>> ---
>> target/riscv/cpu.c | 8 --------
>> target/riscv/tcg/tcg-cpu.c | 7 +++++++
>> 2 files changed, 7 insertions(+), 8 deletions(-)
>
>
>> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
>> index fef66557c2..0d0a704179 100644
>> --- a/target/riscv/tcg/tcg-cpu.c
>> +++ b/target/riscv/tcg/tcg-cpu.c
>> @@ -1662,6 +1662,11 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
>> }
>> }
>> }
>> +
>> +static void riscv_cpu_set_nmi(void *opaque, int irq, int level)
>> +{
>> + riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level);
>
> Preferably inlining riscv_cpu_set_rnmi() here:
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>
Inlined. Thx!
>> +}
>> #endif
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 12/24] target/riscv: move valid_vm_* satp arrays to cpu.c
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (10 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 11/24] target/riscv: move riscv_cpu_set_nmi() " Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 13/24] target/riscv: move some irq helpers " Daniel Henrique Barboza
` (12 subsequent siblings)
24 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
These arrays are used internally in tcg/csr.c and in cpu.c in the satp
options logic, which is common for both KVM and TCG.
Move it to cpu.c to allow KVM to keep using it in --disable-tcg builds.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 13 +++++++++++++
target/riscv/cpu.h | 2 --
target/riscv/tcg/csr.c | 12 ------------
target/riscv/tcg/csr.h | 3 +++
4 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 74b6daa76b..f0ef4c5a4a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -59,6 +59,19 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
#define BYTE(x) (x)
#endif
+/* SATP bits that are shared between TCG and KVM */
+const bool valid_vm_1_10_32[16] = {
+ [VM_1_10_MBARE] = true,
+ [VM_1_10_SV32] = true
+};
+
+const bool valid_vm_1_10_64[16] = {
+ [VM_1_10_MBARE] = true,
+ [VM_1_10_SV39] = true,
+ [VM_1_10_SV48] = true,
+ [VM_1_10_SV57] = true
+};
+
bool riscv_cpu_is_32bit(RISCVCPU *cpu)
{
return riscv_cpu_mxl(&cpu->env) == MXL_RV32;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4fc82d2477..ae6b166d46 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -968,8 +968,6 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
void riscv_add_satp_mode_properties(Object *obj);
bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu);
-extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
-
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
target_ulong riscv_new_csr_seed(target_ulong new_value,
target_ulong write_mask);
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 572a39d660..b17be35e56 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -1874,18 +1874,6 @@ static const uint64_t hvien_writable_mask = LOCAL_INTERRUPTS;
static const uint64_t vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS;
-const bool valid_vm_1_10_32[16] = {
- [VM_1_10_MBARE] = true,
- [VM_1_10_SV32] = true
-};
-
-const bool valid_vm_1_10_64[16] = {
- [VM_1_10_MBARE] = true,
- [VM_1_10_SV39] = true,
- [VM_1_10_SV48] = true,
- [VM_1_10_SV57] = true
-};
-
/* Machine Information Registers */
static RISCVException read_zero(CPURISCVState *env, int csrno,
target_ulong *val)
diff --git a/target/riscv/tcg/csr.h b/target/riscv/tcg/csr.h
index 73d874ee98..53ba3b4a4d 100644
--- a/target/riscv/tcg/csr.h
+++ b/target/riscv/tcg/csr.h
@@ -69,6 +69,9 @@ enum {
CSR_TABLE_SIZE = 0x1000
};
+/* valid_vm_* arrays are shared with KVM via cpu.c */
+extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
+
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 13/24] target/riscv: move some irq helpers to cpu.c
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (11 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 12/24] target/riscv: move valid_vm_* satp arrays to cpu.c Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:07 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 14/24] target/riscv: move riscv_cpu_claim_interrupts " Daniel Henrique Barboza
` (11 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
riscv_cpu_has_work() uses a handful of irq pending functions from
cpu_helper.c. There is a very high possibility that KVM doesn't need
the current implermentation of has_work(), but the common accel code
needs an implementation of this callback (see cpu_exec_class_post_init)
otherwise the KVM driver won't initialize.
Move the relevant irq helpers to cpu.c to allow KVM to keep using the
current has_work implementation, allowing --disable-tcg to work. We'll
circle it back to evaluate a proper KVM implementation for it in a later
date.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 187 ++++++++++++++++++++++++++++++++++
target/riscv/cpu.h | 5 +
target/riscv/tcg/cpu_helper.c | 187 ----------------------------------
3 files changed, 192 insertions(+), 187 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f0ef4c5a4a..41646acfb5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -738,6 +738,193 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
}
#ifndef CONFIG_USER_ONLY
+/*
+ * Default priorities of local interrupts are defined in the
+ * RISC-V Advanced Interrupt Architecture specification.
+ *
+ * ----------------------------------------------------------------
+ * Default |
+ * Priority | Major Interrupt Numbers
+ * ----------------------------------------------------------------
+ * Highest | 47, 23, 46, 45, 22, 44,
+ * | 43, 21, 42, 41, 20, 40
+ * |
+ * | 11 (0b), 3 (03), 7 (07)
+ * | 9 (09), 1 (01), 5 (05)
+ * | 12 (0c)
+ * | 10 (0a), 2 (02), 6 (06)
+ * |
+ * | 39, 19, 38, 37, 18, 36,
+ * Lowest | 35, 17, 34, 33, 16, 32
+ * ----------------------------------------------------------------
+ */
+static const uint8_t default_iprio[64] = {
+ /* Custom interrupts 48 to 63 */
+ [63] = IPRIO_MMAXIPRIO,
+ [62] = IPRIO_MMAXIPRIO,
+ [61] = IPRIO_MMAXIPRIO,
+ [60] = IPRIO_MMAXIPRIO,
+ [59] = IPRIO_MMAXIPRIO,
+ [58] = IPRIO_MMAXIPRIO,
+ [57] = IPRIO_MMAXIPRIO,
+ [56] = IPRIO_MMAXIPRIO,
+ [55] = IPRIO_MMAXIPRIO,
+ [54] = IPRIO_MMAXIPRIO,
+ [53] = IPRIO_MMAXIPRIO,
+ [52] = IPRIO_MMAXIPRIO,
+ [51] = IPRIO_MMAXIPRIO,
+ [50] = IPRIO_MMAXIPRIO,
+ [49] = IPRIO_MMAXIPRIO,
+ [48] = IPRIO_MMAXIPRIO,
+
+ /* Custom interrupts 24 to 31 */
+ [31] = IPRIO_MMAXIPRIO,
+ [30] = IPRIO_MMAXIPRIO,
+ [29] = IPRIO_MMAXIPRIO,
+ [28] = IPRIO_MMAXIPRIO,
+ [27] = IPRIO_MMAXIPRIO,
+ [26] = IPRIO_MMAXIPRIO,
+ [25] = IPRIO_MMAXIPRIO,
+ [24] = IPRIO_MMAXIPRIO,
+
+ [47] = IPRIO_DEFAULT_UPPER,
+ [23] = IPRIO_DEFAULT_UPPER + 1,
+ [46] = IPRIO_DEFAULT_UPPER + 2,
+ [45] = IPRIO_DEFAULT_UPPER + 3,
+ [22] = IPRIO_DEFAULT_UPPER + 4,
+ [44] = IPRIO_DEFAULT_UPPER + 5,
+
+ [43] = IPRIO_DEFAULT_UPPER + 6,
+ [21] = IPRIO_DEFAULT_UPPER + 7,
+ [42] = IPRIO_DEFAULT_UPPER + 8,
+ [41] = IPRIO_DEFAULT_UPPER + 9,
+ [20] = IPRIO_DEFAULT_UPPER + 10,
+ [40] = IPRIO_DEFAULT_UPPER + 11,
+
+ [11] = IPRIO_DEFAULT_M,
+ [3] = IPRIO_DEFAULT_M + 1,
+ [7] = IPRIO_DEFAULT_M + 2,
+
+ [9] = IPRIO_DEFAULT_S,
+ [1] = IPRIO_DEFAULT_S + 1,
+ [5] = IPRIO_DEFAULT_S + 2,
+
+ [12] = IPRIO_DEFAULT_SGEXT,
+
+ [10] = IPRIO_DEFAULT_VS,
+ [2] = IPRIO_DEFAULT_VS + 1,
+ [6] = IPRIO_DEFAULT_VS + 2,
+
+ [39] = IPRIO_DEFAULT_LOWER,
+ [19] = IPRIO_DEFAULT_LOWER + 1,
+ [38] = IPRIO_DEFAULT_LOWER + 2,
+ [37] = IPRIO_DEFAULT_LOWER + 3,
+ [18] = IPRIO_DEFAULT_LOWER + 4,
+ [36] = IPRIO_DEFAULT_LOWER + 5,
+
+ [35] = IPRIO_DEFAULT_LOWER + 6,
+ [17] = IPRIO_DEFAULT_LOWER + 7,
+ [34] = IPRIO_DEFAULT_LOWER + 8,
+ [33] = IPRIO_DEFAULT_LOWER + 9,
+ [16] = IPRIO_DEFAULT_LOWER + 10,
+ [32] = IPRIO_DEFAULT_LOWER + 11,
+};
+
+uint8_t riscv_cpu_default_priority(int irq)
+{
+ if (irq < 0 || irq > 63) {
+ return IPRIO_MMAXIPRIO;
+ }
+
+ return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
+};
+
+int riscv_cpu_pending_to_irq(CPURISCVState *env,
+ int extirq, unsigned int extirq_def_prio,
+ uint64_t pending, uint8_t *iprio)
+{
+ int irq, best_irq = RISCV_EXCP_NONE;
+ unsigned int prio, best_prio = UINT_MAX;
+
+ if (!pending) {
+ return RISCV_EXCP_NONE;
+ }
+
+ irq = ctz64(pending);
+ if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
+ riscv_cpu_cfg(env)->ext_ssaia)) {
+ return irq;
+ }
+
+ pending = pending >> irq;
+ while (pending) {
+ prio = iprio[irq];
+ if (!prio) {
+ if (irq == extirq) {
+ prio = extirq_def_prio;
+ } else {
+ prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
+ 1 : IPRIO_MMAXIPRIO;
+ }
+ }
+ if ((pending & 0x1) && (prio <= best_prio)) {
+ best_irq = irq;
+ best_prio = prio;
+ }
+ irq++;
+ pending = pending >> 1;
+ }
+
+ return best_irq;
+}
+
+/*
+ * Doesn't report interrupts inserted using mvip from M-mode firmware or
+ * using hvip bits 13:63 from HS-mode. Those are returned in
+ * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending().
+ */
+uint64_t riscv_cpu_all_pending(CPURISCVState *env)
+{
+ uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
+ uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
+ uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0;
+
+ return (env->mip | vsgein | vstip) & env->mie;
+}
+
+int riscv_cpu_mirq_pending(CPURISCVState *env)
+{
+ uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
+ ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
+
+ return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
+ irqs, env->miprio);
+}
+
+int riscv_cpu_sirq_pending(CPURISCVState *env)
+{
+ uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & ~env->hideleg;
+ uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie;
+
+ return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
+ irqs | irqs_f, env->siprio);
+}
+
+int riscv_cpu_vsirq_pending(CPURISCVState *env)
+{
+ uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg;
+ uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie;
+ uint64_t vsbits;
+
+ /* Bring VS-level bits to correct position */
+ vsbits = irqs & VS_MODE_INTERRUPTS;
+ irqs &= ~VS_MODE_INTERRUPTS;
+ irqs |= vsbits >> 1;
+
+ return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
+ (irqs | irqs_f_vs), env->hviprio);
+}
+
bool riscv_cpu_has_work(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ae6b166d46..c45ee228f4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -638,6 +638,11 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env);
int riscv_cpu_mirq_pending(CPURISCVState *env);
int riscv_cpu_sirq_pending(CPURISCVState *env);
int riscv_cpu_vsirq_pending(CPURISCVState *env);
+int riscv_cpu_pending_to_irq(CPURISCVState *env,
+ int extirq, unsigned int extirq_def_prio,
+ uint64_t pending, uint8_t *iprio);
+
+
bool riscv_cpu_fp_enabled(CPURISCVState *env);
uint8_t riscv_cpu_get_geilen(CPURISCVState *env);
void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen);
diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
index 9293d61024..09ac1aeda9 100644
--- a/target/riscv/tcg/cpu_helper.c
+++ b/target/riscv/tcg/cpu_helper.c
@@ -330,193 +330,6 @@ int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
return 0;
}
-/*
- * Default priorities of local interrupts are defined in the
- * RISC-V Advanced Interrupt Architecture specification.
- *
- * ----------------------------------------------------------------
- * Default |
- * Priority | Major Interrupt Numbers
- * ----------------------------------------------------------------
- * Highest | 47, 23, 46, 45, 22, 44,
- * | 43, 21, 42, 41, 20, 40
- * |
- * | 11 (0b), 3 (03), 7 (07)
- * | 9 (09), 1 (01), 5 (05)
- * | 12 (0c)
- * | 10 (0a), 2 (02), 6 (06)
- * |
- * | 39, 19, 38, 37, 18, 36,
- * Lowest | 35, 17, 34, 33, 16, 32
- * ----------------------------------------------------------------
- */
-static const uint8_t default_iprio[64] = {
- /* Custom interrupts 48 to 63 */
- [63] = IPRIO_MMAXIPRIO,
- [62] = IPRIO_MMAXIPRIO,
- [61] = IPRIO_MMAXIPRIO,
- [60] = IPRIO_MMAXIPRIO,
- [59] = IPRIO_MMAXIPRIO,
- [58] = IPRIO_MMAXIPRIO,
- [57] = IPRIO_MMAXIPRIO,
- [56] = IPRIO_MMAXIPRIO,
- [55] = IPRIO_MMAXIPRIO,
- [54] = IPRIO_MMAXIPRIO,
- [53] = IPRIO_MMAXIPRIO,
- [52] = IPRIO_MMAXIPRIO,
- [51] = IPRIO_MMAXIPRIO,
- [50] = IPRIO_MMAXIPRIO,
- [49] = IPRIO_MMAXIPRIO,
- [48] = IPRIO_MMAXIPRIO,
-
- /* Custom interrupts 24 to 31 */
- [31] = IPRIO_MMAXIPRIO,
- [30] = IPRIO_MMAXIPRIO,
- [29] = IPRIO_MMAXIPRIO,
- [28] = IPRIO_MMAXIPRIO,
- [27] = IPRIO_MMAXIPRIO,
- [26] = IPRIO_MMAXIPRIO,
- [25] = IPRIO_MMAXIPRIO,
- [24] = IPRIO_MMAXIPRIO,
-
- [47] = IPRIO_DEFAULT_UPPER,
- [23] = IPRIO_DEFAULT_UPPER + 1,
- [46] = IPRIO_DEFAULT_UPPER + 2,
- [45] = IPRIO_DEFAULT_UPPER + 3,
- [22] = IPRIO_DEFAULT_UPPER + 4,
- [44] = IPRIO_DEFAULT_UPPER + 5,
-
- [43] = IPRIO_DEFAULT_UPPER + 6,
- [21] = IPRIO_DEFAULT_UPPER + 7,
- [42] = IPRIO_DEFAULT_UPPER + 8,
- [41] = IPRIO_DEFAULT_UPPER + 9,
- [20] = IPRIO_DEFAULT_UPPER + 10,
- [40] = IPRIO_DEFAULT_UPPER + 11,
-
- [11] = IPRIO_DEFAULT_M,
- [3] = IPRIO_DEFAULT_M + 1,
- [7] = IPRIO_DEFAULT_M + 2,
-
- [9] = IPRIO_DEFAULT_S,
- [1] = IPRIO_DEFAULT_S + 1,
- [5] = IPRIO_DEFAULT_S + 2,
-
- [12] = IPRIO_DEFAULT_SGEXT,
-
- [10] = IPRIO_DEFAULT_VS,
- [2] = IPRIO_DEFAULT_VS + 1,
- [6] = IPRIO_DEFAULT_VS + 2,
-
- [39] = IPRIO_DEFAULT_LOWER,
- [19] = IPRIO_DEFAULT_LOWER + 1,
- [38] = IPRIO_DEFAULT_LOWER + 2,
- [37] = IPRIO_DEFAULT_LOWER + 3,
- [18] = IPRIO_DEFAULT_LOWER + 4,
- [36] = IPRIO_DEFAULT_LOWER + 5,
-
- [35] = IPRIO_DEFAULT_LOWER + 6,
- [17] = IPRIO_DEFAULT_LOWER + 7,
- [34] = IPRIO_DEFAULT_LOWER + 8,
- [33] = IPRIO_DEFAULT_LOWER + 9,
- [16] = IPRIO_DEFAULT_LOWER + 10,
- [32] = IPRIO_DEFAULT_LOWER + 11,
-};
-
-uint8_t riscv_cpu_default_priority(int irq)
-{
- if (irq < 0 || irq > 63) {
- return IPRIO_MMAXIPRIO;
- }
-
- return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
-};
-
-static int riscv_cpu_pending_to_irq(CPURISCVState *env,
- int extirq, unsigned int extirq_def_prio,
- uint64_t pending, uint8_t *iprio)
-{
- int irq, best_irq = RISCV_EXCP_NONE;
- unsigned int prio, best_prio = UINT_MAX;
-
- if (!pending) {
- return RISCV_EXCP_NONE;
- }
-
- irq = ctz64(pending);
- if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
- riscv_cpu_cfg(env)->ext_ssaia)) {
- return irq;
- }
-
- pending = pending >> irq;
- while (pending) {
- prio = iprio[irq];
- if (!prio) {
- if (irq == extirq) {
- prio = extirq_def_prio;
- } else {
- prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
- 1 : IPRIO_MMAXIPRIO;
- }
- }
- if ((pending & 0x1) && (prio <= best_prio)) {
- best_irq = irq;
- best_prio = prio;
- }
- irq++;
- pending = pending >> 1;
- }
-
- return best_irq;
-}
-
-/*
- * Doesn't report interrupts inserted using mvip from M-mode firmware or
- * using hvip bits 13:63 from HS-mode. Those are returned in
- * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending().
- */
-uint64_t riscv_cpu_all_pending(CPURISCVState *env)
-{
- uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
- uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
- uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0;
-
- return (env->mip | vsgein | vstip) & env->mie;
-}
-
-int riscv_cpu_mirq_pending(CPURISCVState *env)
-{
- uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
- ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
-
- return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
- irqs, env->miprio);
-}
-
-int riscv_cpu_sirq_pending(CPURISCVState *env)
-{
- uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & ~env->hideleg;
- uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie;
-
- return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
- irqs | irqs_f, env->siprio);
-}
-
-int riscv_cpu_vsirq_pending(CPURISCVState *env)
-{
- uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg;
- uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie;
- uint64_t vsbits;
-
- /* Bring VS-level bits to correct position */
- vsbits = irqs & VS_MODE_INTERRUPTS;
- irqs &= ~VS_MODE_INTERRUPTS;
- irqs |= vsbits >> 1;
-
- return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
- (irqs | irqs_f_vs), env->hviprio);
-}
-
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
uint64_t irqs, pending, mie, hsie, vsie, irqs_f, irqs_f_vs;
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 13/24] target/riscv: move some irq helpers to cpu.c
2026-06-22 19:31 ` [PATCH 13/24] target/riscv: move some irq helpers " Daniel Henrique Barboza
@ 2026-06-22 21:07 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:07 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> riscv_cpu_has_work() uses a handful of irq pending functions from
> cpu_helper.c. There is a very high possibility that KVM doesn't need
> the current implermentation of has_work(), but the common accel code
> needs an implementation of this callback (see cpu_exec_class_post_init)
> otherwise the KVM driver won't initialize.
Indeed I also noticed that recently elsewhere.
> Move the relevant irq helpers to cpu.c to allow KVM to keep using the
> current has_work implementation, allowing --disable-tcg to work. We'll
> circle it back to evaluate a proper KVM implementation for it in a later
> date.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.c | 187 ++++++++++++++++++++++++++++++++++
> target/riscv/cpu.h | 5 +
> target/riscv/tcg/cpu_helper.c | 187 ----------------------------------
> 3 files changed, 192 insertions(+), 187 deletions(-)
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 14/24] target/riscv: move riscv_cpu_claim_interrupts to cpu.c
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (12 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 13/24] target/riscv: move some irq helpers " Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:08 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 15/24] target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state Daniel Henrique Barboza
` (10 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
The function is used by hw/intc/ files that KVM cares about like
riscv_aplic.c. Move it to cpu.c to be accessible for --disable-tcg
builds.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 14 ++++++++++++++
target/riscv/tcg/cpu_helper.c | 11 -----------
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 41646acfb5..2b1fbe4b0b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -566,6 +566,20 @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
return rval;
}
+#ifndef CONFIG_USER_ONLY
+/* Used by lots of folks in hw/intc */
+int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
+{
+ CPURISCVState *env = &cpu->env;
+ if (env->miclaim & interrupts) {
+ return -1;
+ } else {
+ env->miclaim |= interrupts;
+ return 0;
+ }
+}
+#endif
+
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
index 09ac1aeda9..f99fa636c7 100644
--- a/target/riscv/tcg/cpu_helper.c
+++ b/target/riscv/tcg/cpu_helper.c
@@ -572,17 +572,6 @@ void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level)
}
}
-int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
-{
- CPURISCVState *env = &cpu->env;
- if (env->miclaim & interrupts) {
- return -1;
- } else {
- env->miclaim |= interrupts;
- return 0;
- }
-}
-
void riscv_cpu_interrupt(CPURISCVState *env)
{
uint64_t gein, vsgein = 0, vstip = 0, irqf = 0;
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 14/24] target/riscv: move riscv_cpu_claim_interrupts to cpu.c
2026-06-22 19:31 ` [PATCH 14/24] target/riscv: move riscv_cpu_claim_interrupts " Daniel Henrique Barboza
@ 2026-06-22 21:08 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:08 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> The function is used by hw/intc/ files that KVM cares about like
> riscv_aplic.c. Move it to cpu.c to be accessible for --disable-tcg
> builds.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.c | 14 ++++++++++++++
> target/riscv/tcg/cpu_helper.c | 11 -----------
> 2 files changed, 14 insertions(+), 11 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 15/24] target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (13 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 14/24] target/riscv: move riscv_cpu_claim_interrupts " Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 16/24] target/riscv: gate riscv_cpu_update_mip with tcg_enabled() Daniel Henrique Barboza
` (9 subsequent siblings)
24 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
riscv_dump_csr() is a TCG only function but we'll have to implement it
at some capacity for KVM eventually, therefore put it under a CONFIG_TCG
ifdef while making a note that this function is unimplemented in KVM.
The csr_ops array is also TCG specific, thus the for loop inside
dump_state that iterates it is also TCG only business.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2b1fbe4b0b..9c1b55c3c1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -605,8 +605,10 @@ char *riscv_cpu_get_name(RISCVCPU *cpu)
return cpu_model_from_type(typename);
}
+/* Note: this function needs a KVM implementation. */
static void riscv_dump_csr(CPURISCVState *env, int csrno, FILE *f)
{
+#ifdef CONFIG_TCG
target_ulong val = 0;
RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
@@ -618,6 +620,7 @@ static void riscv_dump_csr(CPURISCVState *env, int csrno, FILE *f)
qemu_fprintf(f, " %-13s " TARGET_FMT_lx "\n",
csr_ops[csrno].name, val);
}
+#endif
}
#if !defined(CONFIG_USER_ONLY)
@@ -655,7 +658,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
#endif
qemu_fprintf(f, " %-13s %" PRIx64 "\n", "pc", env->pc);
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {
int csrno = i;
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 16/24] target/riscv: gate riscv_cpu_update_mip with tcg_enabled()
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (14 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 15/24] target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:12 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 17/24] target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold() Daniel Henrique Barboza
` (8 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
riscv_cpu_update_mip() is a TCG only call. Its KVM equivalent is
kvm_riscv_set_irq(). cpu.c gates the KVM only function with a
kvm_enabled() check, making it unavailable for TCG only builds. We need
to do the same for riscv_cpu_update_mip() otherwise a KVM only build
will fail because it doesn't know what this function is.
Use tcg_enabled() for the couple of riscv_cpu_update_mip() calls we have
unguarded in cpu.c.
We have way more calls to deal with in time_helper.c which isn't using
kvm_riscv_set_irq() at all. For this file create a riscv_set_irq() local
helper that will choose whether to use the KVM or TCG API.
The reason we're going through all this hassle in time_helper.c is
because hw/int/riscv_aclint.c uses it, and if we don't do something
about we won't have riscv_aclint working for KVM. Whether this is a
real problem or not and we should remove aclint support for KVM is
question for another day.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 19 ++++++++++++++-----
target/riscv/time_helper.c | 33 +++++++++++++++++++++++++--------
2 files changed, 39 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9c1b55c3c1..8aac18ea5d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1336,14 +1336,18 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
case IRQ_M_EXT:
if (kvm_enabled()) {
kvm_riscv_set_irq(cpu, irq, level);
- } else {
+ }
+
+ if (tcg_enabled()) {
riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
}
break;
case IRQ_S_EXT:
if (kvm_enabled()) {
kvm_riscv_set_irq(cpu, irq, level);
- } else {
+ }
+
+ if (tcg_enabled()) {
env->external_seip = level;
riscv_cpu_update_mip(env, 1 << irq,
BOOL_TO_MASK(level | env->software_seip));
@@ -1370,9 +1374,14 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
env->hgeip |= 1ULL << irq;
}
- /* Update mip.SGEIP bit */
- riscv_cpu_update_mip(env, MIP_SGEIP,
- BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
+ if (kvm_enabled()) {
+ kvm_riscv_set_irq(cpu, irq, level);
+ }
+ if (tcg_enabled()) {
+ /* Update mip.SGEIP bit */
+ riscv_cpu_update_mip(env, MIP_SGEIP,
+ BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
+ }
} else {
g_assert_not_reached();
}
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index 400e917354..2679dbba6c 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -21,19 +21,34 @@
#include "cpu_bits.h"
#include "time_helper.h"
#include "hw/intc/riscv_aclint.h"
+#include "kvm/kvm_riscv.h"
+#include "system/kvm.h"
+#include "system/tcg.h"
+
+static void riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+ if (kvm_enabled()) {
+ kvm_riscv_set_irq(cpu, irq, level);
+ }
+
+ if (tcg_enabled()) {
+ riscv_cpu_update_mip(&cpu->env, irq, level);
+ }
+}
+
static void riscv_vstimer_cb(void *opaque)
{
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
env->vstime_irq = 1;
- riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
+ riscv_set_irq(cpu, 0, BOOL_TO_MASK(1));
}
static void riscv_stimer_cb(void *opaque)
{
RISCVCPU *cpu = opaque;
- riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1));
+ riscv_set_irq(cpu, MIP_STIP, BOOL_TO_MASK(1));
}
/*
@@ -48,6 +63,7 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
uint32_t timebase_freq;
uint64_t rtc_r;
+ RISCVCPU *cpu;
if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn ||
!env->rdtime_fn_arg || !get_field(env->menvcfg, MENVCFG_STCE)) {
@@ -63,6 +79,7 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
timebase_freq = mtimer->timebase_freq;
rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
+ cpu = env_archcpu(env);
if (timecmp <= rtc_r) {
/*
@@ -71,9 +88,9 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
*/
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 1;
- riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
+ riscv_set_irq(cpu, 0, BOOL_TO_MASK(1));
} else {
- riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1));
+ riscv_set_irq(cpu, MIP_STIP, BOOL_TO_MASK(1));
}
return;
}
@@ -81,9 +98,9 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
/* Clear the [VS|S]TIP bit in mip */
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 0;
- riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0));
+ riscv_set_irq(cpu, 0, BOOL_TO_MASK(0));
} else {
- riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0));
+ riscv_set_irq(cpu, timer_irq, BOOL_TO_MASK(0));
}
/*
@@ -151,7 +168,7 @@ static void riscv_timer_disable_timecmp(CPURISCVState *env, QEMUTimer *timer,
{
/* Disable S-mode Timer IRQ and HW-based STIP */
if ((timer_irq == MIP_STIP) && !get_field(env->menvcfg, MENVCFG_STCE)) {
- riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0));
+ riscv_set_irq(env_archcpu(env), timer_irq, BOOL_TO_MASK(0));
timer_del(timer);
return;
}
@@ -161,7 +178,7 @@ static void riscv_timer_disable_timecmp(CPURISCVState *env, QEMUTimer *timer,
(!get_field(env->menvcfg, MENVCFG_STCE) ||
!get_field(env->henvcfg, HENVCFG_STCE))) {
env->vstime_irq = 0;
- riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0));
+ riscv_set_irq(env_archcpu(env), 0, BOOL_TO_MASK(0));
timer_del(timer);
return;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 16/24] target/riscv: gate riscv_cpu_update_mip with tcg_enabled()
2026-06-22 19:31 ` [PATCH 16/24] target/riscv: gate riscv_cpu_update_mip with tcg_enabled() Daniel Henrique Barboza
@ 2026-06-22 21:12 ` Philippe Mathieu-Daudé
2026-06-23 20:40 ` Daniel Henrique Barboza
0 siblings, 1 reply; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:12 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> riscv_cpu_update_mip() is a TCG only call. Its KVM equivalent is
> kvm_riscv_set_irq(). cpu.c gates the KVM only function with a
> kvm_enabled() check, making it unavailable for TCG only builds. We need
> to do the same for riscv_cpu_update_mip() otherwise a KVM only build
> will fail because it doesn't know what this function is.
>
> Use tcg_enabled() for the couple of riscv_cpu_update_mip() calls we have
> unguarded in cpu.c.
>
> We have way more calls to deal with in time_helper.c which isn't using
> kvm_riscv_set_irq() at all. For this file create a riscv_set_irq() local
> helper that will choose whether to use the KVM or TCG API.
>
> The reason we're going through all this hassle in time_helper.c is
> because hw/int/riscv_aclint.c uses it, and if we don't do something
> about we won't have riscv_aclint working for KVM. Whether this is a
> real problem or not and we should remove aclint support for KVM is
> question for another day.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.c | 19 ++++++++++++++-----
> target/riscv/time_helper.c | 33 +++++++++++++++++++++++++--------
> 2 files changed, 39 insertions(+), 13 deletions(-)
> diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
> index 400e917354..2679dbba6c 100644
> --- a/target/riscv/time_helper.c
> +++ b/target/riscv/time_helper.c
> @@ -21,19 +21,34 @@
> #include "cpu_bits.h"
> #include "time_helper.h"
> #include "hw/intc/riscv_aclint.h"
> +#include "kvm/kvm_riscv.h"
> +#include "system/kvm.h"
> +#include "system/tcg.h"
> +
> +static void riscv_set_irq(RISCVCPU *cpu, int irq, int level)
riscv_accel_set_irq? Regardless,
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> +{
> + if (kvm_enabled()) {
> + kvm_riscv_set_irq(cpu, irq, level);
> + }
> +
> + if (tcg_enabled()) {
> + riscv_cpu_update_mip(&cpu->env, irq, level);
> + }
> +}
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 16/24] target/riscv: gate riscv_cpu_update_mip with tcg_enabled()
2026-06-22 21:12 ` Philippe Mathieu-Daudé
@ 2026-06-23 20:40 ` Daniel Henrique Barboza
0 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-23 20:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 6/22/2026 6:12 PM, Philippe Mathieu-Daudé wrote:
> On 22/6/26 21:31, Daniel Henrique Barboza wrote:
>> riscv_cpu_update_mip() is a TCG only call. Its KVM equivalent is
>> kvm_riscv_set_irq(). cpu.c gates the KVM only function with a
>> kvm_enabled() check, making it unavailable for TCG only builds. We need
>> to do the same for riscv_cpu_update_mip() otherwise a KVM only build
>> will fail because it doesn't know what this function is.
>>
>> Use tcg_enabled() for the couple of riscv_cpu_update_mip() calls we have
>> unguarded in cpu.c.
>>
>> We have way more calls to deal with in time_helper.c which isn't using
>> kvm_riscv_set_irq() at all. For this file create a riscv_set_irq() local
>> helper that will choose whether to use the KVM or TCG API.
>>
>> The reason we're going through all this hassle in time_helper.c is
>> because hw/int/riscv_aclint.c uses it, and if we don't do something
>> about we won't have riscv_aclint working for KVM. Whether this is a
>> real problem or not and we should remove aclint support for KVM is
>> question for another day.
>>
>> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
>> ---
>> target/riscv/cpu.c | 19 ++++++++++++++-----
>> target/riscv/time_helper.c | 33 +++++++++++++++++++++++++--------
>> 2 files changed, 39 insertions(+), 13 deletions(-)
>
>
>> diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
>> index 400e917354..2679dbba6c 100644
>> --- a/target/riscv/time_helper.c
>> +++ b/target/riscv/time_helper.c
>> @@ -21,19 +21,34 @@
>> #include "cpu_bits.h"
>> #include "time_helper.h"
>> #include "hw/intc/riscv_aclint.h"
>> +#include "kvm/kvm_riscv.h"
>> +#include "system/kvm.h"
>> +#include "system/tcg.h"
>> +
>> +static void riscv_set_irq(RISCVCPU *cpu, int irq, int level)
>
> riscv_accel_set_irq? Regardless,
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>
Renamed. thx!
>> +{
>> + if (kvm_enabled()) {
>> + kvm_riscv_set_irq(cpu, irq, level);
>> + }
>> +
>> + if (tcg_enabled()) {
>> + riscv_cpu_update_mip(&cpu->env, irq, level);
>> + }
>> +}
>
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 17/24] target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold()
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (15 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 16/24] target/riscv: gate riscv_cpu_update_mip with tcg_enabled() Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:13 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 18/24] hw/riscv/riscv_hart.c isolate tcg only bits Daniel Henrique Barboza
` (7 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
We have a lot of TCG only initialization in the common cpu_reset_hold
callback that prevents --disable-tcg to work.
Put a CONFIG_TCG ifdef around those bits to make the build work.
Eventually we'll create a TCG specific reset function in tcg-cpu.c but
for now this suffices.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8aac18ea5d..8a330487c5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -958,10 +958,6 @@ bool riscv_cpu_has_work(CPUState *cs)
static void riscv_cpu_reset_hold(Object *obj, ResetType type)
{
-#ifndef CONFIG_USER_ONLY
- uint8_t iprio;
- int i, irq, rdzero;
-#endif
CPUState *cs = CPU(obj);
RISCVCPU *cpu = RISCV_CPU(cs);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
@@ -1013,6 +1009,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
MENVCFG_ADUE : 0);
env->henvcfg = 0;
+#ifdef CONFIG_TCG
+ uint8_t iprio;
+ int i, irq, rdzero;
+
/* Initialized default priorities of local interrupts. */
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
iprio = riscv_cpu_default_priority(i);
@@ -1050,11 +1050,12 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
}
pmp_unlock_entries(env);
+#endif /* ifdef CONFIG_TCG */
#else
env->priv = PRV_U;
env->senvcfg = 0;
env->menvcfg = 0;
-#endif
+#endif /* ifndef CONFIG_USER_ONLY */
/* on reset elp is clear */
env->elp = false;
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 17/24] target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold()
2026-06-22 19:31 ` [PATCH 17/24] target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold() Daniel Henrique Barboza
@ 2026-06-22 21:13 ` Philippe Mathieu-Daudé
2026-06-24 11:19 ` Daniel Henrique Barboza
0 siblings, 1 reply; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:13 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> We have a lot of TCG only initialization in the common cpu_reset_hold
> callback that prevents --disable-tcg to work.
>
> Put a CONFIG_TCG ifdef around those bits to make the build work.
> Eventually we'll create a TCG specific reset function in tcg-cpu.c but
> for now this suffices.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> target/riscv/cpu.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
> @@ -1013,6 +1009,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
> MENVCFG_ADUE : 0);
> env->henvcfg = 0;
>
> +#ifdef CONFIG_TCG
> + uint8_t iprio;
> + int i, irq, rdzero;
> +
> /* Initialized default priorities of local interrupts. */
> for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
> iprio = riscv_cpu_default_priority(i);
> @@ -1050,11 +1050,12 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
> }
>
> pmp_unlock_entries(env);
> +#endif /* ifdef CONFIG_TCG */
> #else
> env->priv = PRV_U;
> env->senvcfg = 0;
> env->menvcfg = 0;
> -#endif
> +#endif /* ifndef CONFIG_USER_ONLY */
/* !CONFIG_USER_ONLY */
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 17/24] target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold()
2026-06-22 21:13 ` Philippe Mathieu-Daudé
@ 2026-06-24 11:19 ` Daniel Henrique Barboza
0 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-24 11:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 6/22/2026 6:13 PM, Philippe Mathieu-Daudé wrote:
> On 22/6/26 21:31, Daniel Henrique Barboza wrote:
>> We have a lot of TCG only initialization in the common cpu_reset_hold
>> callback that prevents --disable-tcg to work.
>>
>> Put a CONFIG_TCG ifdef around those bits to make the build work.
>> Eventually we'll create a TCG specific reset function in tcg-cpu.c but
>> for now this suffices.
>>
>> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
>> ---
>> target/riscv/cpu.c | 11 ++++++-----
>> 1 file changed, 6 insertions(+), 5 deletions(-)
>
>
>> @@ -1013,6 +1009,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>> MENVCFG_ADUE : 0);
>> env->henvcfg = 0;
>> +#ifdef CONFIG_TCG
>> + uint8_t iprio;
>> + int i, irq, rdzero;
>> +
>> /* Initialized default priorities of local interrupts. */
>> for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
>> iprio = riscv_cpu_default_priority(i);
>> @@ -1050,11 +1050,12 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>> }
>> pmp_unlock_entries(env);
>> +#endif /* ifdef CONFIG_TCG */
>> #else
>> env->priv = PRV_U;
>> env->senvcfg = 0;
>> env->menvcfg = 0;
>> -#endif
>> +#endif /* ifndef CONFIG_USER_ONLY */
>
> /* !CONFIG_USER_ONLY */
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Phil I forgot about this ack. My bad :(
I'll make sure to add update it in v3. Cheers,
Daniel
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 18/24] hw/riscv/riscv_hart.c isolate tcg only bits
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (16 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 17/24] target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold() Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:15 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 19/24] target/riscv/gdbstub.c: isolate TCG only checks Daniel Henrique Barboza
` (6 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
riscv_cpu_register_csr_qtest_callback(), vcsr_call() and
csr_qtest_callback() are all TCG only and are not available in
--disable-tcg builds.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
hw/riscv/riscv_hart.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index d1c7188369..28925aee59 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -61,7 +61,7 @@ static void riscv_harts_cpu_reset(void *opaque)
cpu_reset(CPU(cpu));
}
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val)
{
RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num));
@@ -151,7 +151,7 @@ static void riscv_harts_realize(DeviceState *dev, Error **errp)
s->harts = g_new0(RISCVCPU, s->num_harts);
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
riscv_cpu_register_csr_qtest_callback();
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 18/24] hw/riscv/riscv_hart.c isolate tcg only bits
2026-06-22 19:31 ` [PATCH 18/24] hw/riscv/riscv_hart.c isolate tcg only bits Daniel Henrique Barboza
@ 2026-06-22 21:15 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:15 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> riscv_cpu_register_csr_qtest_callback(), vcsr_call() and
> csr_qtest_callback() are all TCG only and are not available in
> --disable-tcg builds.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> hw/riscv/riscv_hart.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> index d1c7188369..28925aee59 100644
> --- a/hw/riscv/riscv_hart.c
> +++ b/hw/riscv/riscv_hart.c
> @@ -61,7 +61,7 @@ static void riscv_harts_cpu_reset(void *opaque)
> cpu_reset(CPU(cpu));
> }
>
> -#ifndef CONFIG_USER_ONLY
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val)
> {
> RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num));
> @@ -151,7 +151,7 @@ static void riscv_harts_realize(DeviceState *dev, Error **errp)
>
> s->harts = g_new0(RISCVCPU, s->num_harts);
>
> -#ifndef CONFIG_USER_ONLY
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
Pre-existing, if (qtest_enabled())?
> riscv_cpu_register_csr_qtest_callback();
> #endif
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 19/24] target/riscv/gdbstub.c: isolate TCG only checks
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (17 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 18/24] hw/riscv/riscv_hart.c isolate tcg only bits Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 20/24] target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint Daniel Henrique Barboza
` (5 subsequent siblings)
24 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
The following functions are TCG only and are broken, if they were ever
usable in the first place, with KVM:
- riscv_gdb_(get|se)t_csr
- riscv_gdb_(get|set)_virtual
- riscv_gen_dynamic_csr_feature
Gate everything with TCG enabled to at least get them out of the way to
enable --disable-tcg.
As a note for the future: other archs have distincts gdbstub files for
each accelerator. There's a strong case for RISC-V to do the same.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/gdbstub.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index f0a5e0d86f..9abbf5bcdf 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -164,6 +164,7 @@ static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n)
return 0;
}
+#ifdef CONFIG_TCG
static int riscv_gdb_get_csr(CPUState *cs, GByteArray *buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
@@ -294,6 +295,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
return &cpu->dyn_csr_feature;
}
+#endif /* CONFIG_TCG */
static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
{
@@ -336,7 +338,6 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
- RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
if (env->misa_ext & RVD) {
@@ -351,6 +352,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
riscv_gdb_set_vector,
ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs));
}
+
+#ifdef CONFIG_TCG
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
+
switch (mcc->def->misa_mxl_max) {
case MXL_RV32:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
@@ -371,4 +376,5 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs));
}
+#endif
}
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 20/24] target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (18 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 19/24] target/riscv/gdbstub.c: isolate TCG only checks Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:16 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 21/24] target/riscv/tcg: remove unused riscv_cpu_get_geilen() Daniel Henrique Barboza
` (4 subsequent siblings)
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
There's no need for it to be in cpu_helper since riscv_aclint is the
only caller.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
hw/intc/riscv_aclint.c | 8 ++++++++
target/riscv/cpu.h | 2 --
target/riscv/tcg/cpu_helper.c | 7 -------
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index e27e5fb394..361a8d1bcb 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -40,6 +40,14 @@ typedef struct riscv_aclint_mtimer_callback {
int num;
} riscv_aclint_mtimer_callback;
+static void riscv_cpu_set_rdtime_fn(CPURISCVState *env,
+ uint64_t (*fn)(void *),
+ void *arg)
+{
+ env->rdtime_fn = fn;
+ env->rdtime_fn_arg = arg;
+}
+
static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq)
{
return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c45ee228f4..9ec86069a6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -679,8 +679,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level);
void riscv_cpu_interrupt(CPURISCVState *env);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
- void *arg);
void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t priv,
aia_ireg_rmw_fn rmw_fn,
void *rmw_fn_arg);
diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
index f99fa636c7..d0d74c3597 100644
--- a/target/riscv/tcg/cpu_helper.c
+++ b/target/riscv/tcg/cpu_helper.c
@@ -612,13 +612,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value)
return old;
}
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
- void *arg)
-{
- env->rdtime_fn = fn;
- env->rdtime_fn_arg = arg;
-}
-
void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t priv,
aia_ireg_rmw_fn rmw_fn,
void *rmw_fn_arg)
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 20/24] target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint
2026-06-22 19:31 ` [PATCH 20/24] target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint Daniel Henrique Barboza
@ 2026-06-22 21:16 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:16 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> There's no need for it to be in cpu_helper since riscv_aclint is the
> only caller.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> hw/intc/riscv_aclint.c | 8 ++++++++
> target/riscv/cpu.h | 2 --
> target/riscv/tcg/cpu_helper.c | 7 -------
> 3 files changed, 8 insertions(+), 9 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 21/24] target/riscv/tcg: remove unused riscv_cpu_get_geilen()
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (19 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 20/24] target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 22/24] target/riscv: move riscv_cpu_set_geilen() to riscv-imsic Daniel Henrique Barboza
` (3 subsequent siblings)
24 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
No one uses it.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu.h | 1 -
target/riscv/tcg/cpu_helper.c | 9 ---------
2 files changed, 10 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9ec86069a6..aa67999005 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -644,7 +644,6 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env,
bool riscv_cpu_fp_enabled(CPURISCVState *env);
-uint8_t riscv_cpu_get_geilen(CPURISCVState *env);
void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen);
bool riscv_cpu_vector_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
index d0d74c3597..1f13d257f6 100644
--- a/target/riscv/tcg/cpu_helper.c
+++ b/target/riscv/tcg/cpu_helper.c
@@ -526,15 +526,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
}
}
-uint8_t riscv_cpu_get_geilen(CPURISCVState *env)
-{
- if (!riscv_has_ext(env, RVH)) {
- return 0;
- }
-
- return env->geilen;
-}
-
void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen)
{
if (!riscv_has_ext(env, RVH)) {
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 22/24] target/riscv: move riscv_cpu_set_geilen() to riscv-imsic
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (20 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 21/24] target/riscv/tcg: remove unused riscv_cpu_get_geilen() Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 19:31 ` [PATCH 23/24] target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic Daniel Henrique Barboza
` (2 subsequent siblings)
24 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
riscv_imsic.c is the only caller. Having it sitting in the TCG only
cpu_helper.c gets in the way of --disable-tcg for no good reason.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
hw/intc/riscv_imsic.c | 13 +++++++++++++
target/riscv/cpu.h | 1 -
target/riscv/tcg/cpu_helper.c | 13 -------------
3 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index 7e5b5349ba..ebb55191c7 100644
--- a/hw/intc/riscv_imsic.c
+++ b/hw/intc/riscv_imsic.c
@@ -46,6 +46,19 @@
#define IMSIC_EISTATE_ENPEND (IMSIC_EISTATE_ENABLED | \
IMSIC_EISTATE_PENDING)
+static void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ if (geilen > (TARGET_LONG_BITS - 1)) {
+ return;
+ }
+
+ env->geilen = geilen;
+}
+
static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page)
{
uint32_t i, max_irq, base;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index aa67999005..65d77842b2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -644,7 +644,6 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env,
bool riscv_cpu_fp_enabled(CPURISCVState *env);
-void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen);
bool riscv_cpu_vector_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
int riscv_env_mmu_index(CPURISCVState *env, bool ifetch);
diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
index 1f13d257f6..3a4e86f6d6 100644
--- a/target/riscv/tcg/cpu_helper.c
+++ b/target/riscv/tcg/cpu_helper.c
@@ -526,19 +526,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
}
}
-void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen)
-{
- if (!riscv_has_ext(env, RVH)) {
- return;
- }
-
- if (geilen > (TARGET_LONG_BITS - 1)) {
- return;
- }
-
- env->geilen = geilen;
-}
-
void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level)
{
CPURISCVState *env = &cpu->env;
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 23/24] target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (21 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 22/24] target/riscv: move riscv_cpu_set_geilen() to riscv-imsic Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 21:17 ` Philippe Mathieu-Daudé
2026-06-22 19:31 ` [PATCH 24/24] gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job Daniel Henrique Barboza
2026-06-22 20:52 ` [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Pierrick Bouvier
24 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier,
Daniel Henrique Barboza, Palmer Dabbelt
riscv_imsic.c is the only caller. Having it sitting in the TCG only
cpu_helper.c gets in the way of --disable-tcg for no good reason.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
hw/intc/riscv_imsic.c | 11 +++++++++++
target/riscv/cpu.h | 3 ---
target/riscv/tcg/cpu_helper.c | 10 ----------
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index ebb55191c7..d6b46cdca2 100644
--- a/hw/intc/riscv_imsic.c
+++ b/hw/intc/riscv_imsic.c
@@ -376,6 +376,17 @@ static void riscv_imsic_reset_enter(Object *obj, ResetType type)
}
}
+static void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env,
+ privilege_mode_t priv,
+ aia_ireg_rmw_fn rmw_fn,
+ void *rmw_fn_arg)
+{
+ if (priv <= PRV_M) {
+ env->aia_ireg_rmw_cb[priv] = rmw_fn;
+ env->aia_ireg_rmw_cb_arg[priv] = rmw_fn_arg;
+ }
+}
+
static void riscv_imsic_realize(DeviceState *dev, Error **errp)
{
RISCVIMSICState *imsic = RISCV_IMSIC(dev);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 65d77842b2..e0836c986e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -677,9 +677,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level);
void riscv_cpu_interrupt(CPURISCVState *env);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
-void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t priv,
- aia_ireg_rmw_fn rmw_fn,
- void *rmw_fn_arg);
RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
index 3a4e86f6d6..2ec1c3f079 100644
--- a/target/riscv/tcg/cpu_helper.c
+++ b/target/riscv/tcg/cpu_helper.c
@@ -590,16 +590,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value)
return old;
}
-void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t priv,
- aia_ireg_rmw_fn rmw_fn,
- void *rmw_fn_arg)
-{
- if (priv <= PRV_M) {
- env->aia_ireg_rmw_cb[priv] = rmw_fn;
- env->aia_ireg_rmw_cb_arg[priv] = rmw_fn_arg;
- }
-}
-
static void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask,
bool virt)
{
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 23/24] target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic
2026-06-22 19:31 ` [PATCH 23/24] target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic Daniel Henrique Barboza
@ 2026-06-22 21:17 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:17 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, pierrick.bouvier, Palmer Dabbelt
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
> riscv_imsic.c is the only caller. Having it sitting in the TCG only
> cpu_helper.c gets in the way of --disable-tcg for no good reason.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
> hw/intc/riscv_imsic.c | 11 +++++++++++
> target/riscv/cpu.h | 3 ---
> target/riscv/tcg/cpu_helper.c | 10 ----------
> 3 files changed, 11 insertions(+), 13 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 24/24] gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (22 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 23/24] target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic Daniel Henrique Barboza
@ 2026-06-22 19:31 ` Daniel Henrique Barboza
2026-06-22 20:52 ` [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Pierrick Bouvier
24 siblings, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 19:31 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd, pierrick.bouvier, Zephyr Li,
Daniel Henrique Barboza, Alex Bennée
From: Zephyr Li <fritchleybohrer@gmail.com>
Add CI coverage for a riscv64 --disable-tcg cross build. This ensures that
RISC-V no-TCG/KVM-only builds keep working and prevents TCG-only code from
being accidentally pulled into common RISC-V sources again.
The cross_accel_build_job template enables KVM by default via
--enable-${ACCEL:-kvm}, so the extra options only need to disable TCG.
Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
.gitlab-ci.d/crossbuilds.yml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
index eaeeb533ce..a823aaaa21 100644
--- a/.gitlab-ci.d/crossbuilds.yml
+++ b/.gitlab-ci.d/crossbuilds.yml
@@ -59,6 +59,14 @@ cross-riscv64-user:
variables:
IMAGE: debian-riscv64-cross
+cross-riscv64-kvm-only:
+ extends: .cross_accel_build_job
+ needs:
+ - job: riscv64-debian-cross-container
+ variables:
+ IMAGE: debian-riscv64-cross
+ EXTRA_CONFIGURE_OPTS: --disable-tcg --without-default-features
+
cross-s390x-system:
extends: .cross_system_build_job
needs:
--
2.43.0
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-22 19:31 [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Daniel Henrique Barboza
` (23 preceding siblings ...)
2026-06-22 19:31 ` [PATCH 24/24] gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job Daniel Henrique Barboza
@ 2026-06-22 20:52 ` Pierrick Bouvier
2026-06-22 21:04 ` Daniel Henrique Barboza
2026-06-22 21:23 ` Philippe Mathieu-Daudé
24 siblings, 2 replies; 71+ messages in thread
From: Pierrick Bouvier @ 2026-06-22 20:52 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd
On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
> Hello,
>
> This series looks scary but it's mostly trivial and mechanical work.
>
> It is yet another attempt at fixing --disable-tcg. We have a recent
> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
> Phil's work didn't get merged and it's now too hard to rebase and
> revive, the most recent attempt got misled into the 'what is common code
> between TCG and KVM' dungeon.
>
> After reviewing [1] I went ahead and look what other targets were doing
> w.r.t their directory structure and comparing to RISC-V. In our case we
> have a log going on in target/riscv:
>
> $ ls target/riscv
> Kconfig cpu_cfg.h fpu_helper.c machine.c sbi_ecall_interface.h vector_internals.c
> XVentanaCondOps.decode cpu_cfg_fields.h.inc gdbstub.c meson.build tcg vector_internals.h
> arch_dump.c cpu_helper.c helper.h mips_csr.c th_csr.c xlrbr.decode
> bitmanip_helper.c cpu_user.h insn16.decode monitor.c time_helper.c xmips.decode
> common-semi-target.c cpu_vendorid.h insn32.decode op_helper.c time_helper.h xthead.decode
> cpu-param.h crypto_helper.c insn_trans pmp.c trace-events zce_helper.c
> cpu-qom.h csr.c instmap.h pmp.h trace.h
> cpu.c csr.h internals.h pmu.c translate.c
> cpu.h debug.c kvm pmu.h vcrypto_helper.c
> cpu_bits.h debug.h m128_helper.c riscv-qmp-cmds.c vector_helper.c
>
>
> It is non-trivial to realize that most of this stuff is TCG specific.
> Meanwhile our 'tcg' subdir is mostly empty:
>
> $ ls target/riscv/tcg
> meson.build tcg-cpu.c tcg-cpu.h
>
> If we compare it with other targets, let's say loongarch:
>
> $ ls target/loongarch/
> Kconfig cpu-csr.h cpu-qom.h cpu_helper.c disas.c insns.decode loongarch-qmp-cmds.c tcg translate.h
> README cpu-mmu.h cpu.c csr.c gdbstub.c internals.h machine.c trace-events vec.h
> arch_dump.c cpu-param.h cpu.h csr.h helper.h kvm meson.build trace.h
> $
> $ ls target/loongarch/tcg
> constant_timer.c fpu_helper.c insn_trans meson.build tcg_cpu.c tlb_helper.c vec_helper.c
> csr_helper.c helper.h iocsr_helper.c op_helper.c tcg_loongarch.h translate.c
>
> It is straightforward to see which files are TCG exclusive and which
> files are common to all accels.
>
> And this is what we did here. The patches goes mostly as follows:
>
> - move stuff to 'tcg' subdir. Most stuff is straighforward and is
> manageable with a single patch. Other things required some logic to
> go to either cpu.c or tcg-cpu;
> - move TCG stuff to tcg-cpu.c;
> - move common accel stuff to cpu.c. Usually from cpu_helper.c;
> - filter TCG specific code in cpu.c and other files;
> - trivial/assorted fixes in misc files that were needed to make
> --disable-tcg work.
>
> Patch 24 is taken from Zephyr Li to enable the CI for --disable-tcg.
> Hopefully we won't break it anytime soon.
>
> After this series we have --disable-tcg working and the following dir
> structure:
>
> $ ls target/riscv
> Kconfig cpu.c cpu_vendorid.h internals.h sbi_ecall_interface.h xlrbr.decode
> XVentanaCondOps.decode cpu.h gdbstub.c kvm tcg xmips.decode
> arch_dump.c cpu_bits.h helper.h machine.c time_helper.c xthead.decode
> common-semi-target.c cpu_cfg.h insn16.decode meson.build time_helper.h
> cpu-param.h cpu_cfg_fields.h.inc insn32.decode monitor.c trace-events
> cpu-qom.h cpu_user.h instmap.h riscv-qmp-cmds.c trace.h
> $
> $ ls target/riscv/tcg
> bitmanip_helper.c csr.h insn_trans op_helper.c pmu.h translate.c vector_internals.h
> cpu_helper.c debug.c m128_helper.c pmp.c tcg-cpu.c vcrypto_helper.c zce_helper.c
> crypto_helper.c debug.h meson.build pmp.h tcg-cpu.h vector_helper.c
> csr.c fpu_helper.c mips_csr.c pmu.c th_csr.c vector_internals.c
>
>
> [1] https://lore.kernel.org/qemu-devel/20260602091753.3209261-1-fritchleybohrer@gmail.com/
> [2] https://lore.kernel.org/qemu-devel/20230711121453.59138-1-philmd@linaro.org/
>
>
> Daniel Henrique Barboza (22):
> target/riscv: move TCG only files to tcg subdir
> target/riscv/machine.c: do not migrate pmp state with kvm
> target/riscv: move pmp files to tcg subdir
> target/riscv: make some riscv_sysemu_ops TCG only
> target/riscv: move pmu.h to tcg subdir
> target/riscv: move debug.h to tcg subdir
> target/riscv: remove csr.h from kvm-cpu.c
> target/riscv: move csr.h to tcg subdir
> target/riscv: move custom_csrs logic to tcg-cpu.c
> target/riscv: move riscv_cpu_set_nmi() to tcg-cpu.c
> target/riscv: move valid_vm_* satp arrays to cpu.c
> target/riscv: move some irq helpers to cpu.c
> target/riscv: move riscv_cpu_claim_interrupts to cpu.c
> target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state
> target/riscv: gate riscv_cpu_update_mip with tcg_enabled()
> target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold()
> hw/riscv/riscv_hart.c isolate tcg only bits
> target/riscv/gdbstub.c: isolate TCG only checks
> target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint
> target/riscv/tcg: remove unused riscv_cpu_get_geilen()
> target/riscv: move riscv_cpu_set_geilen() to riscv-imsic
> target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic
>
> Zephyr Li (2):
> target/riscv: Remove unused tcg/tcg.h include
> gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job
>
> .gitlab-ci.d/crossbuilds.yml | 8 +
> hw/intc/riscv_aclint.c | 8 +
> hw/intc/riscv_imsic.c | 24 ++
> hw/riscv/fdt-common.c | 52 +++
> hw/riscv/riscv_hart.c | 4 +-
> hw/riscv/virt.c | 1 -
> include/hw/riscv/fdt-common.h | 1 +
> target/riscv/cpu.c | 316 +++++++++++++++---
> target/riscv/cpu.h | 19 +-
> target/riscv/gdbstub.c | 10 +-
> target/riscv/kvm/kvm-cpu.c | 1 -
> target/riscv/machine.c | 15 +-
> target/riscv/meson.build | 17 -
> target/riscv/monitor.c | 4 +-
> target/riscv/riscv-qmp-cmds.c | 2 +-
> target/riscv/{ => tcg}/bitmanip_helper.c | 0
> target/riscv/{ => tcg}/cpu_helper.c | 239 +------------
> target/riscv/{ => tcg}/crypto_helper.c | 0
> target/riscv/{ => tcg}/csr.c | 45 +--
> target/riscv/{ => tcg}/csr.h | 6 +-
> target/riscv/{ => tcg}/debug.c | 2 +-
> target/riscv/{ => tcg}/debug.h | 0
> target/riscv/{ => tcg}/fpu_helper.c | 0
> .../insn_trans/trans_privileged.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rva.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvb.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvbf16.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvd.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvf.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvh.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvi.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvk.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvm.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvv.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvvk.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzabha.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzacas.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzalasr.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzawrs.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzce.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzcmop.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzfa.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzfh.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzicbo.c.inc | 0
> .../insn_trans/trans_rvzicfiss.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzicond.c.inc | 0
> .../{ => tcg}/insn_trans/trans_rvzimop.c.inc | 0
> .../{ => tcg}/insn_trans/trans_svinval.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xlrbr.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xmips.c.inc | 0
> .../{ => tcg}/insn_trans/trans_xthead.c.inc | 0
> .../insn_trans/trans_xventanacondops.c.inc | 0
> .../{ => tcg}/insn_trans/trans_zilsd.c.inc | 0
> target/riscv/{ => tcg}/m128_helper.c | 0
> target/riscv/tcg/meson.build | 31 +-
> target/riscv/{ => tcg}/mips_csr.c | 2 +-
> target/riscv/{ => tcg}/op_helper.c | 2 +-
> target/riscv/{ => tcg}/pmp.c | 2 +-
> target/riscv/{ => tcg}/pmp.h | 0
> target/riscv/{ => tcg}/pmu.c | 52 ---
> target/riscv/{ => tcg}/pmu.h | 1 -
> target/riscv/tcg/tcg-cpu.c | 30 +-
> target/riscv/{ => tcg}/th_csr.c | 2 +-
> target/riscv/{ => tcg}/translate.c | 0
> target/riscv/{ => tcg}/vcrypto_helper.c | 0
> target/riscv/{ => tcg}/vector_helper.c | 0
> target/riscv/{ => tcg}/vector_internals.c | 0
> target/riscv/{ => tcg}/vector_internals.h | 0
> target/riscv/{ => tcg}/zce_helper.c | 0
> target/riscv/time_helper.c | 33 +-
> 70 files changed, 495 insertions(+), 434 deletions(-)
> rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
> rename target/riscv/{ => tcg}/cpu_helper.c (92%)
> rename target/riscv/{ => tcg}/crypto_helper.c (100%)
> rename target/riscv/{ => tcg}/csr.c (99%)
> rename target/riscv/{ => tcg}/csr.h (96%)
> rename target/riscv/{ => tcg}/debug.c (99%)
> rename target/riscv/{ => tcg}/debug.h (100%)
> rename target/riscv/{ => tcg}/fpu_helper.c (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rva.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvb.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvbf16.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvd.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvf.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvh.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvi.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvk.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvm.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvv.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvvk.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzabha.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzacas.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzalasr.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzawrs.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzce.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzcmop.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzfa.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzfh.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicbo.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicfiss.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicond.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_rvzimop.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_svinval.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xlrbr.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xmips.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xthead.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_xventanacondops.c.inc (100%)
> rename target/riscv/{ => tcg}/insn_trans/trans_zilsd.c.inc (100%)
> rename target/riscv/{ => tcg}/m128_helper.c (100%)
> rename target/riscv/{ => tcg}/mips_csr.c (99%)
> rename target/riscv/{ => tcg}/op_helper.c (99%)
> rename target/riscv/{ => tcg}/pmp.c (99%)
> rename target/riscv/{ => tcg}/pmp.h (100%)
> rename target/riscv/{ => tcg}/pmu.c (86%)
> rename target/riscv/{ => tcg}/pmu.h (95%)
> rename target/riscv/{ => tcg}/th_csr.c (99%)
> rename target/riscv/{ => tcg}/translate.c (100%)
> rename target/riscv/{ => tcg}/vcrypto_helper.c (100%)
> rename target/riscv/{ => tcg}/vector_helper.c (100%)
> rename target/riscv/{ => tcg}/vector_internals.c (100%)
> rename target/riscv/{ => tcg}/vector_internals.h (100%)
> rename target/riscv/{ => tcg}/zce_helper.c (100%)
>
It seems like series does not apply on top of master, would that be
possible to rebase it?
Regards,
Pierrick
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-22 20:52 ` [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Pierrick Bouvier
@ 2026-06-22 21:04 ` Daniel Henrique Barboza
2026-06-22 21:23 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-22 21:04 UTC (permalink / raw)
To: Pierrick Bouvier, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn, philmd
On 6/22/2026 5:52 PM, Pierrick Bouvier wrote:
> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>> Hello,
>>
>> This series looks scary but it's mostly trivial and mechanical work.
>>
>> It is yet another attempt at fixing --disable-tcg. We have a recent
>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
>> Phil's work didn't get merged and it's now too hard to rebase and
>> revive, the most recent attempt got misled into the 'what is common code
>> between TCG and KVM' dungeon.
>>
>> After reviewing [1] I went ahead and look what other targets were doing
>> w.r.t their directory structure and comparing to RISC-V. In our case we
>> have a log going on in target/riscv:
>>
>> $ ls target/riscv
>> Kconfig cpu_cfg.h fpu_helper.c machine.c sbi_ecall_interface.h vector_internals.c
>> XVentanaCondOps.decode cpu_cfg_fields.h.inc gdbstub.c meson.build tcg vector_internals.h
>> arch_dump.c cpu_helper.c helper.h mips_csr.c th_csr.c xlrbr.decode
>> bitmanip_helper.c cpu_user.h insn16.decode monitor.c time_helper.c xmips.decode
>> common-semi-target.c cpu_vendorid.h insn32.decode op_helper.c time_helper.h xthead.decode
>> cpu-param.h crypto_helper.c insn_trans pmp.c trace-events zce_helper.c
>> cpu-qom.h csr.c instmap.h pmp.h trace.h
>> cpu.c csr.h internals.h pmu.c translate.c
>> cpu.h debug.c kvm pmu.h vcrypto_helper.c
>> cpu_bits.h debug.h m128_helper.c riscv-qmp-cmds.c vector_helper.c
>>
>>
>> It is non-trivial to realize that most of this stuff is TCG specific.
>> Meanwhile our 'tcg' subdir is mostly empty:
>>
>> $ ls target/riscv/tcg
>> meson.build tcg-cpu.c tcg-cpu.h
>>
>> If we compare it with other targets, let's say loongarch:
>>
>> $ ls target/loongarch/
>> Kconfig cpu-csr.h cpu-qom.h cpu_helper.c disas.c insns.decode loongarch-qmp-cmds.c tcg translate.h
>> README cpu-mmu.h cpu.c csr.c gdbstub.c internals.h machine.c trace-events vec.h
>> arch_dump.c cpu-param.h cpu.h csr.h helper.h kvm meson.build trace.h
>> $
>> $ ls target/loongarch/tcg
>> constant_timer.c fpu_helper.c insn_trans meson.build tcg_cpu.c tlb_helper.c vec_helper.c
>> csr_helper.c helper.h iocsr_helper.c op_helper.c tcg_loongarch.h translate.c
>>
>> It is straightforward to see which files are TCG exclusive and which
>> files are common to all accels.
>>
>> And this is what we did here. The patches goes mostly as follows:
>>
>> - move stuff to 'tcg' subdir. Most stuff is straighforward and is
>> manageable with a single patch. Other things required some logic to
>> go to either cpu.c or tcg-cpu;
>> - move TCG stuff to tcg-cpu.c;
>> - move common accel stuff to cpu.c. Usually from cpu_helper.c;
>> - filter TCG specific code in cpu.c and other files;
>> - trivial/assorted fixes in misc files that were needed to make
>> --disable-tcg work.
>>
>> Patch 24 is taken from Zephyr Li to enable the CI for --disable-tcg.
>> Hopefully we won't break it anytime soon.
>>
>> After this series we have --disable-tcg working and the following dir
>> structure:
>>
>> $ ls target/riscv
>> Kconfig cpu.c cpu_vendorid.h internals.h sbi_ecall_interface.h xlrbr.decode
>> XVentanaCondOps.decode cpu.h gdbstub.c kvm tcg xmips.decode
>> arch_dump.c cpu_bits.h helper.h machine.c time_helper.c xthead.decode
>> common-semi-target.c cpu_cfg.h insn16.decode meson.build time_helper.h
>> cpu-param.h cpu_cfg_fields.h.inc insn32.decode monitor.c trace-events
>> cpu-qom.h cpu_user.h instmap.h riscv-qmp-cmds.c trace.h
>> $
>> $ ls target/riscv/tcg
>> bitmanip_helper.c csr.h insn_trans op_helper.c pmu.h translate.c vector_internals.h
>> cpu_helper.c debug.c m128_helper.c pmp.c tcg-cpu.c vcrypto_helper.c zce_helper.c
>> crypto_helper.c debug.h meson.build pmp.h tcg-cpu.h vector_helper.c
>> csr.c fpu_helper.c mips_csr.c pmu.c th_csr.c vector_internals.c
>>
>>
>> [1] https://lore.kernel.org/qemu-devel/20260602091753.3209261-1-fritchleybohrer@gmail.com/
>> [2] https://lore.kernel.org/qemu-devel/20230711121453.59138-1-philmd@linaro.org/
>>
>>
>> Daniel Henrique Barboza (22):
>> target/riscv: move TCG only files to tcg subdir
>> target/riscv/machine.c: do not migrate pmp state with kvm
>> target/riscv: move pmp files to tcg subdir
>> target/riscv: make some riscv_sysemu_ops TCG only
>> target/riscv: move pmu.h to tcg subdir
>> target/riscv: move debug.h to tcg subdir
>> target/riscv: remove csr.h from kvm-cpu.c
>> target/riscv: move csr.h to tcg subdir
>> target/riscv: move custom_csrs logic to tcg-cpu.c
>> target/riscv: move riscv_cpu_set_nmi() to tcg-cpu.c
>> target/riscv: move valid_vm_* satp arrays to cpu.c
>> target/riscv: move some irq helpers to cpu.c
>> target/riscv: move riscv_cpu_claim_interrupts to cpu.c
>> target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state
>> target/riscv: gate riscv_cpu_update_mip with tcg_enabled()
>> target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold()
>> hw/riscv/riscv_hart.c isolate tcg only bits
>> target/riscv/gdbstub.c: isolate TCG only checks
>> target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint
>> target/riscv/tcg: remove unused riscv_cpu_get_geilen()
>> target/riscv: move riscv_cpu_set_geilen() to riscv-imsic
>> target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic
>>
>> Zephyr Li (2):
>> target/riscv: Remove unused tcg/tcg.h include
>> gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job
>>
>> .gitlab-ci.d/crossbuilds.yml | 8 +
>> hw/intc/riscv_aclint.c | 8 +
>> hw/intc/riscv_imsic.c | 24 ++
>> hw/riscv/fdt-common.c | 52 +++
>> hw/riscv/riscv_hart.c | 4 +-
>> hw/riscv/virt.c | 1 -
>> include/hw/riscv/fdt-common.h | 1 +
>> target/riscv/cpu.c | 316 +++++++++++++++---
>> target/riscv/cpu.h | 19 +-
>> target/riscv/gdbstub.c | 10 +-
>> target/riscv/kvm/kvm-cpu.c | 1 -
>> target/riscv/machine.c | 15 +-
>> target/riscv/meson.build | 17 -
>> target/riscv/monitor.c | 4 +-
>> target/riscv/riscv-qmp-cmds.c | 2 +-
>> target/riscv/{ => tcg}/bitmanip_helper.c | 0
>> target/riscv/{ => tcg}/cpu_helper.c | 239 +------------
>> target/riscv/{ => tcg}/crypto_helper.c | 0
>> target/riscv/{ => tcg}/csr.c | 45 +--
>> target/riscv/{ => tcg}/csr.h | 6 +-
>> target/riscv/{ => tcg}/debug.c | 2 +-
>> target/riscv/{ => tcg}/debug.h | 0
>> target/riscv/{ => tcg}/fpu_helper.c | 0
>> .../insn_trans/trans_privileged.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rva.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvb.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvbf16.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvd.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvf.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvh.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvi.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvk.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvm.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvv.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvvk.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzabha.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzacas.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzalasr.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzawrs.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzce.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzcmop.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzfa.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzfh.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzicbo.c.inc | 0
>> .../insn_trans/trans_rvzicfiss.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzicond.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_rvzimop.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_svinval.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_xlrbr.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_xmips.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_xthead.c.inc | 0
>> .../insn_trans/trans_xventanacondops.c.inc | 0
>> .../{ => tcg}/insn_trans/trans_zilsd.c.inc | 0
>> target/riscv/{ => tcg}/m128_helper.c | 0
>> target/riscv/tcg/meson.build | 31 +-
>> target/riscv/{ => tcg}/mips_csr.c | 2 +-
>> target/riscv/{ => tcg}/op_helper.c | 2 +-
>> target/riscv/{ => tcg}/pmp.c | 2 +-
>> target/riscv/{ => tcg}/pmp.h | 0
>> target/riscv/{ => tcg}/pmu.c | 52 ---
>> target/riscv/{ => tcg}/pmu.h | 1 -
>> target/riscv/tcg/tcg-cpu.c | 30 +-
>> target/riscv/{ => tcg}/th_csr.c | 2 +-
>> target/riscv/{ => tcg}/translate.c | 0
>> target/riscv/{ => tcg}/vcrypto_helper.c | 0
>> target/riscv/{ => tcg}/vector_helper.c | 0
>> target/riscv/{ => tcg}/vector_internals.c | 0
>> target/riscv/{ => tcg}/vector_internals.h | 0
>> target/riscv/{ => tcg}/zce_helper.c | 0
>> target/riscv/time_helper.c | 33 +-
>> 70 files changed, 495 insertions(+), 434 deletions(-)
>> rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
>> rename target/riscv/{ => tcg}/cpu_helper.c (92%)
>> rename target/riscv/{ => tcg}/crypto_helper.c (100%)
>> rename target/riscv/{ => tcg}/csr.c (99%)
>> rename target/riscv/{ => tcg}/csr.h (96%)
>> rename target/riscv/{ => tcg}/debug.c (99%)
>> rename target/riscv/{ => tcg}/debug.h (100%)
>> rename target/riscv/{ => tcg}/fpu_helper.c (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rva.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvb.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvbf16.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvd.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvf.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvh.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvi.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvk.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvm.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvv.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvvk.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzabha.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzacas.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzalasr.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzawrs.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzce.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzcmop.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzfa.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzfh.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicbo.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicfiss.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzicond.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_rvzimop.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_svinval.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_xlrbr.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_xmips.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_xthead.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_xventanacondops.c.inc (100%)
>> rename target/riscv/{ => tcg}/insn_trans/trans_zilsd.c.inc (100%)
>> rename target/riscv/{ => tcg}/m128_helper.c (100%)
>> rename target/riscv/{ => tcg}/mips_csr.c (99%)
>> rename target/riscv/{ => tcg}/op_helper.c (99%)
>> rename target/riscv/{ => tcg}/pmp.c (99%)
>> rename target/riscv/{ => tcg}/pmp.h (100%)
>> rename target/riscv/{ => tcg}/pmu.c (86%)
>> rename target/riscv/{ => tcg}/pmu.h (95%)
>> rename target/riscv/{ => tcg}/th_csr.c (99%)
>> rename target/riscv/{ => tcg}/translate.c (100%)
>> rename target/riscv/{ => tcg}/vcrypto_helper.c (100%)
>> rename target/riscv/{ => tcg}/vector_helper.c (100%)
>> rename target/riscv/{ => tcg}/vector_internals.c (100%)
>> rename target/riscv/{ => tcg}/vector_internals.h (100%)
>> rename target/riscv/{ => tcg}/zce_helper.c (100%)
>>
>
> It seems like series does not apply on top of master, would that be
> possible to rebase it?
Oh, sorry. I forgot to mention that patches are based on alistair's
riscv-to-apply.next branch:
https://github.com/alistair23/qemu
Cheers,
Daniel
>
> Regards,
> Pierrick
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-22 20:52 ` [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg Pierrick Bouvier
2026-06-22 21:04 ` Daniel Henrique Barboza
@ 2026-06-22 21:23 ` Philippe Mathieu-Daudé
2026-06-22 21:34 ` Pierrick Bouvier
1 sibling, 1 reply; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-22 21:23 UTC (permalink / raw)
To: Pierrick Bouvier, Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn
On 22/6/26 22:52, Pierrick Bouvier wrote:
> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>> Hello,
>>
>> This series looks scary but it's mostly trivial and mechanical work.
>>
>> It is yet another attempt at fixing --disable-tcg. We have a recent
>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
>> Phil's work didn't get merged and it's now too hard to rebase and
>> revive, the most recent attempt got misled into the 'what is common code
>> between TCG and KVM' dungeon.
> It seems like series does not apply on top of master, would that be
> possible to rebase it?
For some reason the RISC-V series are handled distinctly than the
rest of QEMU, Alistair queues work on his repository and developers
are custome to base their series on top of it (otherwise Alistair
can not apply them on his tree and asks for reposts), see the
riscv-to-apply.next branch on https://github.com/alistair23/qemu.
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-22 21:23 ` Philippe Mathieu-Daudé
@ 2026-06-22 21:34 ` Pierrick Bouvier
2026-06-23 8:17 ` Philippe Mathieu-Daudé
2026-06-23 9:48 ` Daniel Henrique Barboza
0 siblings, 2 replies; 71+ messages in thread
From: Pierrick Bouvier @ 2026-06-22 21:34 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn
On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
> On 22/6/26 22:52, Pierrick Bouvier wrote:
>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>>> Hello,
>>>
>>> This series looks scary but it's mostly trivial and mechanical work.
>>>
>>> It is yet another attempt at fixing --disable-tcg. We have a recent
>>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
>>> Phil's work didn't get merged and it's now too hard to rebase and
>>> revive, the most recent attempt got misled into the 'what is common code
>>> between TCG and KVM' dungeon.
>
>
>> It seems like series does not apply on top of master, would that be
>> possible to rebase it?
>
> For some reason the RISC-V series are handled distinctly than the
> rest of QEMU, Alistair queues work on his repository and developers
> are custome to base their series on top of it (otherwise Alistair
> can not apply them on his tree and asks for reposts), see the
> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
Unfortunately, it makes it hard to run any kind of automated testing,
especially for series like this that target specific configs.
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-22 21:34 ` Pierrick Bouvier
@ 2026-06-23 8:17 ` Philippe Mathieu-Daudé
2026-06-23 9:48 ` Daniel Henrique Barboza
1 sibling, 0 replies; 71+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-06-23 8:17 UTC (permalink / raw)
To: Pierrick Bouvier, Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn
On 22/6/26 23:34, Pierrick Bouvier wrote:
> On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
>> On 22/6/26 22:52, Pierrick Bouvier wrote:
>>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>>>> Hello,
>>>>
>>>> This series looks scary but it's mostly trivial and mechanical work.
>>>>
>>>> It is yet another attempt at fixing --disable-tcg. We have a recent
>>>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
>>>> Phil's work didn't get merged and it's now too hard to rebase and
>>>> revive, the most recent attempt got misled into the 'what is common code
>>>> between TCG and KVM' dungeon.
>>
>>
>>> It seems like series does not apply on top of master, would that be
>>> possible to rebase it?
>>
>> For some reason the RISC-V series are handled distinctly than the
>> rest of QEMU, Alistair queues work on his repository and developers
>> are custome to base their series on top of it (otherwise Alistair
>> can not apply them on his tree and asks for reposts), see the
>> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
>
> Unfortunately, it makes it hard to run any kind of automated testing,
> especially for series like this that target specific configs.
I agree, I was just explaining this special workflow. Peter also
told Cédric his preference for not using distinct workflow for VFIO:
https://lore.kernel.org/qemu-devel/CAFEAcA9HGWgJYvU_GVZCsxM7-WaR5QuwLES8aetPqD9jaLKr_A@mail.gmail.com/
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-22 21:34 ` Pierrick Bouvier
2026-06-23 8:17 ` Philippe Mathieu-Daudé
@ 2026-06-23 9:48 ` Daniel Henrique Barboza
2026-06-23 9:58 ` Peter Maydell
1 sibling, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-23 9:48 UTC (permalink / raw)
To: Pierrick Bouvier, Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn
On 6/22/2026 6:34 PM, Pierrick Bouvier wrote:
> On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
>> On 22/6/26 22:52, Pierrick Bouvier wrote:
>>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>>>> Hello,
>>>>
>>>> This series looks scary but it's mostly trivial and mechanical work.
>>>>
>>>> It is yet another attempt at fixing --disable-tcg. We have a recent
>>>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
>>>> Phil's work didn't get merged and it's now too hard to rebase and
>>>> revive, the most recent attempt got misled into the 'what is common code
>>>> between TCG and KVM' dungeon.
>>
>>
>>> It seems like series does not apply on top of master, would that be
>>> possible to rebase it?
>>
>> For some reason the RISC-V series are handled distinctly than the
>> rest of QEMU, Alistair queues work on his repository and developers
>> are custome to base their series on top of it (otherwise Alistair
>> can not apply them on his tree and asks for reposts), see the
>> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
>
> Unfortunately, it makes it hard to run any kind of automated testing,
> especially for series like this that target specific configs.
Don't we have ways of saying in the commit message "these patches applies
on top of these other patches" and then the tooling would deal with it?
I remember patchew doing stuff like that with that "Based-on: <message-id>"
tag.
At this point I would expect automatic tooling being able to understand
some form of "this gitlab/github branch contains the patches" and do their
thing. Maybe there's stuff out there to help us out.
Thanks,
Daniel
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-23 9:48 ` Daniel Henrique Barboza
@ 2026-06-23 9:58 ` Peter Maydell
2026-06-23 11:38 ` Daniel Henrique Barboza
0 siblings, 1 reply; 71+ messages in thread
From: Peter Maydell @ 2026-06-23 9:58 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: Pierrick Bouvier, Philippe Mathieu-Daudé, qemu-devel,
qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn
On Tue, 23 Jun 2026 at 10:49, Daniel Henrique Barboza
<daniel.barboza@oss.qualcomm.com> wrote:
>
>
>
> On 6/22/2026 6:34 PM, Pierrick Bouvier wrote:
> > On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
> >> On 22/6/26 22:52, Pierrick Bouvier wrote:
> >>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
> >>>> Hello,
> >>>>
> >>>> This series looks scary but it's mostly trivial and mechanical work.
> >>>>
> >>>> It is yet another attempt at fixing --disable-tcg. We have a recent
> >>>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
> >>>> Phil's work didn't get merged and it's now too hard to rebase and
> >>>> revive, the most recent attempt got misled into the 'what is common code
> >>>> between TCG and KVM' dungeon.
> >>
> >>
> >>> It seems like series does not apply on top of master, would that be
> >>> possible to rebase it?
> >>
> >> For some reason the RISC-V series are handled distinctly than the
> >> rest of QEMU, Alistair queues work on his repository and developers
> >> are custome to base their series on top of it (otherwise Alistair
> >> can not apply them on his tree and asks for reposts), see the
> >> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
> >
> > Unfortunately, it makes it hard to run any kind of automated testing,
> > especially for series like this that target specific configs.
>
> Don't we have ways of saying in the commit message "these patches applies
> on top of these other patches" and then the tooling would deal with it?
> I remember patchew doing stuff like that with that "Based-on: <message-id>"
> tag.
Yes, Based-on: is our convention for marking "this patchset needs some
other one to be applied first". But that should be the exception rather
than a common case -- if patchsets regularly need to be based on
something other than head-of-git, this is I think a sign that
maintainers are not sending out pull requests frequently enough.
I would prefer it if QEMU didn't develop kernel-style "subsystems
have their own particular workflows" fragmentation -- I don't
think we're big enough or that sub-parts of QEMU are sufficiently
well separated for it to work out well.
thanks
-- PMM
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-23 9:58 ` Peter Maydell
@ 2026-06-23 11:38 ` Daniel Henrique Barboza
2026-06-23 16:10 ` Pierrick Bouvier
2026-06-26 1:37 ` Alistair Francis
0 siblings, 2 replies; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-23 11:38 UTC (permalink / raw)
To: Peter Maydell
Cc: Pierrick Bouvier, Philippe Mathieu-Daudé, qemu-devel,
qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn
On 6/23/2026 6:58 AM, Peter Maydell wrote:
> On Tue, 23 Jun 2026 at 10:49, Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com> wrote:
>>
>>
>>
>> On 6/22/2026 6:34 PM, Pierrick Bouvier wrote:
>>> On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
>>>> On 22/6/26 22:52, Pierrick Bouvier wrote:
>>>>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>>>>>> Hello,
>>>>>>
>>>>>> This series looks scary but it's mostly trivial and mechanical work.
>>>>>>
>>>>>> It is yet another attempt at fixing --disable-tcg. We have a recent
>>>>>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
>>>>>> Phil's work didn't get merged and it's now too hard to rebase and
>>>>>> revive, the most recent attempt got misled into the 'what is common code
>>>>>> between TCG and KVM' dungeon.
>>>>
>>>>
>>>>> It seems like series does not apply on top of master, would that be
>>>>> possible to rebase it?
>>>>
>>>> For some reason the RISC-V series are handled distinctly than the
>>>> rest of QEMU, Alistair queues work on his repository and developers
>>>> are custome to base their series on top of it (otherwise Alistair
>>>> can not apply them on his tree and asks for reposts), see the
>>>> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
>>>
>>> Unfortunately, it makes it hard to run any kind of automated testing,
>>> especially for series like this that target specific configs.
>>
>> Don't we have ways of saying in the commit message "these patches applies
>> on top of these other patches" and then the tooling would deal with it?
>> I remember patchew doing stuff like that with that "Based-on: <message-id>"
>> tag.
>
> Yes, Based-on: is our convention for marking "this patchset needs some
> other one to be applied first". But that should be the exception rather
> than a common case -- if patchsets regularly need to be based on
> something other than head-of-git, this is I think a sign that
> maintainers are not sending out pull requests frequently enough.
>
> I would prefer it if QEMU didn't develop kernel-style "subsystems
> have their own particular workflows" fragmentation -- I don't
> think we're big enough or that sub-parts of QEMU are sufficiently
> well separated for it to work out well.
I agree that rebasing things on master is better than rebasing it on the
maintainer's tree. And we could make a better job at informing developers that
submitting a patch for qemu-riscv, vfio or any particular subtree, means that
the patch should be based on a maintainer tree X.
The thing is that sending patches on master only works if master is always up
to date, and that's not feasible with our current style of merging PRs. This
series we're commenting on is an example: it doesn't apply to master because
there are pre-approved RISC-V patches in the maintainer's tree from 2 days ago
(also my patches, I might add) that caused conflicts that I wasn't aware that
would happen. This conflict would have to be dealt with at some point by myself
or the maintainer, and it's not like 2 days is too much time without a PR.
We can argue "this is an exception that doesn't happen that often, we should
stick with using master as a base", and to a certain extend that's true. But
then this sort of conflict happens again, then again, then again, it comes to
a point where it's easier to tell developers to use the maintainer's tree instead
of master.
Maybe I'm downplaying the problem because I've been sending stuff based on the
maintainer's tree since forever and got used to it. IMO, unless we decide to be
like libvirt and create the "committer" role to allow trustworthy devs to push
stuff to master after acks, making it more feasible to expect master to be up to
date, I'm afraid we're closer to a kernel-style workflow. For better or worse.
Thanks,
Daniel
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-23 11:38 ` Daniel Henrique Barboza
@ 2026-06-23 16:10 ` Pierrick Bouvier
2026-06-23 19:01 ` Daniel Henrique Barboza
2026-06-26 1:37 ` Alistair Francis
1 sibling, 1 reply; 71+ messages in thread
From: Pierrick Bouvier @ 2026-06-23 16:10 UTC (permalink / raw)
To: Daniel Henrique Barboza, Peter Maydell
Cc: Philippe Mathieu-Daudé, qemu-devel, qemu-riscv,
alistair.francis, liwei1518, zhiwei_liu, chao.liu.zevorn
On 6/23/2026 4:38 AM, Daniel Henrique Barboza wrote:
>
>
> On 6/23/2026 6:58 AM, Peter Maydell wrote:
>> On Tue, 23 Jun 2026 at 10:49, Daniel Henrique Barboza
>> <daniel.barboza@oss.qualcomm.com> wrote:
>>>
>>>
>>>
>>> On 6/22/2026 6:34 PM, Pierrick Bouvier wrote:
>>>> On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
>>>>> On 22/6/26 22:52, Pierrick Bouvier wrote:
>>>>>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>>>>>>> Hello,
>>>>>>>
>>>>>>> This series looks scary but it's mostly trivial and mechanical work.
>>>>>>>
>>>>>>> It is yet another attempt at fixing --disable-tcg. We have a recent
>>>>>>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
>>>>>>> Phil's work didn't get merged and it's now too hard to rebase and
>>>>>>> revive, the most recent attempt got misled into the 'what is
>>>>>>> common code
>>>>>>> between TCG and KVM' dungeon.
>>>>>
>>>>>
>>>>>> It seems like series does not apply on top of master, would that be
>>>>>> possible to rebase it?
>>>>>
>>>>> For some reason the RISC-V series are handled distinctly than the
>>>>> rest of QEMU, Alistair queues work on his repository and developers
>>>>> are custome to base their series on top of it (otherwise Alistair
>>>>> can not apply them on his tree and asks for reposts), see the
>>>>> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
>>>>
>>>> Unfortunately, it makes it hard to run any kind of automated testing,
>>>> especially for series like this that target specific configs.
>>>
>>> Don't we have ways of saying in the commit message "these patches
>>> applies
>>> on top of these other patches" and then the tooling would deal with it?
>>> I remember patchew doing stuff like that with that "Based-on:
>>> <message-id>"
>>> tag.
>>
>> Yes, Based-on: is our convention for marking "this patchset needs some
>> other one to be applied first". But that should be the exception rather
>> than a common case -- if patchsets regularly need to be based on
>> something other than head-of-git, this is I think a sign that
>> maintainers are not sending out pull requests frequently enough.
>>
>> I would prefer it if QEMU didn't develop kernel-style "subsystems
>> have their own particular workflows" fragmentation -- I don't
>> think we're big enough or that sub-parts of QEMU are sufficiently
>> well separated for it to work out well.
>
> I agree that rebasing things on master is better than rebasing it on the
> maintainer's tree. And we could make a better job at informing
> developers that
> submitting a patch for qemu-riscv, vfio or any particular subtree, means
> that
> the patch should be based on a maintainer tree X.
>
> The thing is that sending patches on master only works if master is
> always up
> to date, and that's not feasible with our current style of merging PRs.
> This
> series we're commenting on is an example: it doesn't apply to master
> because
> there are pre-approved RISC-V patches in the maintainer's tree from 2
> days ago
> (also my patches, I might add) that caused conflicts that I wasn't aware
> that
> would happen. This conflict would have to be dealt with at some point
> by myself
> or the maintainer, and it's not like 2 days is too much time without a PR.
>
> We can argue "this is an exception that doesn't happen that often, we
> should
> stick with using master as a base", and to a certain extend that's
> true. But
> then this sort of conflict happens again, then again, then again, it
> comes to
> a point where it's easier to tell developers to use the maintainer's
> tree instead
> of master.
>
> Maybe I'm downplaying the problem because I've been sending stuff based
> on the
> maintainer's tree since forever and got used to it. IMO, unless we
> decide to be
> like libvirt and create the "committer" role to allow trustworthy devs
> to push
> stuff to master after acks, making it more feasible to expect master to
> be up to
> date, I'm afraid we're closer to a kernel-style workflow. For better or
> worse.
>
>
> Thanks,
> Daniel
>
>
>>
>> thanks
>> -- PMM
>
In this very specific case, where base patches are needed, maybe it
would be better to make the required commits appear in this series, and
mention in cover letter that patches 1-N are just coming from another
series and are already reviewed/approved. IMHO it doesn't hurt, and
reviewers are free to skip commits already reviewed.
Or, a solution I'm not fond of but I ended up adopting most of the time,
just wait for required patches to be merged on master before posting the
series, and work on something else meanwhile.
Ideally, yes, it would be better if maintainers could send PR more
frequently to avoid creating those intermediate staging trees. The
faster we merge, the less conflicts we'll have.
Regards,
Pierrick
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-23 16:10 ` Pierrick Bouvier
@ 2026-06-23 19:01 ` Daniel Henrique Barboza
2026-06-23 19:16 ` Pierrick Bouvier
0 siblings, 1 reply; 71+ messages in thread
From: Daniel Henrique Barboza @ 2026-06-23 19:01 UTC (permalink / raw)
To: Pierrick Bouvier, Peter Maydell
Cc: Philippe Mathieu-Daudé, qemu-devel, qemu-riscv,
alistair.francis, liwei1518, zhiwei_liu, chao.liu.zevorn
On 6/23/2026 1:10 PM, Pierrick Bouvier wrote:
> On 6/23/2026 4:38 AM, Daniel Henrique Barboza wrote:
>>
>>
>> On 6/23/2026 6:58 AM, Peter Maydell wrote:
>>> On Tue, 23 Jun 2026 at 10:49, Daniel Henrique Barboza
>>> <daniel.barboza@oss.qualcomm.com> wrote:
>>>>
>>>>
>>>>
>>>> On 6/22/2026 6:34 PM, Pierrick Bouvier wrote:
>>>>> On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
>>>>>> On 22/6/26 22:52, Pierrick Bouvier wrote:
>>>>>>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>>>>>>>> Hello,
>>>>>>>>
>>>>>>>> This series looks scary but it's mostly trivial and mechanical work.
>>>>>>>>
>>>>>>>> It is yet another attempt at fixing --disable-tcg. We have a recent
>>>>>>>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
>>>>>>>> Phil's work didn't get merged and it's now too hard to rebase and
>>>>>>>> revive, the most recent attempt got misled into the 'what is
>>>>>>>> common code
>>>>>>>> between TCG and KVM' dungeon.
>>>>>>
>>>>>>
>>>>>>> It seems like series does not apply on top of master, would that be
>>>>>>> possible to rebase it?
>>>>>>
>>>>>> For some reason the RISC-V series are handled distinctly than the
>>>>>> rest of QEMU, Alistair queues work on his repository and developers
>>>>>> are custome to base their series on top of it (otherwise Alistair
>>>>>> can not apply them on his tree and asks for reposts), see the
>>>>>> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
>>>>>
>>>>> Unfortunately, it makes it hard to run any kind of automated testing,
>>>>> especially for series like this that target specific configs.
>>>>
>>>> Don't we have ways of saying in the commit message "these patches
>>>> applies
>>>> on top of these other patches" and then the tooling would deal with it?
>>>> I remember patchew doing stuff like that with that "Based-on:
>>>> <message-id>"
>>>> tag.
>>>
>>> Yes, Based-on: is our convention for marking "this patchset needs some
>>> other one to be applied first". But that should be the exception rather
>>> than a common case -- if patchsets regularly need to be based on
>>> something other than head-of-git, this is I think a sign that
>>> maintainers are not sending out pull requests frequently enough.
>>>
>>> I would prefer it if QEMU didn't develop kernel-style "subsystems
>>> have their own particular workflows" fragmentation -- I don't
>>> think we're big enough or that sub-parts of QEMU are sufficiently
>>> well separated for it to work out well.
>>
>> I agree that rebasing things on master is better than rebasing it on the
>> maintainer's tree. And we could make a better job at informing
>> developers that
>> submitting a patch for qemu-riscv, vfio or any particular subtree, means
>> that
>> the patch should be based on a maintainer tree X.
>>
>> The thing is that sending patches on master only works if master is
>> always up
>> to date, and that's not feasible with our current style of merging PRs.
>> This
>> series we're commenting on is an example: it doesn't apply to master
>> because
>> there are pre-approved RISC-V patches in the maintainer's tree from 2
>> days ago
>> (also my patches, I might add) that caused conflicts that I wasn't aware
>> that
>> would happen. This conflict would have to be dealt with at some point
>> by myself
>> or the maintainer, and it's not like 2 days is too much time without a PR.
>>
>> We can argue "this is an exception that doesn't happen that often, we
>> should
>> stick with using master as a base", and to a certain extend that's
>> true. But
>> then this sort of conflict happens again, then again, then again, it
>> comes to
>> a point where it's easier to tell developers to use the maintainer's
>> tree instead
>> of master.
>>
>> Maybe I'm downplaying the problem because I've been sending stuff based
>> on the
>> maintainer's tree since forever and got used to it. IMO, unless we
>> decide to be
>> like libvirt and create the "committer" role to allow trustworthy devs
>> to push
>> stuff to master after acks, making it more feasible to expect master to
>> be up to
>> date, I'm afraid we're closer to a kernel-style workflow. For better or
>> worse.
>>
>>
>> Thanks,
>> Daniel
>>
>>
>>>
>>> thanks
>>> -- PMM
>>
>
> In this very specific case, where base patches are needed, maybe it
> would be better to make the required commits appear in this series, and
> mention in cover letter that patches 1-N are just coming from another
> series and are already reviewed/approved. IMHO it doesn't hurt, and
> reviewers are free to skip commits already reviewed.
That's fair enough but I wonder if that won't scare people away with
even bigger series :D in this case here I would need to either send all
the queued patches, making the series go to 40+, or I would need to triage
which patches from the queue creates a conflict with this work and send
only those.
Now, as for qemu-ci ... How farfetched it is to make it read a specific tag
in the cover-letter, e.g. "branch-id", that can point to a gitlab/github
repo with the patches, and use that code base instead of applying the
patches to the master branch? Then for the next version of this work
I could do
"branch-id: https://gitlab.com/danielhb/qemu/-/tree/riscv_disabletcg_v2"
and the tool would still work. If there's no "branch-id" then it assumes
that the patches are to be applied on master.
And yeah, in an ideal world the problem goes away if we just do more PRs and
strive to keep 'master' updated. I'm just thinking out loud about possible
alternatives until we reach that point.
Cheers,
Daniel
>
> Or, a solution I'm not fond of but I ended up adopting most of the time,
> just wait for required patches to be merged on master before posting the
> series, and work on something else meanwhile.
>
> Ideally, yes, it would be better if maintainers could send PR more
> frequently to avoid creating those intermediate staging trees. The
> faster we merge, the less conflicts we'll have.
>
> Regards,
> Pierrick
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-23 19:01 ` Daniel Henrique Barboza
@ 2026-06-23 19:16 ` Pierrick Bouvier
2026-06-26 1:41 ` Alistair Francis
2026-06-27 3:31 ` Konstantin Ryabitsev
0 siblings, 2 replies; 71+ messages in thread
From: Pierrick Bouvier @ 2026-06-23 19:16 UTC (permalink / raw)
To: Daniel Henrique Barboza, Peter Maydell
Cc: Philippe Mathieu-Daudé, qemu-devel, qemu-riscv,
alistair.francis, liwei1518, zhiwei_liu, chao.liu.zevorn
On 6/23/2026 12:01 PM, Daniel Henrique Barboza wrote:
>
>
> On 6/23/2026 1:10 PM, Pierrick Bouvier wrote:
>> On 6/23/2026 4:38 AM, Daniel Henrique Barboza wrote:
>>>
>>>
>>> On 6/23/2026 6:58 AM, Peter Maydell wrote:
>>>> On Tue, 23 Jun 2026 at 10:49, Daniel Henrique Barboza
>>>> <daniel.barboza@oss.qualcomm.com> wrote:
>>>>>
>>>>>
>>>>>
>>>>> On 6/22/2026 6:34 PM, Pierrick Bouvier wrote:
>>>>>> On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
>>>>>>> On 22/6/26 22:52, Pierrick Bouvier wrote:
>>>>>>>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>>>>>>>>> Hello,
>>>>>>>>>
>>>>>>>>> This series looks scary but it's mostly trivial and mechanical
>>>>>>>>> work.
>>>>>>>>>
>>>>>>>>> It is yet another attempt at fixing --disable-tcg. We have a
>>>>>>>>> recent
>>>>>>>>> work sent to the ML [1] and we had Phil's attempt back in 2023
>>>>>>>>> [2].
>>>>>>>>> Phil's work didn't get merged and it's now too hard to rebase and
>>>>>>>>> revive, the most recent attempt got misled into the 'what is
>>>>>>>>> common code
>>>>>>>>> between TCG and KVM' dungeon.
>>>>>>>
>>>>>>>
>>>>>>>> It seems like series does not apply on top of master, would that be
>>>>>>>> possible to rebase it?
>>>>>>>
>>>>>>> For some reason the RISC-V series are handled distinctly than the
>>>>>>> rest of QEMU, Alistair queues work on his repository and developers
>>>>>>> are custome to base their series on top of it (otherwise Alistair
>>>>>>> can not apply them on his tree and asks for reposts), see the
>>>>>>> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
>>>>>>
>>>>>> Unfortunately, it makes it hard to run any kind of automated testing,
>>>>>> especially for series like this that target specific configs.
>>>>>
>>>>> Don't we have ways of saying in the commit message "these patches
>>>>> applies
>>>>> on top of these other patches" and then the tooling would deal with
>>>>> it?
>>>>> I remember patchew doing stuff like that with that "Based-on:
>>>>> <message-id>"
>>>>> tag.
>>>>
>>>> Yes, Based-on: is our convention for marking "this patchset needs some
>>>> other one to be applied first". But that should be the exception rather
>>>> than a common case -- if patchsets regularly need to be based on
>>>> something other than head-of-git, this is I think a sign that
>>>> maintainers are not sending out pull requests frequently enough.
>>>>
>>>> I would prefer it if QEMU didn't develop kernel-style "subsystems
>>>> have their own particular workflows" fragmentation -- I don't
>>>> think we're big enough or that sub-parts of QEMU are sufficiently
>>>> well separated for it to work out well.
>>>
>>> I agree that rebasing things on master is better than rebasing it on the
>>> maintainer's tree. And we could make a better job at informing
>>> developers that
>>> submitting a patch for qemu-riscv, vfio or any particular subtree, means
>>> that
>>> the patch should be based on a maintainer tree X.
>>>
>>> The thing is that sending patches on master only works if master is
>>> always up
>>> to date, and that's not feasible with our current style of merging PRs.
>>> This
>>> series we're commenting on is an example: it doesn't apply to master
>>> because
>>> there are pre-approved RISC-V patches in the maintainer's tree from 2
>>> days ago
>>> (also my patches, I might add) that caused conflicts that I wasn't aware
>>> that
>>> would happen. This conflict would have to be dealt with at some point
>>> by myself
>>> or the maintainer, and it's not like 2 days is too much time without
>>> a PR.
>>>
>>> We can argue "this is an exception that doesn't happen that often, we
>>> should
>>> stick with using master as a base", and to a certain extend that's
>>> true. But
>>> then this sort of conflict happens again, then again, then again, it
>>> comes to
>>> a point where it's easier to tell developers to use the maintainer's
>>> tree instead
>>> of master.
>>>
>>> Maybe I'm downplaying the problem because I've been sending stuff based
>>> on the
>>> maintainer's tree since forever and got used to it. IMO, unless we
>>> decide to be
>>> like libvirt and create the "committer" role to allow trustworthy devs
>>> to push
>>> stuff to master after acks, making it more feasible to expect master to
>>> be up to
>>> date, I'm afraid we're closer to a kernel-style workflow. For better or
>>> worse.
>>>
>>>
>>> Thanks,
>>> Daniel
>>>
>>>
>>>>
>>>> thanks
>>>> -- PMM
>>>
>>
>> In this very specific case, where base patches are needed, maybe it
>> would be better to make the required commits appear in this series, and
>> mention in cover letter that patches 1-N are just coming from another
>> series and are already reviewed/approved. IMHO it doesn't hurt, and
>> reviewers are free to skip commits already reviewed.
>
> That's fair enough but I wonder if that won't scare people away with
> even bigger series :D in this case here I would need to either send all
> the queued patches, making the series go to 40+, or I would need to triage
> which patches from the queue creates a conflict with this work and send
> only those.
>
> Now, as for qemu-ci ... How farfetched it is to make it read a specific
> tag
> in the cover-letter, e.g. "branch-id", that can point to a gitlab/github
> repo with the patches, and use that code base instead of applying the
> patches to the master branch? Then for the next version of this work
> I could do
>
> "branch-id: https://gitlab.com/danielhb/qemu/-/tree/riscv_disabletcg_v2"
>
Based-on: is a QEMU specific tag, that is only understood by patchew,
and no other tool to my knowledge.
b4 has base_commit, which allows to give a specific base, but not a
specific repository. I'm not aware of any b4 tag that allows to mention
a base series. It makes sense, series are not branches, and stacking
them comes with a lot of problems.
So it seems like email workflow is quite limited in this regard, and the
only way to deal with it properly is to wait for base patches to be
merged, or include them in the series.
From another perspective, the same problem would exist if we would use a
forge like GitHub or GitLab. It's not possible to stack PR on top of
others, and only solution is to wait, or duplicate patches. IMHO, it's a
sane default, as it forces correct ordering instead of allowing chaotic
development.
> and the tool would still work. If there's no "branch-id" then it assumes
> that the patches are to be applied on master.
>
>
> And yeah, in an ideal world the problem goes away if we just do more PRs
> and
> strive to keep 'master' updated. I'm just thinking out loud about possible
> alternatives until we reach that point.
>
>
> Cheers,
> Daniel
>
>>
>> Or, a solution I'm not fond of but I ended up adopting most of the time,
>> just wait for required patches to be merged on master before posting the
>> series, and work on something else meanwhile.
>>
>> Ideally, yes, it would be better if maintainers could send PR more
>> frequently to avoid creating those intermediate staging trees. The
>> faster we merge, the less conflicts we'll have.
>>
>> Regards,
>> Pierrick
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-23 19:16 ` Pierrick Bouvier
@ 2026-06-26 1:41 ` Alistair Francis
2026-06-26 15:28 ` Pierrick Bouvier
2026-06-27 3:31 ` Konstantin Ryabitsev
1 sibling, 1 reply; 71+ messages in thread
From: Alistair Francis @ 2026-06-26 1:41 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: Daniel Henrique Barboza, Peter Maydell,
Philippe Mathieu-Daudé, qemu-devel, qemu-riscv,
alistair.francis, liwei1518, zhiwei_liu, chao.liu.zevorn
On Wed, Jun 24, 2026 at 5:18 AM Pierrick Bouvier
<pierrick.bouvier@oss.qualcomm.com> wrote:
>
> On 6/23/2026 12:01 PM, Daniel Henrique Barboza wrote:
> >
> >
> > On 6/23/2026 1:10 PM, Pierrick Bouvier wrote:
> >> On 6/23/2026 4:38 AM, Daniel Henrique Barboza wrote:
> >>>
> >>>
> >>> On 6/23/2026 6:58 AM, Peter Maydell wrote:
> >>>> On Tue, 23 Jun 2026 at 10:49, Daniel Henrique Barboza
> >>>> <daniel.barboza@oss.qualcomm.com> wrote:
> >>>>>
> >>>>>
> >>>>>
> >>>>> On 6/22/2026 6:34 PM, Pierrick Bouvier wrote:
> >>>>>> On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
> >>>>>>> On 22/6/26 22:52, Pierrick Bouvier wrote:
> >>>>>>>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
> >>>>>>>>> Hello,
> >>>>>>>>>
> >>>>>>>>> This series looks scary but it's mostly trivial and mechanical
> >>>>>>>>> work.
> >>>>>>>>>
> >>>>>>>>> It is yet another attempt at fixing --disable-tcg. We have a
> >>>>>>>>> recent
> >>>>>>>>> work sent to the ML [1] and we had Phil's attempt back in 2023
> >>>>>>>>> [2].
> >>>>>>>>> Phil's work didn't get merged and it's now too hard to rebase and
> >>>>>>>>> revive, the most recent attempt got misled into the 'what is
> >>>>>>>>> common code
> >>>>>>>>> between TCG and KVM' dungeon.
> >>>>>>>
> >>>>>>>
> >>>>>>>> It seems like series does not apply on top of master, would that be
> >>>>>>>> possible to rebase it?
> >>>>>>>
> >>>>>>> For some reason the RISC-V series are handled distinctly than the
> >>>>>>> rest of QEMU, Alistair queues work on his repository and developers
> >>>>>>> are custome to base their series on top of it (otherwise Alistair
> >>>>>>> can not apply them on his tree and asks for reposts), see the
> >>>>>>> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
> >>>>>>
> >>>>>> Unfortunately, it makes it hard to run any kind of automated testing,
> >>>>>> especially for series like this that target specific configs.
> >>>>>
> >>>>> Don't we have ways of saying in the commit message "these patches
> >>>>> applies
> >>>>> on top of these other patches" and then the tooling would deal with
> >>>>> it?
> >>>>> I remember patchew doing stuff like that with that "Based-on:
> >>>>> <message-id>"
> >>>>> tag.
> >>>>
> >>>> Yes, Based-on: is our convention for marking "this patchset needs some
> >>>> other one to be applied first". But that should be the exception rather
> >>>> than a common case -- if patchsets regularly need to be based on
> >>>> something other than head-of-git, this is I think a sign that
> >>>> maintainers are not sending out pull requests frequently enough.
> >>>>
> >>>> I would prefer it if QEMU didn't develop kernel-style "subsystems
> >>>> have their own particular workflows" fragmentation -- I don't
> >>>> think we're big enough or that sub-parts of QEMU are sufficiently
> >>>> well separated for it to work out well.
> >>>
> >>> I agree that rebasing things on master is better than rebasing it on the
> >>> maintainer's tree. And we could make a better job at informing
> >>> developers that
> >>> submitting a patch for qemu-riscv, vfio or any particular subtree, means
> >>> that
> >>> the patch should be based on a maintainer tree X.
> >>>
> >>> The thing is that sending patches on master only works if master is
> >>> always up
> >>> to date, and that's not feasible with our current style of merging PRs.
> >>> This
> >>> series we're commenting on is an example: it doesn't apply to master
> >>> because
> >>> there are pre-approved RISC-V patches in the maintainer's tree from 2
> >>> days ago
> >>> (also my patches, I might add) that caused conflicts that I wasn't aware
> >>> that
> >>> would happen. This conflict would have to be dealt with at some point
> >>> by myself
> >>> or the maintainer, and it's not like 2 days is too much time without
> >>> a PR.
> >>>
> >>> We can argue "this is an exception that doesn't happen that often, we
> >>> should
> >>> stick with using master as a base", and to a certain extend that's
> >>> true. But
> >>> then this sort of conflict happens again, then again, then again, it
> >>> comes to
> >>> a point where it's easier to tell developers to use the maintainer's
> >>> tree instead
> >>> of master.
> >>>
> >>> Maybe I'm downplaying the problem because I've been sending stuff based
> >>> on the
> >>> maintainer's tree since forever and got used to it. IMO, unless we
> >>> decide to be
> >>> like libvirt and create the "committer" role to allow trustworthy devs
> >>> to push
> >>> stuff to master after acks, making it more feasible to expect master to
> >>> be up to
> >>> date, I'm afraid we're closer to a kernel-style workflow. For better or
> >>> worse.
> >>>
> >>>
> >>> Thanks,
> >>> Daniel
> >>>
> >>>
> >>>>
> >>>> thanks
> >>>> -- PMM
> >>>
> >>
> >> In this very specific case, where base patches are needed, maybe it
> >> would be better to make the required commits appear in this series, and
> >> mention in cover letter that patches 1-N are just coming from another
> >> series and are already reviewed/approved. IMHO it doesn't hurt, and
> >> reviewers are free to skip commits already reviewed.
> >
> > That's fair enough but I wonder if that won't scare people away with
> > even bigger series :D in this case here I would need to either send all
> > the queued patches, making the series go to 40+, or I would need to triage
> > which patches from the queue creates a conflict with this work and send
> > only those.
> >
> > Now, as for qemu-ci ... How farfetched it is to make it read a specific
> > tag
> > in the cover-letter, e.g. "branch-id", that can point to a gitlab/github
> > repo with the patches, and use that code base instead of applying the
> > patches to the master branch? Then for the next version of this work
> > I could do
> >
> > "branch-id: https://gitlab.com/danielhb/qemu/-/tree/riscv_disabletcg_v2"
> >
>
> Based-on: is a QEMU specific tag, that is only understood by patchew,
> and no other tool to my knowledge.
> b4 has base_commit, which allows to give a specific base, but not a
> specific repository. I'm not aware of any b4 tag that allows to mention
> a base series. It makes sense, series are not branches, and stacking
> them comes with a lot of problems.
>
> So it seems like email workflow is quite limited in this regard, and the
> only way to deal with it properly is to wait for base patches to be
> merged, or include them in the series.
>
> From another perspective, the same problem would exist if we would use a
> forge like GitHub or GitLab. It's not possible to stack PR on top of
> others, and only solution is to wait, or duplicate patches. IMHO, it's a
> sane default, as it forces correct ordering instead of allowing chaotic
> development.
>
> > and the tool would still work. If there's no "branch-id" then it assumes
> > that the patches are to be applied on master.
> >
> >
> > And yeah, in an ideal world the problem goes away if we just do more PRs
> > and
> > strive to keep 'master' updated. I'm just thinking out loud about possible
> > alternatives until we reach that point.
When you sent v2 of this series it had been one week since the last
RISC-V PR. Are we really aiming for more than one PR a week?
> >
> >
> > Cheers,
> > Daniel
> >
> >>
> >> Or, a solution I'm not fond of but I ended up adopting most of the time,
> >> just wait for required patches to be merged on master before posting the
> >> series, and work on something else meanwhile.
I do feel that a few people do that, just not Daniel :)
Alistair
> >>
> >> Ideally, yes, it would be better if maintainers could send PR more
> >> frequently to avoid creating those intermediate staging trees. The
> >> faster we merge, the less conflicts we'll have.
> >>
> >> Regards,
> >> Pierrick
> >
>
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-26 1:41 ` Alistair Francis
@ 2026-06-26 15:28 ` Pierrick Bouvier
0 siblings, 0 replies; 71+ messages in thread
From: Pierrick Bouvier @ 2026-06-26 15:28 UTC (permalink / raw)
To: Alistair Francis
Cc: Daniel Henrique Barboza, Peter Maydell,
Philippe Mathieu-Daudé, qemu-devel, qemu-riscv,
alistair.francis, liwei1518, zhiwei_liu, chao.liu.zevorn
On 6/25/2026 6:41 PM, Alistair Francis wrote:
> On Wed, Jun 24, 2026 at 5:18 AM Pierrick Bouvier
> <pierrick.bouvier@oss.qualcomm.com> wrote:
>>
>> On 6/23/2026 12:01 PM, Daniel Henrique Barboza wrote:
>>>
>>>
>>> On 6/23/2026 1:10 PM, Pierrick Bouvier wrote:
>>>> On 6/23/2026 4:38 AM, Daniel Henrique Barboza wrote:
>>>>>
>>>>>
>>>>> On 6/23/2026 6:58 AM, Peter Maydell wrote:
>>>>>> On Tue, 23 Jun 2026 at 10:49, Daniel Henrique Barboza
>>>>>> <daniel.barboza@oss.qualcomm.com> wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On 6/22/2026 6:34 PM, Pierrick Bouvier wrote:
>>>>>>>> On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
>>>>>>>>> On 22/6/26 22:52, Pierrick Bouvier wrote:
>>>>>>>>>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>>>>>>>>>>> Hello,
>>>>>>>>>>>
>>>>>>>>>>> This series looks scary but it's mostly trivial and mechanical
>>>>>>>>>>> work.
>>>>>>>>>>>
>>>>>>>>>>> It is yet another attempt at fixing --disable-tcg. We have a
>>>>>>>>>>> recent
>>>>>>>>>>> work sent to the ML [1] and we had Phil's attempt back in 2023
>>>>>>>>>>> [2].
>>>>>>>>>>> Phil's work didn't get merged and it's now too hard to rebase and
>>>>>>>>>>> revive, the most recent attempt got misled into the 'what is
>>>>>>>>>>> common code
>>>>>>>>>>> between TCG and KVM' dungeon.
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>> It seems like series does not apply on top of master, would that be
>>>>>>>>>> possible to rebase it?
>>>>>>>>>
>>>>>>>>> For some reason the RISC-V series are handled distinctly than the
>>>>>>>>> rest of QEMU, Alistair queues work on his repository and developers
>>>>>>>>> are custome to base their series on top of it (otherwise Alistair
>>>>>>>>> can not apply them on his tree and asks for reposts), see the
>>>>>>>>> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
>>>>>>>>
>>>>>>>> Unfortunately, it makes it hard to run any kind of automated testing,
>>>>>>>> especially for series like this that target specific configs.
>>>>>>>
>>>>>>> Don't we have ways of saying in the commit message "these patches
>>>>>>> applies
>>>>>>> on top of these other patches" and then the tooling would deal with
>>>>>>> it?
>>>>>>> I remember patchew doing stuff like that with that "Based-on:
>>>>>>> <message-id>"
>>>>>>> tag.
>>>>>>
>>>>>> Yes, Based-on: is our convention for marking "this patchset needs some
>>>>>> other one to be applied first". But that should be the exception rather
>>>>>> than a common case -- if patchsets regularly need to be based on
>>>>>> something other than head-of-git, this is I think a sign that
>>>>>> maintainers are not sending out pull requests frequently enough.
>>>>>>
>>>>>> I would prefer it if QEMU didn't develop kernel-style "subsystems
>>>>>> have their own particular workflows" fragmentation -- I don't
>>>>>> think we're big enough or that sub-parts of QEMU are sufficiently
>>>>>> well separated for it to work out well.
>>>>>
>>>>> I agree that rebasing things on master is better than rebasing it on the
>>>>> maintainer's tree. And we could make a better job at informing
>>>>> developers that
>>>>> submitting a patch for qemu-riscv, vfio or any particular subtree, means
>>>>> that
>>>>> the patch should be based on a maintainer tree X.
>>>>>
>>>>> The thing is that sending patches on master only works if master is
>>>>> always up
>>>>> to date, and that's not feasible with our current style of merging PRs.
>>>>> This
>>>>> series we're commenting on is an example: it doesn't apply to master
>>>>> because
>>>>> there are pre-approved RISC-V patches in the maintainer's tree from 2
>>>>> days ago
>>>>> (also my patches, I might add) that caused conflicts that I wasn't aware
>>>>> that
>>>>> would happen. This conflict would have to be dealt with at some point
>>>>> by myself
>>>>> or the maintainer, and it's not like 2 days is too much time without
>>>>> a PR.
>>>>>
>>>>> We can argue "this is an exception that doesn't happen that often, we
>>>>> should
>>>>> stick with using master as a base", and to a certain extend that's
>>>>> true. But
>>>>> then this sort of conflict happens again, then again, then again, it
>>>>> comes to
>>>>> a point where it's easier to tell developers to use the maintainer's
>>>>> tree instead
>>>>> of master.
>>>>>
>>>>> Maybe I'm downplaying the problem because I've been sending stuff based
>>>>> on the
>>>>> maintainer's tree since forever and got used to it. IMO, unless we
>>>>> decide to be
>>>>> like libvirt and create the "committer" role to allow trustworthy devs
>>>>> to push
>>>>> stuff to master after acks, making it more feasible to expect master to
>>>>> be up to
>>>>> date, I'm afraid we're closer to a kernel-style workflow. For better or
>>>>> worse.
>>>>>
>>>>>
>>>>> Thanks,
>>>>> Daniel
>>>>>
>>>>>
>>>>>>
>>>>>> thanks
>>>>>> -- PMM
>>>>>
>>>>
>>>> In this very specific case, where base patches are needed, maybe it
>>>> would be better to make the required commits appear in this series, and
>>>> mention in cover letter that patches 1-N are just coming from another
>>>> series and are already reviewed/approved. IMHO it doesn't hurt, and
>>>> reviewers are free to skip commits already reviewed.
>>>
>>> That's fair enough but I wonder if that won't scare people away with
>>> even bigger series :D in this case here I would need to either send all
>>> the queued patches, making the series go to 40+, or I would need to triage
>>> which patches from the queue creates a conflict with this work and send
>>> only those.
>>>
>>> Now, as for qemu-ci ... How farfetched it is to make it read a specific
>>> tag
>>> in the cover-letter, e.g. "branch-id", that can point to a gitlab/github
>>> repo with the patches, and use that code base instead of applying the
>>> patches to the master branch? Then for the next version of this work
>>> I could do
>>>
>>> "branch-id: https://gitlab.com/danielhb/qemu/-/tree/riscv_disabletcg_v2"
>>>
>>
>> Based-on: is a QEMU specific tag, that is only understood by patchew,
>> and no other tool to my knowledge.
>> b4 has base_commit, which allows to give a specific base, but not a
>> specific repository. I'm not aware of any b4 tag that allows to mention
>> a base series. It makes sense, series are not branches, and stacking
>> them comes with a lot of problems.
>>
>> So it seems like email workflow is quite limited in this regard, and the
>> only way to deal with it properly is to wait for base patches to be
>> merged, or include them in the series.
>>
>> From another perspective, the same problem would exist if we would use a
>> forge like GitHub or GitLab. It's not possible to stack PR on top of
>> others, and only solution is to wait, or duplicate patches. IMHO, it's a
>> sane default, as it forces correct ordering instead of allowing chaotic
>> development.
>>
>>> and the tool would still work. If there's no "branch-id" then it assumes
>>> that the patches are to be applied on master.
>>>
>>>
>>> And yeah, in an ideal world the problem goes away if we just do more PRs
>>> and
>>> strive to keep 'master' updated. I'm just thinking out loud about possible
>>> alternatives until we reach that point.
>
> When you sent v2 of this series it had been one week since the last
> RISC-V PR. Are we really aiming for more than one PR a week?
>
>>>
>>>
>>> Cheers,
>>> Daniel
>>>
>>>>
>>>> Or, a solution I'm not fond of but I ended up adopting most of the time,
>>>> just wait for required patches to be merged on master before posting the
>>>> series, and work on something else meanwhile.
>
> I do feel that a few people do that, just not Daniel :)
>
Waiting works well if you know the wait period is deterministic. "Ok, I
missed this train, let me catch the one next week". Unfortunately, it
varies per maintainer, and some are even stochastic processes on their own.
I can't blame people who submit and are not maintainer to feel
frustration with this, it's a real issue.
> Alistair
>
>>>>
>>>> Ideally, yes, it would be better if maintainers could send PR more
>>>> frequently to avoid creating those intermediate staging trees. The
>>>> faster we merge, the less conflicts we'll have.
>>>>
>>>> Regards,
>>>> Pierrick
>>>
>>
>>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-23 19:16 ` Pierrick Bouvier
2026-06-26 1:41 ` Alistair Francis
@ 2026-06-27 3:31 ` Konstantin Ryabitsev
2026-06-27 7:00 ` Pierrick Bouvier
1 sibling, 1 reply; 71+ messages in thread
From: Konstantin Ryabitsev @ 2026-06-27 3:31 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: Daniel Henrique Barboza, Peter Maydell,
Philippe Mathieu-Daudé, qemu-devel, qemu-riscv,
alistair.francis, liwei1518, zhiwei_liu, chao.liu.zevorn
On Tue, Jun 23, 2026 at 12:16:56PM -0700, Pierrick Bouvier wrote:
> Based-on: is a QEMU specific tag, that is only understood by patchew,
> and no other tool to my knowledge.
> b4 has base_commit, which allows to give a specific base, but not a
> specific repository. I'm not aware of any b4 tag that allows to mention
> a base series. It makes sense, series are not branches, and stacking
> them comes with a lot of problems.
>
> So it seems like email workflow is quite limited in this regard, and the
> only way to deal with it properly is to wait for base patches to be
> merged, or include them in the series.
You *can* specify dependencies with a b4-managed branch, via --edit-deps.
However, both the contributor and the maintainer have to use b4 to retrieve
and apply patches for it to really work.
If the maintainer retrieves the series using "b4 shazam <msgid>" then, if the
series specifies prerequisites, they will all be retrieved and applied.
See https://b4.docs.kernel.org/en/latest/contributor/prep.html#working-with-series-dependencies
It remains marked as "experimental" simply because not enough people use it
and therefore there are still many corner-case bugs that exist and just
haven't been properly discovered.
HTH!
-K
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-27 3:31 ` Konstantin Ryabitsev
@ 2026-06-27 7:00 ` Pierrick Bouvier
0 siblings, 0 replies; 71+ messages in thread
From: Pierrick Bouvier @ 2026-06-27 7:00 UTC (permalink / raw)
To: Konstantin Ryabitsev
Cc: Daniel Henrique Barboza, Peter Maydell,
Philippe Mathieu-Daudé, qemu-devel, qemu-riscv,
alistair.francis, liwei1518, zhiwei_liu, chao.liu.zevorn
On 6/26/2026 8:31 PM, Konstantin Ryabitsev wrote:
> On Tue, Jun 23, 2026 at 12:16:56PM -0700, Pierrick Bouvier wrote:
>> Based-on: is a QEMU specific tag, that is only understood by patchew,
>> and no other tool to my knowledge.
>> b4 has base_commit, which allows to give a specific base, but not a
>> specific repository. I'm not aware of any b4 tag that allows to mention
>> a base series. It makes sense, series are not branches, and stacking
>> them comes with a lot of problems.
>>
>> So it seems like email workflow is quite limited in this regard, and the
>> only way to deal with it properly is to wait for base patches to be
>> merged, or include them in the series.
>
> You *can* specify dependencies with a b4-managed branch, via --edit-deps.
> However, both the contributor and the maintainer have to use b4 to retrieve
> and apply patches for it to really work.
>
> If the maintainer retrieves the series using "b4 shazam <msgid>" then, if the
> series specifies prerequisites, they will all be retrieved and applied.
>
> See https://b4.docs.kernel.org/en/latest/contributor/prep.html#working-with-series-dependencies
>
> It remains marked as "experimental" simply because not enough people use it
> and therefore there are still many corner-case bugs that exist and just
> haven't been properly discovered.
>
Maybe I missed something in the documentation (feel free to correct me),
but as mentioned above, it seems like b4 only has base-commit (+
change-id, message-id, patch-id). In the current discussion, the need
would be to specify a base commit/branch + a base repository, similar to
information included in a pull request, thus why I said it's limited. I
didn't see how to cover that with b4 or any other tool and email
workflow, and maybe it's not even a good idea to be honest.
> HTH!
>
> -K
Thanks,
Pierrick
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-23 11:38 ` Daniel Henrique Barboza
2026-06-23 16:10 ` Pierrick Bouvier
@ 2026-06-26 1:37 ` Alistair Francis
2026-06-26 15:25 ` Pierrick Bouvier
1 sibling, 1 reply; 71+ messages in thread
From: Alistair Francis @ 2026-06-26 1:37 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: Peter Maydell, Pierrick Bouvier, Philippe Mathieu-Daudé,
qemu-devel, qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn
On Tue, Jun 23, 2026 at 9:39 PM Daniel Henrique Barboza
<daniel.barboza@oss.qualcomm.com> wrote:
>
>
>
> On 6/23/2026 6:58 AM, Peter Maydell wrote:
> > On Tue, 23 Jun 2026 at 10:49, Daniel Henrique Barboza
> > <daniel.barboza@oss.qualcomm.com> wrote:
> >>
> >>
> >>
> >> On 6/22/2026 6:34 PM, Pierrick Bouvier wrote:
> >>> On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
> >>>> On 22/6/26 22:52, Pierrick Bouvier wrote:
> >>>>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
> >>>>>> Hello,
> >>>>>>
> >>>>>> This series looks scary but it's mostly trivial and mechanical work.
> >>>>>>
> >>>>>> It is yet another attempt at fixing --disable-tcg. We have a recent
> >>>>>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
> >>>>>> Phil's work didn't get merged and it's now too hard to rebase and
> >>>>>> revive, the most recent attempt got misled into the 'what is common code
> >>>>>> between TCG and KVM' dungeon.
> >>>>
> >>>>
> >>>>> It seems like series does not apply on top of master, would that be
> >>>>> possible to rebase it?
> >>>>
> >>>> For some reason the RISC-V series are handled distinctly than the
> >>>> rest of QEMU, Alistair queues work on his repository and developers
> >>>> are custome to base their series on top of it (otherwise Alistair
> >>>> can not apply them on his tree and asks for reposts), see the
> >>>> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
> >>>
> >>> Unfortunately, it makes it hard to run any kind of automated testing,
> >>> especially for series like this that target specific configs.
> >>
> >> Don't we have ways of saying in the commit message "these patches applies
> >> on top of these other patches" and then the tooling would deal with it?
> >> I remember patchew doing stuff like that with that "Based-on: <message-id>"
> >> tag.
> >
> > Yes, Based-on: is our convention for marking "this patchset needs some
> > other one to be applied first". But that should be the exception rather
> > than a common case -- if patchsets regularly need to be based on
> > something other than head-of-git, this is I think a sign that
> > maintainers are not sending out pull requests frequently enough.
> >
> > I would prefer it if QEMU didn't develop kernel-style "subsystems
> > have their own particular workflows" fragmentation -- I don't
> > think we're big enough or that sub-parts of QEMU are sufficiently
> > well separated for it to work out well.
>
> I agree that rebasing things on master is better than rebasing it on the
> maintainer's tree. And we could make a better job at informing developers that
> submitting a patch for qemu-riscv, vfio or any particular subtree, means that
> the patch should be based on a maintainer tree X.
I would prefer patches on master, the issue is it just creates a lot
of conflicts. That takes time for me to fix and I'm always worried
that I'll mess something up and it will go upstream with a bug that
wasn't in the original patch because no one gets a chance to verify
that I rebased it correctly.
>
> The thing is that sending patches on master only works if master is always up
> to date, and that's not feasible with our current style of merging PRs. This
> series we're commenting on is an example: it doesn't apply to master because
> there are pre-approved RISC-V patches in the maintainer's tree from 2 days ago
> (also my patches, I might add) that caused conflicts that I wasn't aware that
> would happen. This conflict would have to be dealt with at some point by myself
> or the maintainer, and it's not like 2 days is too much time without a PR.
Yeah, I try to send them every few weeks, but when all the patches are
touching the same few files it's hard not to hit conflicts.
>
> We can argue "this is an exception that doesn't happen that often, we should
> stick with using master as a base", and to a certain extend that's true. But
> then this sort of conflict happens again, then again, then again, it comes to
> a point where it's easier to tell developers to use the maintainer's tree instead
> of master.
Which is exactly what happened. I think I have just asked people to
rebase on the RISC-V tree enough times that they just start with that
from the beginning.
Alistair
>
> Maybe I'm downplaying the problem because I've been sending stuff based on the
> maintainer's tree since forever and got used to it. IMO, unless we decide to be
> like libvirt and create the "committer" role to allow trustworthy devs to push
> stuff to master after acks, making it more feasible to expect master to be up to
> date, I'm afraid we're closer to a kernel-style workflow. For better or worse.
>
>
> Thanks,
> Daniel
>
>
> >
> > thanks
> > -- PMM
>
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 00/24] target/riscv: move TCG files and fix --disable-tcg
2026-06-26 1:37 ` Alistair Francis
@ 2026-06-26 15:25 ` Pierrick Bouvier
0 siblings, 0 replies; 71+ messages in thread
From: Pierrick Bouvier @ 2026-06-26 15:25 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Peter Maydell, Philippe Mathieu-Daudé, qemu-devel,
qemu-riscv, alistair.francis, liwei1518, zhiwei_liu,
chao.liu.zevorn
On 6/25/2026 6:37 PM, Alistair Francis wrote:
> On Tue, Jun 23, 2026 at 9:39 PM Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com> wrote:
>>
>>
>>
>> On 6/23/2026 6:58 AM, Peter Maydell wrote:
>>> On Tue, 23 Jun 2026 at 10:49, Daniel Henrique Barboza
>>> <daniel.barboza@oss.qualcomm.com> wrote:
>>>>
>>>>
>>>>
>>>> On 6/22/2026 6:34 PM, Pierrick Bouvier wrote:
>>>>> On 6/22/2026 2:23 PM, Philippe Mathieu-Daudé wrote:
>>>>>> On 22/6/26 22:52, Pierrick Bouvier wrote:
>>>>>>> On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
>>>>>>>> Hello,
>>>>>>>>
>>>>>>>> This series looks scary but it's mostly trivial and mechanical work.
>>>>>>>>
>>>>>>>> It is yet another attempt at fixing --disable-tcg. We have a recent
>>>>>>>> work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
>>>>>>>> Phil's work didn't get merged and it's now too hard to rebase and
>>>>>>>> revive, the most recent attempt got misled into the 'what is common code
>>>>>>>> between TCG and KVM' dungeon.
>>>>>>
>>>>>>
>>>>>>> It seems like series does not apply on top of master, would that be
>>>>>>> possible to rebase it?
>>>>>>
>>>>>> For some reason the RISC-V series are handled distinctly than the
>>>>>> rest of QEMU, Alistair queues work on his repository and developers
>>>>>> are custome to base their series on top of it (otherwise Alistair
>>>>>> can not apply them on his tree and asks for reposts), see the
>>>>>> riscv-to-apply.next branch on https://github.com/alistair23/qemu.
>>>>>
>>>>> Unfortunately, it makes it hard to run any kind of automated testing,
>>>>> especially for series like this that target specific configs.
>>>>
>>>> Don't we have ways of saying in the commit message "these patches applies
>>>> on top of these other patches" and then the tooling would deal with it?
>>>> I remember patchew doing stuff like that with that "Based-on: <message-id>"
>>>> tag.
>>>
>>> Yes, Based-on: is our convention for marking "this patchset needs some
>>> other one to be applied first". But that should be the exception rather
>>> than a common case -- if patchsets regularly need to be based on
>>> something other than head-of-git, this is I think a sign that
>>> maintainers are not sending out pull requests frequently enough.
>>>
>>> I would prefer it if QEMU didn't develop kernel-style "subsystems
>>> have their own particular workflows" fragmentation -- I don't
>>> think we're big enough or that sub-parts of QEMU are sufficiently
>>> well separated for it to work out well.
>>
>> I agree that rebasing things on master is better than rebasing it on the
>> maintainer's tree. And we could make a better job at informing developers that
>> submitting a patch for qemu-riscv, vfio or any particular subtree, means that
>> the patch should be based on a maintainer tree X.
>
> I would prefer patches on master, the issue is it just creates a lot
> of conflicts. That takes time for me to fix and I'm always worried
> that I'll mess something up and it will go upstream with a bug that
> wasn't in the original patch because no one gets a chance to verify
> that I rebased it correctly.
>
I agree it does not scale. It creates friction both for you and people
who submit in the subsystem.
>>
>> The thing is that sending patches on master only works if master is always up
>> to date, and that's not feasible with our current style of merging PRs. This
>> series we're commenting on is an example: it doesn't apply to master because
>> there are pre-approved RISC-V patches in the maintainer's tree from 2 days ago
>> (also my patches, I might add) that caused conflicts that I wasn't aware that
>> would happen. This conflict would have to be dealt with at some point by myself
>> or the maintainer, and it's not like 2 days is too much time without a PR.
>
> Yeah, I try to send them every few weeks, but when all the patches are
> touching the same few files it's hard not to hit conflicts.
>
Then simply apply a FIFO strategy. Take series as they come, and leave
conflicting one out. IMHO, it should not be the responsibility of a
maintainer.
>>
>> We can argue "this is an exception that doesn't happen that often, we should
>> stick with using master as a base", and to a certain extend that's true. But
>> then this sort of conflict happens again, then again, then again, it comes to
>> a point where it's easier to tell developers to use the maintainer's tree instead
>> of master.
>
> Which is exactly what happened. I think I have just asked people to
> rebase on the RISC-V tree enough times that they just start with that
> from the beginning.
>
How about merging things to master fast enough so people can just rebase
on master? It seems like it would solve both people problems, and yours
also. No need to do any rebase, and no wait time for developers.
The only thing it requires is to increase PR frequency, and I would even
go as far as suggesting to send one PR per series if you want to provide
the best velocity possible for this subsystem. Just automate the push
and CI triggering, so it does not take more than 2 min of your time.
When a conflict happen or a test fail, simply ask "please rebase/fix",
and wait for the next version. Not your problem anymore.
What do you think?
> Alistair
>
>>
>> Maybe I'm downplaying the problem because I've been sending stuff based on the
>> maintainer's tree since forever and got used to it. IMO, unless we decide to be
>> like libvirt and create the "committer" role to allow trustworthy devs to push
>> stuff to master after acks, making it more feasible to expect master to be up to
>> date, I'm afraid we're closer to a kernel-style workflow. For better or worse.
>>
>>
>> Thanks,
>> Daniel
>>
>>
>>>
>>> thanks
>>> -- PMM
>>
>>
Regards,
Pierrick
^ permalink raw reply [flat|nested] 71+ messages in thread