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From: Pavel Machek <pavel@nabladev.com>
To: Biju <biju.das.au@gmail.com>
Cc: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>,
	Pavel Machek <pavel@nabladev.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 6.12.y-cip 14/23] mfd: syscon: Allow syscon nodes without a "syscon" compatible
Date: Wed, 15 Jul 2026 12:20:36 +0200	[thread overview]
Message-ID: <alde9PF2ScrONpQg@duo.ucw.cz> (raw)
In-Reply-To: <20260703105923.251255-15-biju.das.jz@bp.renesas.com>

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Hi!

> From: "Rob Herring (Arm)" <robh@kernel.org>
> 
> [ Upstream commit ba5095ebbc7a83965ac049a50fa493d7c751f19b ]
> 
> of_syscon_register_regmap() was added for nodes which need a custom
> regmap setup. It's not really correct for those nodes to claim they are
> compatible with "syscon" as the default handling likely doesn't work in
> those cases. If device_node_get_regmap() happens to be called first,
> then of_syscon_register() will be called and an incorrect regmap will be
> created (barring some other error). That may lead to unknown results in
> the worst case. In the best case, of_syscon_register_regmap() will fail
> with -EEXIST. This problem remains unless these cases drop "syscon" (an
> ABI issue) or we exclude them using their specific compatible. ATM,
> there is only one user: "google,gs101-pmu"
> 
> There are also cases of adding "syscon" compatible to existing nodes
> after the fact in order to register the syscon. That presents a
> potential DT ABI problem. Instead, if there's a kernel change needing a
> syscon for a node, then it should be possible to allow the kernel to
> register a syscon without a DT change. That's only possible by using
> of_syscon_register_regmap() currently, but in the future we may want to
> support a match list for cases which don't need a custom regmap.
> 
> With this change, the lookup functions will succeed for any node
> registered by of_syscon_register_regmap() regardless of whether the node
> compatible contains "syscon".

I note this is change to generic code. I trust it has all dependencies
it needs and will not cause problems somewhere?

Thanks and best regards,
								Pavel

> +++ b/drivers/mfd/syscon.c
> @@ -176,9 +176,12 @@ static struct regmap *device_node_get_regmap(struct device_node *np,
>  			break;
>  		}
>  
> -	if (!syscon)
> -		syscon = of_syscon_register(np, check_res);
> -
> +	if (!syscon) {
> +		if (of_device_is_compatible(np, "syscon"))
> +			syscon = of_syscon_register(np, check_res);
> +		else
> +			syscon = ERR_PTR(-EINVAL);
> +	}
>  	mutex_unlock(&syscon_list_lock);
>  
>  	if (IS_ERR(syscon))
> @@ -243,9 +246,6 @@ EXPORT_SYMBOL_GPL(device_node_to_regmap);
>  
>  struct regmap *syscon_node_to_regmap(struct device_node *np)
>  {
> -	if (!of_device_is_compatible(np, "syscon"))
> -		return ERR_PTR(-EINVAL);
> -
>  	return device_node_get_regmap(np, true);
>  }
>  EXPORT_SYMBOL_GPL(syscon_node_to_regmap);

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  reply	other threads:[~2026-07-15 10:20 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-03 10:58 [PATCH 6.12.y-cip 00/23] Add support for RZ/G3L pincontrol Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 01/23] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document reset-names Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 02/23] dt-bindings: pinctrl: renesas: Document RZ/G3L SoC Biju
2026-07-15 10:12   ` Pavel Machek
2026-07-03 10:58 ` [PATCH 6.12.y-cip 03/23] pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 04/23] pinctrl: renesas: rzg2l: Fix SMT register cache handling Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 05/23] pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 06/23] pinctrl: renesas: rzg2l: Handle RZ/V2H(P) IOLH configuration in PM cache Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 07/23] pinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resume Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 08/23] pinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in PM Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 09/23] pinctrl: renesas: rzg2l: Make QSPI register handling conditional Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 10/23] pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO} Biju
2026-07-15 10:18   ` Pavel Machek
2026-07-03 10:59 ` [PATCH 6.12.y-cip 11/23] pinctrl: renesas: rzg2l: Update OEN pin validation to use exact match Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 12/23] pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 13/23] pinctrl: renesas: rzg2l: Simplify rzg2l_pinctrl_set_mux() Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 14/23] mfd: syscon: Allow syscon nodes without a "syscon" compatible Biju
2026-07-15 10:20   ` Pavel Machek [this message]
2026-07-03 10:59 ` [PATCH 6.12.y-cip 15/23] pinctrl: renesas: rzg2l: Add support for clone channel control Biju
2026-07-15 10:23   ` Pavel Machek
2026-07-03 10:59 ` [PATCH 6.12.y-cip 16/23] arm64: dts: renesas: Add pinctrl reset-names for RZ/G2L and RZ/V2H family SoCs Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 17/23] arm64: dts: renesas: Drop "syscon" fallback compatible from sysc/sys nodes Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 18/23] arm64: dts: renesas: r9a08g046: Add ICU node Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 19/23] arm64: dts: renesas: r9a08g046: Add pincontrol node Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 20/23] arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 21/23] arm64: dts: renesas: rzg3l-smarc-som: Add pinctrl configuration for ETH0 Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 22/23] arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 23/23] arm64: dts: renesas: r9a08g046l48-smarc: Add gpio keys Biju
2026-07-15 10:23 ` [PATCH 6.12.y-cip 00/23] Add support for RZ/G3L pincontrol Pavel Machek

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