All of lore.kernel.org
 help / color / mirror / Atom feed
From: Pavel Machek <pavel@nabladev.com>
To: Biju <biju.das.au@gmail.com>
Cc: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>,
	Pavel Machek <pavel@nabladev.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 6.12.y-cip 00/23] Add support for RZ/G3L pincontrol
Date: Wed, 15 Jul 2026 12:23:59 +0200	[thread overview]
Message-ID: <aldfv7QGPrBZ4yh6@duo.ucw.cz> (raw)
In-Reply-To: <20260703105923.251255-1-biju.das.jz@bp.renesas.com>

[-- Attachment #1: Type: text/plain, Size: 799 bytes --]

Hi!

> This patch series aims to add pinctrl driver support for RZ/G3L SoC.
> 
> All the patches from this series are cherry-picked from mainline except
> the patch for dropping "syscon" fallback compatible from sysc/sys
> nodes from RZ/G3S, RZ/G3E, RZ/V2H and RZ/V2N to match with the
> documentation after backporting the commit ba5095ebbc7a ("mfd: syscon:
> Allow syscon nodes without a "syscon" compatible") to 6.12.y-cip.

I had some minor comments here, but those should be fixed in mainline,
first, so they should not block the merge.

This looks okay to me.

Reviewed-by: Pavel Machek <pavel@nabladev.com>

I can apply the series if it passes testing and there are no other
comments.

Best regards,
                                                                Pavel

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

      parent reply	other threads:[~2026-07-15 10:24 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-03 10:58 [PATCH 6.12.y-cip 00/23] Add support for RZ/G3L pincontrol Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 01/23] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document reset-names Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 02/23] dt-bindings: pinctrl: renesas: Document RZ/G3L SoC Biju
2026-07-15 10:12   ` Pavel Machek
2026-07-16  1:19     ` [cip-dev] " nobuhiro.iwamatsu.x90
2026-07-03 10:58 ` [PATCH 6.12.y-cip 03/23] pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 04/23] pinctrl: renesas: rzg2l: Fix SMT register cache handling Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 05/23] pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 06/23] pinctrl: renesas: rzg2l: Handle RZ/V2H(P) IOLH configuration in PM cache Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 07/23] pinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resume Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 08/23] pinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in PM Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 09/23] pinctrl: renesas: rzg2l: Make QSPI register handling conditional Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 10/23] pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO} Biju
2026-07-15 10:18   ` Pavel Machek
2026-07-03 10:59 ` [PATCH 6.12.y-cip 11/23] pinctrl: renesas: rzg2l: Update OEN pin validation to use exact match Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 12/23] pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 13/23] pinctrl: renesas: rzg2l: Simplify rzg2l_pinctrl_set_mux() Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 14/23] mfd: syscon: Allow syscon nodes without a "syscon" compatible Biju
2026-07-15 10:20   ` Pavel Machek
2026-07-03 10:59 ` [PATCH 6.12.y-cip 15/23] pinctrl: renesas: rzg2l: Add support for clone channel control Biju
2026-07-15 10:23   ` Pavel Machek
2026-07-03 10:59 ` [PATCH 6.12.y-cip 16/23] arm64: dts: renesas: Add pinctrl reset-names for RZ/G2L and RZ/V2H family SoCs Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 17/23] arm64: dts: renesas: Drop "syscon" fallback compatible from sysc/sys nodes Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 18/23] arm64: dts: renesas: r9a08g046: Add ICU node Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 19/23] arm64: dts: renesas: r9a08g046: Add pincontrol node Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 20/23] arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 21/23] arm64: dts: renesas: rzg3l-smarc-som: Add pinctrl configuration for ETH0 Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 22/23] arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 23/23] arm64: dts: renesas: r9a08g046l48-smarc: Add gpio keys Biju
2026-07-15 10:23 ` Pavel Machek [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=aldfv7QGPrBZ4yh6@duo.ucw.cz \
    --to=pavel@nabladev.com \
    --cc=biju.das.au@gmail.com \
    --cc=biju.das.jz@bp.renesas.com \
    --cc=cip-dev@lists.cip-project.org \
    --cc=nobuhiro.iwamatsu.x90@mail.toshiba \
    --cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.