From: Pavel Machek <pavel@nabladev.com>
To: Biju <biju.das.au@gmail.com>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>,
Pavel Machek <pavel@nabladev.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 6.12.y-cip 10/23] pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO}
Date: Wed, 15 Jul 2026 12:18:09 +0200 [thread overview]
Message-ID: <aldeYc-IRbM2fWHP@duo.ucw.cz> (raw)
In-Reply-To: <20260703105923.251255-11-biju.das.jz@bp.renesas.com>
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Hi!
> The RZ/G3L SoC has support for setting power source that are not
> controlled by the following voltage control registers:
> - SD_CH{0,1,2}_POC, XSPI_POC, ETH{0,1}_POC, I3C_SET.POC
>
> Add support for selecting voltages using OTHER_POC register for
> setting I/O domain voltage for WDT, ISO and AWO by extending
> rzg2l_caps_to_pwr_reg() with a mask output parameter so that callers
> callers can identify which bit(s) within OTHER_POC correspond to the
> requested domain. Update rzg2l_get_power_source() to extract the
> relevant bit field via field_get() when reading OTHER_POC, and update
> rzg2l_set_power_source() to perform a read-modify-write under the
> spinlock when writing to OTHER_POC, since multiple domains share the
> same register.
I believe more robustness is needed here.
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -958,25 +983,37 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps
>
> switch (ps) {
> case 1800:
> - val = PVDD_1800;
> + poc_val = PVDD_1800;
> break;
> case 2500:
> if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))
> return -EINVAL;
> - val = PVDD_2500;
> + poc_val = PVDD_2500;
> break;
> case 3300:
> - val = PVDD_3300;
> + poc_val = PVDD_3300;
> break;
> default:
> return -EINVAL;
> }
>
> - pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
> + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask);
> if (pwr_reg < 0)
> return pwr_reg;
>
> - writeb(val, pctrl->base + pwr_reg);
> + if (pwr_reg == OTHER_POC) {
> + scoped_guard(raw_spinlock, &pctrl->lock) {
> + val = readb(pctrl->base + pwr_reg);
> + if (poc_val)
> + val |= mask;
> + else
> + val &= ~mask;
> + writeb(val, pctrl->base + pwr_reg);
> + }
This is strange. You test that ps is right ammount of milivolts, but
here you just ignore poc_val, no matter if user selected 1800, 2500 or
3300mV.
I believe you should cross-check values here, so that if user requests
1800mV, he does not silenly get 3300mV (or vice versa, I'm not sure
how the hardware work).
Best regards,
Pavel
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next prev parent reply other threads:[~2026-07-15 10:18 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-03 10:58 [PATCH 6.12.y-cip 00/23] Add support for RZ/G3L pincontrol Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 01/23] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document reset-names Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 02/23] dt-bindings: pinctrl: renesas: Document RZ/G3L SoC Biju
2026-07-15 10:12 ` Pavel Machek
2026-07-16 1:19 ` [cip-dev] " nobuhiro.iwamatsu.x90
2026-07-03 10:58 ` [PATCH 6.12.y-cip 03/23] pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 04/23] pinctrl: renesas: rzg2l: Fix SMT register cache handling Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 05/23] pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 06/23] pinctrl: renesas: rzg2l: Handle RZ/V2H(P) IOLH configuration in PM cache Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 07/23] pinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resume Biju
2026-07-03 10:58 ` [PATCH 6.12.y-cip 08/23] pinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in PM Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 09/23] pinctrl: renesas: rzg2l: Make QSPI register handling conditional Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 10/23] pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO} Biju
2026-07-15 10:18 ` Pavel Machek [this message]
2026-07-03 10:59 ` [PATCH 6.12.y-cip 11/23] pinctrl: renesas: rzg2l: Update OEN pin validation to use exact match Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 12/23] pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 13/23] pinctrl: renesas: rzg2l: Simplify rzg2l_pinctrl_set_mux() Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 14/23] mfd: syscon: Allow syscon nodes without a "syscon" compatible Biju
2026-07-15 10:20 ` Pavel Machek
2026-07-03 10:59 ` [PATCH 6.12.y-cip 15/23] pinctrl: renesas: rzg2l: Add support for clone channel control Biju
2026-07-15 10:23 ` Pavel Machek
2026-07-03 10:59 ` [PATCH 6.12.y-cip 16/23] arm64: dts: renesas: Add pinctrl reset-names for RZ/G2L and RZ/V2H family SoCs Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 17/23] arm64: dts: renesas: Drop "syscon" fallback compatible from sysc/sys nodes Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 18/23] arm64: dts: renesas: r9a08g046: Add ICU node Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 19/23] arm64: dts: renesas: r9a08g046: Add pincontrol node Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 20/23] arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 21/23] arm64: dts: renesas: rzg3l-smarc-som: Add pinctrl configuration for ETH0 Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 22/23] arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface Biju
2026-07-03 10:59 ` [PATCH 6.12.y-cip 23/23] arm64: dts: renesas: r9a08g046l48-smarc: Add gpio keys Biju
2026-07-15 10:23 ` [PATCH 6.12.y-cip 00/23] Add support for RZ/G3L pincontrol Pavel Machek
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