* [PATCH v7 01/24] KVM: arm64: Add a generic clock
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 13:48 ` Vincent Donnefort
2026-07-15 11:58 ` [PATCH v7 02/24] KVM: arm64: Donate MMIO to the hypervisor Mostafa Saleh
` (22 subsequent siblings)
23 siblings, 1 reply; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
IOMMU drivers need to track time, mainly for timeouts.
Add 2 new functions to nvhe/clock.c:
- hyp_clock_init(): Get the system timer frequency at boot
- hyp_clock_ns(): Get current time in nano seconds.
This is mainly used for timeouts, so a malicious host can DoS the
system or cause premature timeouts which likely end up in hyp panic,
that should be acceptable as neither of those would undermine the
security guarantees.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
arch/arm64/kvm/hyp/include/nvhe/clock.h | 3 +++
arch/arm64/kvm/hyp/nvhe/Makefile | 4 ++--
arch/arm64/kvm/hyp/nvhe/clock.c | 29 +++++++++++++++++++++++++
arch/arm64/kvm/hyp/nvhe/setup.c | 5 +++++
4 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/hyp/include/nvhe/clock.h b/arch/arm64/kvm/hyp/include/nvhe/clock.h
index ae03ec6965af..7ef982939bf9 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/clock.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/clock.h
@@ -13,4 +13,7 @@ static inline void
trace_hyp_clock_update(u32 mult, u32 shift, u64 epoch_ns, u64 epoch_cyc) { }
static inline u64 trace_hyp_clock(void) { return 0; }
#endif
+
+u64 hyp_clock_ns(void);
+int hyp_clock_init(void);
#endif
diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile
index f57450ebcb49..7c879292974d 100644
--- a/arch/arm64/kvm/hyp/nvhe/Makefile
+++ b/arch/arm64/kvm/hyp/nvhe/Makefile
@@ -26,10 +26,10 @@ hyp-obj-y := timer-sr.o sysreg-sr.o debug-sr.o switch.o tlb.o hyp-init.o host.o
hyp-main.o hyp-smp.o psci-relay.o early_alloc.o page_alloc.o \
cache.o setup.o mm.o mem_protect.o sys_regs.o pkvm.o stacktrace.o ffa.o
hyp-obj-y += ../vgic-v3-sr.o ../aarch32.o ../vgic-v2-cpuif-proxy.o ../entry.o \
- ../hyp-entry.o ../exception.o ../pgtable.o ../vgic-v5-sr.o
+ ../hyp-entry.o ../exception.o ../pgtable.o ../vgic-v5-sr.o clock.o
hyp-obj-y += ../../../kernel/smccc-call.o
hyp-obj-$(CONFIG_LIST_HARDENED) += list_debug.o
-hyp-obj-$(CONFIG_NVHE_EL2_TRACING) += clock.o trace.o events.o
+hyp-obj-$(CONFIG_NVHE_EL2_TRACING) += trace.o events.o
hyp-obj-y += $(lib-objs)
# Path to simple_ring_buffer.c
diff --git a/arch/arm64/kvm/hyp/nvhe/clock.c b/arch/arm64/kvm/hyp/nvhe/clock.c
index f3e2619db4e4..43d2cba4f810 100644
--- a/arch/arm64/kvm/hyp/nvhe/clock.c
+++ b/arch/arm64/kvm/hyp/nvhe/clock.c
@@ -8,7 +8,12 @@
#include <asm/arch_timer.h>
#include <asm/div64.h>
+#include <linux/math64.h>
+#include <vdso/time64.h>
+static u32 timer_freq;
+
+#ifdef CONFIG_NVHE_EL2_TRACING
static struct clock_data {
struct {
u32 mult;
@@ -66,3 +71,27 @@ u64 trace_hyp_clock(void)
return (u64)ns + clock->data[bank].epoch_ns;
}
+#endif /* CONFIG_NVHE_EL2_TRACING */
+
+int hyp_clock_init(void)
+{
+ timer_freq = read_sysreg(cntfrq_el0);
+ /*
+ * KVM will not initialize if FW didn't set cntfrq_el0, that is already
+ * part of the boot protocol.
+ */
+ if (!timer_freq)
+ return -ENODEV;
+
+ /* Timer freq can't be larger than 1Ghz by spec. */
+ if (timer_freq > NSEC_PER_SEC)
+ return -EINVAL;
+
+ return 0;
+}
+
+/* Return time in ns. */
+u64 hyp_clock_ns(void)
+{
+ return mul_u64_u32_div(__arch_counter_get_cntvct(), NSEC_PER_SEC, timer_freq);
+}
diff --git a/arch/arm64/kvm/hyp/nvhe/setup.c b/arch/arm64/kvm/hyp/nvhe/setup.c
index 75b00c323310..970c5cf342f5 100644
--- a/arch/arm64/kvm/hyp/nvhe/setup.c
+++ b/arch/arm64/kvm/hyp/nvhe/setup.c
@@ -10,6 +10,7 @@
#include <asm/kvm_pgtable.h>
#include <asm/kvm_pkvm.h>
+#include <nvhe/clock.h>
#include <nvhe/early_alloc.h>
#include <nvhe/ffa.h>
#include <nvhe/gfp.h>
@@ -320,6 +321,10 @@ void __noreturn __pkvm_init_finalise(void)
if (ret)
goto out;
+ ret = hyp_clock_init();
+ if (ret)
+ goto out;
+
ret = fix_host_ownership();
if (ret)
goto out;
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v7 01/24] KVM: arm64: Add a generic clock
2026-07-15 11:58 ` [PATCH v7 01/24] KVM: arm64: Add a generic clock Mostafa Saleh
@ 2026-07-15 13:48 ` Vincent Donnefort
2026-07-15 14:13 ` Mostafa Saleh
0 siblings, 1 reply; 29+ messages in thread
From: Vincent Donnefort @ 2026-07-15 13:48 UTC (permalink / raw)
To: Mostafa Saleh
Cc: linux-arm-kernel, linux-kernel, kvmarm, iommu, catalin.marinas,
will, maz, oliver.upton, joey.gouly, suzuki.poulose, yuzenghui,
joro, jgg, mark.rutland, qperret, tabba, sebastianene, keirf
[...]
> diff --git a/arch/arm64/kvm/hyp/nvhe/clock.c b/arch/arm64/kvm/hyp/nvhe/clock.c
> index f3e2619db4e4..43d2cba4f810 100644
> --- a/arch/arm64/kvm/hyp/nvhe/clock.c
> +++ b/arch/arm64/kvm/hyp/nvhe/clock.c
> @@ -8,7 +8,12 @@
>
> #include <asm/arch_timer.h>
> #include <asm/div64.h>
> +#include <linux/math64.h>
> +#include <vdso/time64.h>
>
> +static u32 timer_freq;
> +
> +#ifdef CONFIG_NVHE_EL2_TRACING
> static struct clock_data {
> struct {
> u32 mult;
> @@ -66,3 +71,27 @@ u64 trace_hyp_clock(void)
>
> return (u64)ns + clock->data[bank].epoch_ns;
> }
> +#endif /* CONFIG_NVHE_EL2_TRACING */
> +
> +int hyp_clock_init(void)
> +{
> + timer_freq = read_sysreg(cntfrq_el0);
> + /*
> + * KVM will not initialize if FW didn't set cntfrq_el0, that is already
> + * part of the boot protocol.
> + */
> + if (!timer_freq)
> + return -ENODEV;
> +
> + /* Timer freq can't be larger than 1Ghz by spec. */
> + if (timer_freq > NSEC_PER_SEC)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +/* Return time in ns. */
> +u64 hyp_clock_ns(void)
> +{
> + return mul_u64_u32_div(__arch_counter_get_cntvct(), NSEC_PER_SEC, timer_freq);
IIUC, this will overflow the u64 mult very quickly (in few minutes) and also I
see that we don't need such small nanoseconds accuracy.
So here we could always fallback to 128-bits mult... or update the epoch from
time to time. But I have something completely different to propose:
Instead of using a "clock" how about we just modify smmu_wait?
#define smmu_wait() {
static u32 window = arch_timer_get_cntfrq() / ARM_SMMU_EL2_POLL_TIMEOUT_US
u64 timeout = __arch_counter_get_cntvct() + window;
u64 cur;
...
while (!(__cond)) {
...
cur = __arch_counter_get_cntvct();
if (cur >= timeout)
__ret = -ETIMEOUT;
No risk of overflowing u64
No init necessary
> +}
> diff --git a/arch/arm64/kvm/hyp/nvhe/setup.c b/arch/arm64/kvm/hyp/nvhe/setup.c
> index 75b00c323310..970c5cf342f5 100644
> --- a/arch/arm64/kvm/hyp/nvhe/setup.c
> +++ b/arch/arm64/kvm/hyp/nvhe/setup.c
> @@ -10,6 +10,7 @@
> #include <asm/kvm_pgtable.h>
> #include <asm/kvm_pkvm.h>
>
> +#include <nvhe/clock.h>
> #include <nvhe/early_alloc.h>
> #include <nvhe/ffa.h>
> #include <nvhe/gfp.h>
> @@ -320,6 +321,10 @@ void __noreturn __pkvm_init_finalise(void)
> if (ret)
> goto out;
>
> + ret = hyp_clock_init();
> + if (ret)
> + goto out;
> +
> ret = fix_host_ownership();
> if (ret)
> goto out;
> --
> 2.55.0.141.g00534a21ce-goog
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v7 01/24] KVM: arm64: Add a generic clock
2026-07-15 13:48 ` Vincent Donnefort
@ 2026-07-15 14:13 ` Mostafa Saleh
2026-07-15 14:34 ` Vincent Donnefort
0 siblings, 1 reply; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 14:13 UTC (permalink / raw)
To: Vincent Donnefort
Cc: linux-arm-kernel, linux-kernel, kvmarm, iommu, catalin.marinas,
will, maz, oliver.upton, joey.gouly, suzuki.poulose, yuzenghui,
joro, jgg, mark.rutland, qperret, tabba, sebastianene, keirf
On Wed, Jul 15, 2026 at 02:48:50PM +0100, Vincent Donnefort wrote:
> [...]
>
> > diff --git a/arch/arm64/kvm/hyp/nvhe/clock.c b/arch/arm64/kvm/hyp/nvhe/clock.c
> > index f3e2619db4e4..43d2cba4f810 100644
> > --- a/arch/arm64/kvm/hyp/nvhe/clock.c
> > +++ b/arch/arm64/kvm/hyp/nvhe/clock.c
> > @@ -8,7 +8,12 @@
> >
> > #include <asm/arch_timer.h>
> > #include <asm/div64.h>
> > +#include <linux/math64.h>
> > +#include <vdso/time64.h>
> >
> > +static u32 timer_freq;
> > +
> > +#ifdef CONFIG_NVHE_EL2_TRACING
> > static struct clock_data {
> > struct {
> > u32 mult;
> > @@ -66,3 +71,27 @@ u64 trace_hyp_clock(void)
> >
> > return (u64)ns + clock->data[bank].epoch_ns;
> > }
> > +#endif /* CONFIG_NVHE_EL2_TRACING */
> > +
> > +int hyp_clock_init(void)
> > +{
> > + timer_freq = read_sysreg(cntfrq_el0);
> > + /*
> > + * KVM will not initialize if FW didn't set cntfrq_el0, that is already
> > + * part of the boot protocol.
> > + */
> > + if (!timer_freq)
> > + return -ENODEV;
> > +
> > + /* Timer freq can't be larger than 1Ghz by spec. */
> > + if (timer_freq > NSEC_PER_SEC)
> > + return -EINVAL;
> > +
> > + return 0;
> > +}
> > +
> > +/* Return time in ns. */
> > +u64 hyp_clock_ns(void)
> > +{
> > + return mul_u64_u32_div(__arch_counter_get_cntvct(), NSEC_PER_SEC, timer_freq);
>
> IIUC, this will overflow the u64 mult very quickly (in few minutes) and also I
> see that we don't need such small nanoseconds accuracy.
>
> So here we could always fallback to 128-bits mult... or update the epoch from
> time to time. But I have something completely different to propose:
>
It should not overflow because mul_u64_u32_div() handles this.
> Instead of using a "clock" how about we just modify smmu_wait?
>
> #define smmu_wait() {
> static u32 window = arch_timer_get_cntfrq() / ARM_SMMU_EL2_POLL_TIMEOUT_US
> u64 timeout = __arch_counter_get_cntvct() + window;
> u64 cur;
>
> ...
>
> while (!(__cond)) {
> ...
>
> cur = __arch_counter_get_cntvct();
> if (cur >= timeout)
> __ret = -ETIMEOUT;
>
>
> No risk of overflowing u64
> No init necessary
It believe init will be needed as caching arch_timer_get_cntfrq()
is much better that re-reading everytime. But I can make all of this
contained in the SMMUv3 driver and remove this patch.
Thanks,
Mostafa
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v7 01/24] KVM: arm64: Add a generic clock
2026-07-15 14:13 ` Mostafa Saleh
@ 2026-07-15 14:34 ` Vincent Donnefort
0 siblings, 0 replies; 29+ messages in thread
From: Vincent Donnefort @ 2026-07-15 14:34 UTC (permalink / raw)
To: Mostafa Saleh
Cc: linux-arm-kernel, linux-kernel, kvmarm, iommu, catalin.marinas,
will, maz, oliver.upton, joey.gouly, suzuki.poulose, yuzenghui,
joro, jgg, mark.rutland, qperret, tabba, sebastianene, keirf
[...]
> > #define smmu_wait() {
> > static u32 window = arch_timer_get_cntfrq() / ARM_SMMU_EL2_POLL_TIMEOUT_US
> > u64 timeout = __arch_counter_get_cntvct() + window;
> > u64 cur;
> >
> > ...
> >
> > while (!(__cond)) {
> > ...
> >
> > cur = __arch_counter_get_cntvct();
> > if (cur >= timeout)
> > __ret = -ETIMEOUT;
> >
> >
> > No risk of overflowing u64
> > No init necessary
>
> It believe init will be needed as caching arch_timer_get_cntfrq()
> is much better that re-reading everytime. But I can make all of this
> contained in the SMMUv3 driver and remove this patch.
That's why I have made window static :) (well of course it is per callsite...)
>
> Thanks,
> Mostafa
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v7 02/24] KVM: arm64: Donate MMIO to the hypervisor
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 01/24] KVM: arm64: Add a generic clock Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 17:26 ` Vincent Donnefort
2026-07-15 11:58 ` [PATCH v7 03/24] iommu/arm-smmu-v3: Split code with hyp Mostafa Saleh
` (21 subsequent siblings)
23 siblings, 1 reply; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Add a function to donate MMIO to the hypervisor so IOMMU hypervisor
drivers can protect and access the MMIO of IOMMUs.
As donating MMIO is very rare, and we don’t need to encode the full
state, it’s reasonable to have a separate function to do this.
It will init the host s2 page table with an invalid leaf with the owner ID
to prevent the host from mapping the page on faults.
Also, prevent kvm_pgtable_stage2_unmap() from removing owner ID from
stage-2 PTEs, as this can be triggered from recycle logic under memory
pressure. There is no code relying on this, as all ownership changes is
done via kvm_pgtable_stage2_set_owner()
For the error path in IOMMU drivers, add a function to donate MMIO
back from hyp to host. However, that leaks the hypervisor virtual
address range which should be acceptable as this is quite rare and
it matches the behaviour of fix_map/block.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
arch/arm64/kvm/hyp/include/nvhe/mem_protect.h | 7 ++
arch/arm64/kvm/hyp/nvhe/mem_protect.c | 91 ++++++++++++++++++-
arch/arm64/kvm/hyp/pgtable.c | 11 +--
3 files changed, 102 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h b/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
index 29935c7da1de..51b0eb3844a9 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
@@ -36,6 +36,13 @@ int __pkvm_guest_share_host(struct pkvm_hyp_vcpu *vcpu, u64 gfn);
int __pkvm_guest_unshare_host(struct pkvm_hyp_vcpu *vcpu, u64 gfn);
int __pkvm_host_unshare_hyp(u64 pfn);
int __pkvm_host_donate_hyp(u64 pfn, u64 nr_pages);
+/*
+ * Donate MMIO range to the hypervisor, it will be mapped in the hypervisor's
+ * private range and unmapped from the host stage-2.
+ */
+int __pkvm_host_donate_hyp_mmio(phys_addr_t addr, size_t size, unsigned long *haddr);
+/* Remaps MMIO range in the host, typically used in error path. */
+int __pkvm_hyp_donate_host_mmio(phys_addr_t addr, size_t size);
int __pkvm_hyp_donate_host(u64 pfn, u64 nr_pages);
int __pkvm_host_share_ffa(u64 pfn, u64 nr_pages);
int __pkvm_host_unshare_ffa(u64 pfn, u64 nr_pages);
diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
index 4e329e39a695..d803b3dd4cb4 100644
--- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
+++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
@@ -378,7 +378,11 @@ static int host_stage2_unmap_dev_all(void)
u64 addr = 0;
int i, ret;
- /* Unmap all non-memory regions to recycle the pages */
+ /*
+ * Unmap all non-memory regions to recycle the pages.
+ * That relies on kvm_pgtable_stage2_unmap() not clearing
+ * counted PTEs which include hypervisor MMIO.
+ */
for (i = 0; i < hyp_memblock_nr; i++, addr = reg->base + reg->size) {
reg = &hyp_memory[i];
ret = kvm_pgtable_stage2_unmap(pgt, addr, reg->base - addr);
@@ -1119,6 +1123,91 @@ int __pkvm_host_donate_hyp(u64 pfn, u64 nr_pages)
return ret;
}
+int __pkvm_host_donate_hyp_mmio(phys_addr_t addr, size_t size, unsigned long *haddr)
+{
+ kvm_pte_t pte;
+ u64 offset;
+ int ret;
+
+ /* Only before de-privilege. */
+ if (static_branch_unlikely(&kvm_protected_mode_initialized))
+ return -EPERM;
+
+ if (!PAGE_ALIGNED(addr | size) ||
+ !pfn_range_is_valid(hyp_phys_to_pfn(addr), size >> PAGE_SHIFT))
+ return -EINVAL;
+
+ ret = __pkvm_create_private_mapping(addr, size, PAGE_HYP_DEVICE, haddr);
+ if (ret)
+ return ret;
+
+ host_lock_component();
+ for (offset = 0; offset < size; offset += PAGE_SIZE) {
+ if (addr_is_memory(addr + offset)) {
+ ret = -EINVAL;
+ goto unlock;
+ }
+ ret = kvm_pgtable_get_leaf(&host_mmu.pgt, addr + offset, &pte, NULL);
+ if (ret)
+ goto unlock;
+ if (pte && !kvm_pte_valid(pte)) {
+ ret = -EPERM;
+ goto unlock;
+ }
+ }
+ /*
+ * We set HYP as the owner of the MMIO pages in the host stage-2, for:
+ * - host aborts: host_stage2_adjust_range() would fail for invalid non zero PTEs.
+ * - recycle under memory pressure: host_stage2_unmap_dev_all() would call
+ * kvm_pgtable_stage2_unmap() which will not clear non zero invalid ptes (counted).
+ * - other MMIO donation: Would fail as we check that the PTE is valid or empty.
+ */
+ ret = host_stage2_try(kvm_pgtable_stage2_annotate, &host_mmu.pgt,
+ addr, size, &host_s2_pool,
+ KVM_HOST_INVALID_PTE_TYPE_DONATION,
+ FIELD_PREP(KVM_HOST_DONATION_PTE_OWNER_MASK, PKVM_ID_HYP));
+unlock:
+ host_unlock_component();
+ return ret;
+}
+
+int __pkvm_hyp_donate_host_mmio(phys_addr_t addr, size_t size)
+{
+ kvm_pte_t pte;
+ u64 offset;
+ int ret = 0;
+
+ if (static_branch_unlikely(&kvm_protected_mode_initialized))
+ return -EPERM;
+
+ if (!PAGE_ALIGNED(addr | size) ||
+ !pfn_range_is_valid(hyp_phys_to_pfn(addr), size >> PAGE_SHIFT))
+ return -EINVAL;
+
+ host_lock_component();
+ for (offset = 0; offset < size; offset += PAGE_SIZE) {
+ if (addr_is_memory(addr + offset)) {
+ ret = -EINVAL;
+ goto unlock;
+ }
+ ret = kvm_pgtable_get_leaf(&host_mmu.pgt, addr + offset, &pte, NULL);
+ if (ret)
+ goto unlock;
+ if (!pte || kvm_pte_valid(pte)) {
+ ret = -EINVAL;
+ goto unlock;
+ }
+ if (FIELD_GET(KVM_HOST_DONATION_PTE_OWNER_MASK, pte) != PKVM_ID_HYP) {
+ ret = -EPERM;
+ goto unlock;
+ }
+ }
+ WARN_ON(host_stage2_idmap_locked(addr, size, PKVM_HOST_MMIO_PROT));
+unlock:
+ host_unlock_component();
+ return ret;
+}
+
int __pkvm_hyp_donate_host(u64 pfn, u64 nr_pages)
{
u64 phys = hyp_pfn_to_phys(pfn);
diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
index 91a7dfad6686..3073184cf6ad 100644
--- a/arch/arm64/kvm/hyp/pgtable.c
+++ b/arch/arm64/kvm/hyp/pgtable.c
@@ -1161,13 +1161,12 @@ static int stage2_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx,
kvm_pte_t *childp = NULL;
bool need_flush = false;
- if (!kvm_pte_valid(ctx->old)) {
- if (stage2_pte_is_counted(ctx->old)) {
- kvm_clear_pte(ctx->ptep);
- mm_ops->put_page(ctx->ptep);
- }
+ /*
+ * That also ignores stage2_pte_is_counted() instead of clearing
+ * the PTE as the MMIO can be owned by the hypervisor.
+ */
+ if (!kvm_pte_valid(ctx->old))
return 0;
- }
if (kvm_pte_table(ctx->old, ctx->level)) {
childp = kvm_pte_follow(ctx->old, mm_ops);
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v7 02/24] KVM: arm64: Donate MMIO to the hypervisor
2026-07-15 11:58 ` [PATCH v7 02/24] KVM: arm64: Donate MMIO to the hypervisor Mostafa Saleh
@ 2026-07-15 17:26 ` Vincent Donnefort
0 siblings, 0 replies; 29+ messages in thread
From: Vincent Donnefort @ 2026-07-15 17:26 UTC (permalink / raw)
To: Mostafa Saleh
Cc: linux-arm-kernel, linux-kernel, kvmarm, iommu, catalin.marinas,
will, maz, oliver.upton, joey.gouly, suzuki.poulose, yuzenghui,
joro, jgg, mark.rutland, qperret, tabba, sebastianene, keirf
On Wed, Jul 15, 2026 at 11:58:43AM +0000, Mostafa Saleh wrote:
> Add a function to donate MMIO to the hypervisor so IOMMU hypervisor
> drivers can protect and access the MMIO of IOMMUs.
>
> As donating MMIO is very rare, and we don’t need to encode the full
> state, it’s reasonable to have a separate function to do this.
> It will init the host s2 page table with an invalid leaf with the owner ID
> to prevent the host from mapping the page on faults.
>
> Also, prevent kvm_pgtable_stage2_unmap() from removing owner ID from
> stage-2 PTEs, as this can be triggered from recycle logic under memory
> pressure. There is no code relying on this, as all ownership changes is
> done via kvm_pgtable_stage2_set_owner()
>
> For the error path in IOMMU drivers, add a function to donate MMIO
> back from hyp to host. However, that leaks the hypervisor virtual
> address range which should be acceptable as this is quite rare and
> it matches the behaviour of fix_map/block.
>
> Signed-off-by: Mostafa Saleh <smostafa@google.com>
> ---
> arch/arm64/kvm/hyp/include/nvhe/mem_protect.h | 7 ++
> arch/arm64/kvm/hyp/nvhe/mem_protect.c | 91 ++++++++++++++++++-
> arch/arm64/kvm/hyp/pgtable.c | 11 +--
> 3 files changed, 102 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h b/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
> index 29935c7da1de..51b0eb3844a9 100644
> --- a/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
> +++ b/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
> @@ -36,6 +36,13 @@ int __pkvm_guest_share_host(struct pkvm_hyp_vcpu *vcpu, u64 gfn);
> int __pkvm_guest_unshare_host(struct pkvm_hyp_vcpu *vcpu, u64 gfn);
> int __pkvm_host_unshare_hyp(u64 pfn);
> int __pkvm_host_donate_hyp(u64 pfn, u64 nr_pages);
> +/*
> + * Donate MMIO range to the hypervisor, it will be mapped in the hypervisor's
> + * private range and unmapped from the host stage-2.
> + */
> +int __pkvm_host_donate_hyp_mmio(phys_addr_t addr, size_t size, unsigned long *haddr);
> +/* Remaps MMIO range in the host, typically used in error path. */
> +int __pkvm_hyp_donate_host_mmio(phys_addr_t addr, size_t size);
> int __pkvm_hyp_donate_host(u64 pfn, u64 nr_pages);
> int __pkvm_host_share_ffa(u64 pfn, u64 nr_pages);
> int __pkvm_host_unshare_ffa(u64 pfn, u64 nr_pages);
> diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
> index 4e329e39a695..d803b3dd4cb4 100644
> --- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
> +++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
> @@ -378,7 +378,11 @@ static int host_stage2_unmap_dev_all(void)
> u64 addr = 0;
> int i, ret;
>
> - /* Unmap all non-memory regions to recycle the pages */
> + /*
> + * Unmap all non-memory regions to recycle the pages.
> + * That relies on kvm_pgtable_stage2_unmap() not clearing
> + * counted PTEs which include hypervisor MMIO.
> + */
> for (i = 0; i < hyp_memblock_nr; i++, addr = reg->base + reg->size) {
> reg = &hyp_memory[i];
> ret = kvm_pgtable_stage2_unmap(pgt, addr, reg->base - addr);
> @@ -1119,6 +1123,91 @@ int __pkvm_host_donate_hyp(u64 pfn, u64 nr_pages)
> return ret;
> }
>
> +int __pkvm_host_donate_hyp_mmio(phys_addr_t addr, size_t size, unsigned long *haddr)
> +{
> + kvm_pte_t pte;
> + u64 offset;
> + int ret;
> +
> + /* Only before de-privilege. */
> + if (static_branch_unlikely(&kvm_protected_mode_initialized))
> + return -EPERM;
> +
> + if (!PAGE_ALIGNED(addr | size) ||
You wouldn't need that with u64 pfn, u64 nr_pages :)
> + !pfn_range_is_valid(hyp_phys_to_pfn(addr), size >> PAGE_SHIFT))
> + return -EINVAL;
> +
> + ret = __pkvm_create_private_mapping(addr, size, PAGE_HYP_DEVICE, haddr);
> + if (ret)
> + return ret;
> +
> + host_lock_component();
> + for (offset = 0; offset < size; offset += PAGE_SIZE) {
> + if (addr_is_memory(addr + offset)) {
> + ret = -EINVAL;
> + goto unlock;
> + }
> + ret = kvm_pgtable_get_leaf(&host_mmu.pgt, addr + offset, &pte, NULL);
> + if (ret)
> + goto unlock;
Is that called for big regions? because that looks quite inefficient even for
something that is init and IIRC we want to use this for GIC hardening too?
Perhaps it wouldn't be complicated to walk hyp_memory[] to make sure this
doesn't overlap any memory region. And then to reuse check_page_state_range() to
verify the host stage-2?
> + if (pte && !kvm_pte_valid(pte)) {
> + ret = -EPERM;
> + goto unlock;
> + }
> + }
> + /*
> + * We set HYP as the owner of the MMIO pages in the host stage-2, for:
> + * - host aborts: host_stage2_adjust_range() would fail for invalid non zero PTEs.
> + * - recycle under memory pressure: host_stage2_unmap_dev_all() would call
> + * kvm_pgtable_stage2_unmap() which will not clear non zero invalid ptes (counted).
> + * - other MMIO donation: Would fail as we check that the PTE is valid or empty.
> + */
Not sure we want that level of detail, it will probably become stall very
quickly. Perhaps we can simply say "the annotation is refcounted and protects
this region until it is released with __pkvm_hyp_donate_host_mmio()" or
something like that?
Also that makes me think, do we want to add this to the ownership_selftest?
> + ret = host_stage2_try(kvm_pgtable_stage2_annotate, &host_mmu.pgt,
> + addr, size, &host_s2_pool,
> + KVM_HOST_INVALID_PTE_TYPE_DONATION,
> + FIELD_PREP(KVM_HOST_DONATION_PTE_OWNER_MASK, PKVM_ID_HYP));
> +unlock:
> + host_unlock_component();
> + return ret;
> +}
> +
> +int __pkvm_hyp_donate_host_mmio(phys_addr_t addr, size_t size)
> +{
> + kvm_pte_t pte;
> + u64 offset;
> + int ret = 0;
> +
> + if (static_branch_unlikely(&kvm_protected_mode_initialized))
> + return -EPERM;
> +
> + if (!PAGE_ALIGNED(addr | size) ||
> + !pfn_range_is_valid(hyp_phys_to_pfn(addr), size >> PAGE_SHIFT))
> + return -EINVAL;
> +
> + host_lock_component();
> + for (offset = 0; offset < size; offset += PAGE_SIZE) {
> + if (addr_is_memory(addr + offset)) {
> + ret = -EINVAL;
> + goto unlock;
> + }
> + ret = kvm_pgtable_get_leaf(&host_mmu.pgt, addr + offset, &pte, NULL);
> + if (ret)
> + goto unlock;
> + if (!pte || kvm_pte_valid(pte)) {
> + ret = -EINVAL;
> + goto unlock;
> + }
> + if (FIELD_GET(KVM_HOST_DONATION_PTE_OWNER_MASK, pte) != PKVM_ID_HYP) {
> + ret = -EPERM;
> + goto unlock;
> + }
> + }
> + WARN_ON(host_stage2_idmap_locked(addr, size, PKVM_HOST_MMIO_PROT));
> +unlock:
> + host_unlock_component();
> + return ret;
> +}
> +
> int __pkvm_hyp_donate_host(u64 pfn, u64 nr_pages)
> {
> u64 phys = hyp_pfn_to_phys(pfn);
> diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
> index 91a7dfad6686..3073184cf6ad 100644
> --- a/arch/arm64/kvm/hyp/pgtable.c
> +++ b/arch/arm64/kvm/hyp/pgtable.c
> @@ -1161,13 +1161,12 @@ static int stage2_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx,
> kvm_pte_t *childp = NULL;
> bool need_flush = false;
>
> - if (!kvm_pte_valid(ctx->old)) {
> - if (stage2_pte_is_counted(ctx->old)) {
> - kvm_clear_pte(ctx->ptep);
> - mm_ops->put_page(ctx->ptep);
> - }
> + /*
> + * That also ignores stage2_pte_is_counted() instead of clearing
> + * the PTE as the MMIO can be owned by the hypervisor.
Not sure we should reference something pKVM specific in that code. Perhaps just
say we don't touch refcounted PTEs?
> + */
> + if (!kvm_pte_valid(ctx->old))
> return 0;
> - }
>
> if (kvm_pte_table(ctx->old, ctx->level)) {
> childp = kvm_pte_follow(ctx->old, mm_ops);
> --
> 2.55.0.141.g00534a21ce-goog
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v7 03/24] iommu/arm-smmu-v3: Split code with hyp
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 01/24] KVM: arm64: Add a generic clock Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 02/24] KVM: arm64: Donate MMIO to the hypervisor Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 04/24] iommu/arm-smmu-v3: Move TLB range invalidation into common code Mostafa Saleh
` (20 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
The KVM SMMUv3 driver would re-use some of the cmdq and ste code
inside the hypervisor, move these functions to the header file that
is shared between the host kernel and the hypervisor.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 59 --------------------
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 60 +++++++++++++++++++++
2 files changed, 60 insertions(+), 59 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index a10affb483a4..2a2289d4a3f3 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -125,33 +125,6 @@ static void parse_driver_options(struct arm_smmu_device *smmu)
}
/* Low-level queue manipulation functions */
-static bool queue_has_space(struct arm_smmu_ll_queue *q, u32 n)
-{
- u32 space, prod, cons;
-
- prod = Q_IDX(q, q->prod);
- cons = Q_IDX(q, q->cons);
-
- if (Q_WRP(q, q->prod) == Q_WRP(q, q->cons))
- space = (1 << q->max_n_shift) - (prod - cons);
- else
- space = cons - prod;
-
- return space >= n;
-}
-
-static bool queue_full(struct arm_smmu_ll_queue *q)
-{
- return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) &&
- Q_WRP(q, q->prod) != Q_WRP(q, q->cons);
-}
-
-static bool queue_empty(struct arm_smmu_ll_queue *q)
-{
- return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) &&
- Q_WRP(q, q->prod) == Q_WRP(q, q->cons);
-}
-
static bool queue_consumed(struct arm_smmu_ll_queue *q, u32 prod)
{
return ((Q_WRP(q, q->cons) == Q_WRP(q, prod)) &&
@@ -170,12 +143,6 @@ static void queue_sync_cons_out(struct arm_smmu_queue *q)
writel_relaxed(q->llq.cons, q->cons_reg);
}
-static void queue_inc_cons(struct arm_smmu_ll_queue *q)
-{
- u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1;
- q->cons = Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons);
-}
-
static void queue_sync_cons_ovf(struct arm_smmu_queue *q)
{
struct arm_smmu_ll_queue *llq = &q->llq;
@@ -207,12 +174,6 @@ static int queue_sync_prod_in(struct arm_smmu_queue *q)
return ret;
}
-static u32 queue_inc_prod_n(struct arm_smmu_ll_queue *q, int n)
-{
- u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + n;
- return Q_OVF(q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod);
-}
-
static void queue_poll_init(struct arm_smmu_device *smmu,
struct arm_smmu_queue_poll *qp)
{
@@ -240,14 +201,6 @@ static int queue_poll(struct arm_smmu_queue_poll *qp)
return 0;
}
-static void queue_write(__le64 *dst, u64 *src, size_t n_dwords)
-{
- int i;
-
- for (i = 0; i < n_dwords; ++i)
- *dst++ = cpu_to_le64(*src++);
-}
-
static void queue_read(u64 *dst, __le64 *src, size_t n_dwords)
{
int i;
@@ -1731,18 +1684,6 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_master *master)
}
/* Stream table manipulation functions */
-static void arm_smmu_write_strtab_l1_desc(struct arm_smmu_strtab_l1 *dst,
- dma_addr_t l2ptr_dma)
-{
- u64 val = 0;
-
- val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, STRTAB_SPLIT + 1);
- val |= l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK;
-
- /* The HW has 64 bit atomicity with stores to the L2 STE table */
- WRITE_ONCE(dst->l2ptr, cpu_to_le64(val));
-}
-
struct arm_smmu_ste_writer {
struct arm_smmu_entry_writer writer;
u32 sid;
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index c909c9a88538..e93489841ec7 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -1212,6 +1212,66 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,
struct arm_smmu_cmd *cmds, int n,
bool sync);
+/* Queue functions shared between kernel and hyp. */
+static inline bool queue_has_space(struct arm_smmu_ll_queue *q, u32 n)
+{
+ u32 space, prod, cons;
+
+ prod = Q_IDX(q, q->prod);
+ cons = Q_IDX(q, q->cons);
+
+ if (Q_WRP(q, q->prod) == Q_WRP(q, q->cons))
+ space = (1 << q->max_n_shift) - (prod - cons);
+ else
+ space = cons - prod;
+
+ return space >= n;
+}
+
+static inline bool queue_full(struct arm_smmu_ll_queue *q)
+{
+ return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) &&
+ Q_WRP(q, q->prod) != Q_WRP(q, q->cons);
+}
+
+static inline bool queue_empty(struct arm_smmu_ll_queue *q)
+{
+ return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) &&
+ Q_WRP(q, q->prod) == Q_WRP(q, q->cons);
+}
+
+static inline u32 queue_inc_prod_n(struct arm_smmu_ll_queue *q, int n)
+{
+ u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + n;
+ return Q_OVF(q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod);
+}
+
+static inline void queue_inc_cons(struct arm_smmu_ll_queue *q)
+{
+ u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1;
+ q->cons = Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons);
+}
+
+static inline void queue_write(__le64 *dst, u64 *src, size_t n_dwords)
+{
+ int i;
+
+ for (i = 0; i < n_dwords; ++i)
+ *dst++ = cpu_to_le64(*src++);
+}
+
+static inline void arm_smmu_write_strtab_l1_desc(struct arm_smmu_strtab_l1 *dst,
+ dma_addr_t l2ptr_dma)
+{
+ u64 val = 0;
+
+ val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, STRTAB_SPLIT + 1);
+ val |= l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK;
+
+ /* The HW has 64 bit atomicity with stores to the L2 STE table */
+ WRITE_ONCE(dst->l2ptr, cpu_to_le64(val));
+}
+
#ifdef CONFIG_ARM_SMMU_V3_SVA
bool arm_smmu_sva_supported(struct arm_smmu_device *smmu);
void arm_smmu_sva_notifier_synchronize(void);
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 04/24] iommu/arm-smmu-v3: Move TLB range invalidation into common code
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (2 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 03/24] iommu/arm-smmu-v3: Split code with hyp Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 05/24] iommu/arm-smmu-v3: Move IDR parsing to common functions Mostafa Saleh
` (19 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Range TLB invalidation has a very specific algorithm. Instead of
re-writing it for the hypervisor, move it to a function that can
be re-used.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 79 +++---------------
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 89 +++++++++++++++++++++
2 files changed, 102 insertions(+), 66 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 2a2289d4a3f3..cd17a3255312 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -2336,81 +2336,28 @@ static void arm_smmu_tlb_inv_context(void *cookie)
arm_smmu_domain_inv(smmu_domain);
}
+static void __arm_smmu_cmdq_batch_add(void *__opaque,
+ struct arm_smmu_cmdq_batch *cmds,
+ struct arm_smmu_cmd *cmd)
+{
+ struct arm_smmu_device *smmu = (struct arm_smmu_device *)__opaque;
+
+ arm_smmu_cmdq_batch_add_cmd_p(smmu, cmds, cmd);
+}
+
static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu,
struct arm_smmu_cmdq_batch *cmds,
struct arm_smmu_cmd *cmd, bool leaf,
unsigned long iova, size_t size,
size_t granule, size_t pgsize)
{
- unsigned long end = iova + size, num_pages = 0, tg = pgsize;
- u64 orig_data0 = cmd->data[0];
- size_t inv_range = granule;
- u8 ttl = 0, tg_enc = 0;
-
if (WARN_ON_ONCE(!size))
return;
- if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) {
- num_pages = size >> tg;
-
- /* Convert page size of 12,14,16 (log2) to 1,2,3 */
- tg_enc = (tg - 10) / 2;
-
- /*
- * Determine what level the granule is at. For non-leaf, both
- * io-pgtable and SVA pass a nominal last-level granule because
- * they don't know what level(s) actually apply, so ignore that
- * and leave TTL=0. However for various errata reasons we still
- * want to use a range command, so avoid the SVA corner case
- * where both scale and num could be 0 as well.
- */
- if (leaf)
- ttl = 4 - ((ilog2(granule) - 3) / (tg - 3));
- else if ((num_pages & CMDQ_TLBI_RANGE_NUM_MAX) == 1)
- num_pages++;
- }
-
- while (iova < end) {
- if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) {
- /*
- * On each iteration of the loop, the range is 5 bits
- * worth of the aligned size remaining.
- * The range in pages is:
- *
- * range = (num_pages & (0x1f << __ffs(num_pages)))
- */
- unsigned long scale, num;
-
- /* Determine the power of 2 multiple number of pages */
- scale = __ffs(num_pages);
-
- /* Determine how many chunks of 2^scale size we have */
- num = (num_pages >> scale) & CMDQ_TLBI_RANGE_NUM_MAX;
-
- cmd->data[0] = orig_data0 |
- FIELD_PREP(CMDQ_TLBI_0_NUM, num - 1) |
- FIELD_PREP(CMDQ_TLBI_0_SCALE, scale);
-
- /* range is num * 2^scale * pgsize */
- inv_range = num << (scale + tg);
-
- /* Clear out the lower order bits for the next iteration */
- num_pages -= num << scale;
- }
-
- /*
- * IPA has fewer bits than VA, but they are reserved in the
- * command and something would be very broken if iova had them
- * set.
- */
- cmd->data[1] = FIELD_PREP(CMDQ_TLBI_1_LEAF, leaf) |
- FIELD_PREP(CMDQ_TLBI_1_TTL, ttl) |
- FIELD_PREP(CMDQ_TLBI_1_TG, tg_enc) |
- (iova & ~GENMASK_U64(11, 0));
-
- arm_smmu_cmdq_batch_add_cmd_p(smmu, cmds, cmd);
- iova += inv_range;
- }
+ arm_smmu_tlb_inv_build(cmd, iova, size, granule, pgsize,
+ smmu->features & ARM_SMMU_FEAT_RANGE_INV,
+ smmu, leaf, __arm_smmu_cmdq_batch_add,
+ cmds);
}
static bool arm_smmu_inv_size_too_big(struct arm_smmu_device *smmu, size_t size,
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index e93489841ec7..494e55a2dc34 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -1272,6 +1272,95 @@ static inline void arm_smmu_write_strtab_l1_desc(struct arm_smmu_strtab_l1 *dst,
WRITE_ONCE(dst->l2ptr, cpu_to_le64(val));
}
+/**
+ * arm_smmu_tlb_inv_build - Create a range invalidation command
+ * @cmd: Base command initialized with OPCODE (S1, S2..), vmid and asid
+ * @iova: Start IOVA to invalidate
+ * @size: Size of range
+ * @granule: Granule of invalidation
+ * @pgsize: Page size of the invalidation
+ * @is_range: Use range invalidation commands
+ * @opaque: Pointer to pass to add_cmd
+ * @leaf: Is leaf invalidation
+ * @add_cmd: Function to send/batch the invalidation command
+ * @cmds: Incase of batching, it includes the pointer to the batch
+ */
+static inline void arm_smmu_tlb_inv_build(struct arm_smmu_cmd *cmd,
+ unsigned long iova, size_t size,
+ size_t granule, unsigned long pgsize,
+ bool is_range, void *opaque, bool leaf,
+ void (*add_cmd)(void *_opaque,
+ struct arm_smmu_cmdq_batch *cmds,
+ struct arm_smmu_cmd *cmd),
+ struct arm_smmu_cmdq_batch *cmds)
+{
+ unsigned long end = iova + size, num_pages = 0, tg = pgsize;
+ u64 orig_data0 = cmd->data[0];
+ size_t inv_range = granule;
+ u8 ttl = 0, tg_enc = 0;
+
+ if (is_range) {
+ num_pages = size >> tg;
+
+ /* Convert page size of 12,14,16 (log2) to 1,2,3 */
+ tg_enc = (tg - 10) / 2;
+
+ /*
+ * Determine what level the granule is at. For non-leaf, both
+ * io-pgtable and SVA pass a nominal last-level granule because
+ * they don't know what level(s) actually apply, so ignore that
+ * and leave TTL=0. However for various errata reasons we still
+ * want to use a range command, so avoid the SVA corner case
+ * where both scale and num could be 0 as well.
+ */
+ if (leaf)
+ ttl = 4 - ((ilog2(granule) - 3) / (tg - 3));
+ else if ((num_pages & CMDQ_TLBI_RANGE_NUM_MAX) == 1)
+ num_pages++;
+ }
+
+ while (iova < end) {
+ if (is_range) {
+ /*
+ * On each iteration of the loop, the range is 5 bits
+ * worth of the aligned size remaining.
+ * The range in pages is:
+ *
+ * range = (num_pages & (0x1f << __ffs(num_pages)))
+ */
+ unsigned long scale, num;
+
+ /* Determine the power of 2 multiple number of pages */
+ scale = __ffs(num_pages);
+
+ /* Determine how many chunks of 2^scale size we have */
+ num = (num_pages >> scale) & CMDQ_TLBI_RANGE_NUM_MAX;
+
+ cmd->data[0] = orig_data0 |
+ FIELD_PREP(CMDQ_TLBI_0_NUM, num - 1) |
+ FIELD_PREP(CMDQ_TLBI_0_SCALE, scale);
+
+ /* range is num * 2^scale * pgsize */
+ inv_range = num << (scale + tg);
+
+ /* Clear out the lower order bits for the next iteration */
+ num_pages -= num << scale;
+ }
+ /*
+ * IPA has fewer bits than VA, but they are reserved in the
+ * command and something would be very broken if iova had them
+ * set.
+ */
+ cmd->data[1] = FIELD_PREP(CMDQ_TLBI_1_LEAF, leaf) |
+ FIELD_PREP(CMDQ_TLBI_1_TTL, ttl) |
+ FIELD_PREP(CMDQ_TLBI_1_TG, tg_enc) |
+ (iova & ~GENMASK_U64(11, 0));
+
+ add_cmd(opaque, cmds, cmd);
+ iova += inv_range;
+ }
+}
+
#ifdef CONFIG_ARM_SMMU_V3_SVA
bool arm_smmu_sva_supported(struct arm_smmu_device *smmu);
void arm_smmu_sva_notifier_synchronize(void);
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 05/24] iommu/arm-smmu-v3: Move IDR parsing to common functions
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (3 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 04/24] iommu/arm-smmu-v3: Move TLB range invalidation into common code Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 06/24] KVM: arm64: iommu: Introduce IOMMU driver infrastructure Mostafa Saleh
` (18 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Move parsing of IDRs to functions so that it can be re-used
from the hypervisor.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
drivers/iommu/arm/arm-smmu-v3/Makefile | 2 +-
.../arm/arm-smmu-v3/arm-smmu-v3-common-lib.c | 184 ++++++++++++++++++
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 162 ++-------------
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 13 ++
4 files changed, 215 insertions(+), 146 deletions(-)
create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-common-lib.c
diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm-smmu-v3/Makefile
index 493a659cc66b..c9ce392e6d31 100644
--- a/drivers/iommu/arm/arm-smmu-v3/Makefile
+++ b/drivers/iommu/arm/arm-smmu-v3/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o
-arm_smmu_v3-y := arm-smmu-v3.o
+arm_smmu_v3-y := arm-smmu-v3.o arm-smmu-v3-common-lib.o
arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) += arm-smmu-v3-iommufd.o
arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) += tegra241-cmdqv.o
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-common-lib.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-common-lib.c
new file mode 100644
index 000000000000..ce0ad88b81e3
--- /dev/null
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-common-lib.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ * Arm SMMUv3 driver functions shared with hypervisor.
+ */
+
+#include "arm-smmu-v3.h"
+#include <asm-generic/errno-base.h>
+
+#include <linux/string.h>
+
+u32 smmu_idr0_features(u32 reg)
+{
+ u32 features = 0;
+
+ /* 2-level structures */
+ if (FIELD_GET(IDR0_ST_LVL, reg) == IDR0_ST_LVL_2LVL)
+ features |= ARM_SMMU_FEAT_2_LVL_STRTAB;
+
+ if (reg & IDR0_CD2L)
+ features |= ARM_SMMU_FEAT_2_LVL_CDTAB;
+
+ /*
+ * Translation table endianness.
+ * We currently require the same endianness as the CPU, but this
+ * could be changed later by adding a new IO_PGTABLE_QUIRK.
+ */
+ switch (FIELD_GET(IDR0_TTENDIAN, reg)) {
+ case IDR0_TTENDIAN_MIXED:
+ features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE;
+ break;
+#ifdef __BIG_ENDIAN
+ case IDR0_TTENDIAN_BE:
+ features |= ARM_SMMU_FEAT_TT_BE;
+ break;
+#else
+ case IDR0_TTENDIAN_LE:
+ features |= ARM_SMMU_FEAT_TT_LE;
+ break;
+#endif
+ }
+
+ /* Boolean feature flags */
+ if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI)
+ features |= ARM_SMMU_FEAT_PRI;
+
+ if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS)
+ features |= ARM_SMMU_FEAT_ATS;
+
+ if (reg & IDR0_SEV)
+ features |= ARM_SMMU_FEAT_SEV;
+
+ if (reg & IDR0_MSI)
+ features |= ARM_SMMU_FEAT_MSI;
+
+ if (reg & IDR0_HYP)
+ features |= ARM_SMMU_FEAT_HYP;
+
+ switch (FIELD_GET(IDR0_STALL_MODEL, reg)) {
+ case IDR0_STALL_MODEL_FORCE:
+ features |= ARM_SMMU_FEAT_STALL_FORCE;
+ fallthrough;
+ case IDR0_STALL_MODEL_STALL:
+ features |= ARM_SMMU_FEAT_STALLS;
+ }
+
+ if (reg & IDR0_S1P)
+ features |= ARM_SMMU_FEAT_TRANS_S1;
+
+ if (reg & IDR0_S2P)
+ features |= ARM_SMMU_FEAT_TRANS_S2;
+
+ if ((features & ARM_SMMU_FEAT_TRANS_S1) &&
+ (features & ARM_SMMU_FEAT_TRANS_S2))
+ features |= ARM_SMMU_FEAT_NESTING;
+
+ return features;
+}
+
+u32 smmu_idr3_features(u32 reg)
+{
+ u32 features = 0;
+
+ if (FIELD_GET(IDR3_RIL, reg))
+ features |= ARM_SMMU_FEAT_RANGE_INV;
+ if (FIELD_GET(IDR3_FWB, reg))
+ features |= ARM_SMMU_FEAT_S2FWB;
+ if (FIELD_GET(IDR3_BBM, reg) == 2)
+ features |= ARM_SMMU_FEAT_BBML2;
+ return features;
+}
+
+u32 smmu_idr5_to_oas(u32 reg)
+{
+ switch (FIELD_GET(IDR5_OAS, reg)) {
+ case IDR5_OAS_32_BIT:
+ return 32;
+ case IDR5_OAS_36_BIT:
+ return 36;
+ case IDR5_OAS_40_BIT:
+ return 40;
+ case IDR5_OAS_42_BIT:
+ return 42;
+ case IDR5_OAS_44_BIT:
+ return 44;
+ case IDR5_OAS_48_BIT:
+ return 48;
+ case IDR5_OAS_52_BIT:
+ return 52;
+ }
+ return 0;
+}
+
+unsigned long smmu_idr5_to_pgsize(u32 reg)
+{
+ unsigned long pgsize_bitmap = 0;
+
+ if (reg & IDR5_GRAN64K)
+ pgsize_bitmap |= SZ_64K | SZ_512M;
+ if (reg & IDR5_GRAN16K)
+ pgsize_bitmap |= SZ_16K | SZ_32M;
+ if (reg & IDR5_GRAN4K)
+ pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
+ return pgsize_bitmap;
+}
+
+unsigned long smmu_iidr_features(u32 reg, unsigned long features)
+{
+ unsigned int implementer, productid, variant, revision;
+
+ implementer = FIELD_GET(IIDR_IMPLEMENTER, reg);
+ productid = FIELD_GET(IIDR_PRODUCTID, reg);
+ variant = FIELD_GET(IIDR_VARIANT, reg);
+ revision = FIELD_GET(IIDR_REVISION, reg);
+
+ switch (implementer) {
+ case IIDR_IMPLEMENTER_ARM:
+ switch (productid) {
+ case IIDR_PRODUCTID_ARM_MMU_600:
+ /* Arm erratum 1076982 */
+ if (variant == 0 && revision <= 2)
+ features &= ~ARM_SMMU_FEAT_SEV;
+ /* Arm erratum 1209401 */
+ if (variant < 2)
+ features &= ~ARM_SMMU_FEAT_NESTING;
+ break;
+ case IIDR_PRODUCTID_ARM_MMU_700:
+ /* Many errata... */
+ features &= ~ARM_SMMU_FEAT_BTM;
+ if (variant < 1 || revision < 1) {
+ /* Arm errata 2268618, 2812531 */
+ features &= ~ARM_SMMU_FEAT_NESTING;
+ }
+ break;
+ case IIDR_PRODUCTID_ARM_MMU_L1:
+ case IIDR_PRODUCTID_ARM_MMU_S3:
+ /* Arm errata 3878312/3995052 */
+ features &= ~ARM_SMMU_FEAT_BTM;
+ break;
+ }
+ break;
+ }
+ return features;
+}
+
+unsigned long smmu_iidr_options(u32 reg, unsigned long options)
+{
+ unsigned int implementer, productid, variant, revision;
+
+ implementer = FIELD_GET(IIDR_IMPLEMENTER, reg);
+ productid = FIELD_GET(IIDR_PRODUCTID, reg);
+ variant = FIELD_GET(IIDR_VARIANT, reg);
+ revision = FIELD_GET(IIDR_REVISION, reg);
+
+ if ((implementer == IIDR_IMPLEMENTER_ARM) &&
+ (productid == IIDR_PRODUCTID_ARM_MMU_700) &&
+ (variant < 1 || revision < 1)) {
+ /* Arm erratum 2812531 */
+ options |= ARM_SMMU_OPT_CMDQ_FORCE_SYNC;
+ }
+ return options;
+}
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index cd17a3255312..674ff98706f6 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -4759,52 +4759,13 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
return 0;
}
-#define IIDR_IMPLEMENTER_ARM 0x43b
-#define IIDR_PRODUCTID_ARM_MMU_600 0x483
-#define IIDR_PRODUCTID_ARM_MMU_700 0x487
-#define IIDR_PRODUCTID_ARM_MMU_L1 0x48a
-#define IIDR_PRODUCTID_ARM_MMU_S3 0x498
-
static void arm_smmu_device_iidr_probe(struct arm_smmu_device *smmu)
{
u32 reg;
- unsigned int implementer, productid, variant, revision;
reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR);
- implementer = FIELD_GET(IIDR_IMPLEMENTER, reg);
- productid = FIELD_GET(IIDR_PRODUCTID, reg);
- variant = FIELD_GET(IIDR_VARIANT, reg);
- revision = FIELD_GET(IIDR_REVISION, reg);
-
- switch (implementer) {
- case IIDR_IMPLEMENTER_ARM:
- switch (productid) {
- case IIDR_PRODUCTID_ARM_MMU_600:
- /* Arm erratum 1076982 */
- if (variant == 0 && revision <= 2)
- smmu->features &= ~ARM_SMMU_FEAT_SEV;
- /* Arm erratum 1209401 */
- if (variant < 2)
- smmu->features &= ~ARM_SMMU_FEAT_NESTING;
- break;
- case IIDR_PRODUCTID_ARM_MMU_700:
- /* Many errata... */
- smmu->features &= ~ARM_SMMU_FEAT_BTM;
- if (variant < 1 || revision < 1) {
- /* Arm erratum 2812531 */
- smmu->options |= ARM_SMMU_OPT_CMDQ_FORCE_SYNC;
- /* Arm errata 2268618, 2812531 */
- smmu->features &= ~ARM_SMMU_FEAT_NESTING;
- }
- break;
- case IIDR_PRODUCTID_ARM_MMU_L1:
- case IIDR_PRODUCTID_ARM_MMU_S3:
- /* Arm errata 3878312/3995052 */
- smmu->features &= ~ARM_SMMU_FEAT_BTM;
- break;
- }
- break;
- }
+ smmu->features = smmu_iidr_features(reg, smmu->features);
+ smmu->options = smmu_iidr_options(reg, smmu->options);
}
static void arm_smmu_get_httu(struct arm_smmu_device *smmu, u32 reg)
@@ -4837,57 +4798,17 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
/* IDR0 */
reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0);
- /* 2-level structures */
- if (FIELD_GET(IDR0_ST_LVL, reg) == IDR0_ST_LVL_2LVL)
- smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB;
-
- if (reg & IDR0_CD2L)
- smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB;
-
- /*
- * Translation table endianness.
- * We currently require the same endianness as the CPU, but this
- * could be changed later by adding a new IO_PGTABLE_QUIRK.
- */
- switch (FIELD_GET(IDR0_TTENDIAN, reg)) {
- case IDR0_TTENDIAN_MIXED:
- smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE;
- break;
-#ifdef __BIG_ENDIAN
- case IDR0_TTENDIAN_BE:
- smmu->features |= ARM_SMMU_FEAT_TT_BE;
- break;
-#else
- case IDR0_TTENDIAN_LE:
- smmu->features |= ARM_SMMU_FEAT_TT_LE;
- break;
-#endif
- default:
+ smmu->features |= smmu_idr0_features(reg);
+ if (!(smmu->features & (ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE))) {
dev_err(smmu->dev, "unknown/unsupported TT endianness!\n");
return -ENXIO;
}
-
- /* Boolean feature flags */
- if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI)
- smmu->features |= ARM_SMMU_FEAT_PRI;
-
- if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS)
- smmu->features |= ARM_SMMU_FEAT_ATS;
-
- if (reg & IDR0_SEV)
- smmu->features |= ARM_SMMU_FEAT_SEV;
-
- if (reg & IDR0_MSI) {
- smmu->features |= ARM_SMMU_FEAT_MSI;
- if (coherent && !disable_msipolling)
- smmu->options |= ARM_SMMU_OPT_MSIPOLL;
- }
-
- if (reg & IDR0_HYP) {
- smmu->features |= ARM_SMMU_FEAT_HYP;
- if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN))
- smmu->features |= ARM_SMMU_FEAT_E2H;
- }
+ if (coherent && !disable_msipolling &&
+ smmu->features & ARM_SMMU_FEAT_MSI)
+ smmu->options |= ARM_SMMU_OPT_MSIPOLL;
+ if (smmu->features & ARM_SMMU_FEAT_HYP &&
+ cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN))
+ smmu->features |= ARM_SMMU_FEAT_E2H;
arm_smmu_get_httu(smmu, reg);
@@ -4899,21 +4820,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n",
str_true_false(coherent));
- switch (FIELD_GET(IDR0_STALL_MODEL, reg)) {
- case IDR0_STALL_MODEL_FORCE:
- smmu->features |= ARM_SMMU_FEAT_STALL_FORCE;
- fallthrough;
- case IDR0_STALL_MODEL_STALL:
- smmu->features |= ARM_SMMU_FEAT_STALLS;
- }
-
- if (reg & IDR0_S1P)
- smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
-
- if (reg & IDR0_S2P)
- smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
-
- if (!(reg & (IDR0_S1P | IDR0_S2P))) {
+ if (!(smmu->features & (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
dev_err(smmu->dev, "no translation support!\n");
return -ENXIO;
}
@@ -4972,13 +4879,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
/* IDR3 */
reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3);
- if (FIELD_GET(IDR3_RIL, reg))
- smmu->features |= ARM_SMMU_FEAT_RANGE_INV;
- if (FIELD_GET(IDR3_FWB, reg))
- smmu->features |= ARM_SMMU_FEAT_S2FWB;
-
- if (FIELD_GET(IDR3_BBM, reg) == 2)
- smmu->features |= ARM_SMMU_FEAT_BBML2;
+ smmu->features |= smmu_idr3_features(reg);
/* IDR5 */
reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5);
@@ -4987,43 +4888,18 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg);
/* Page sizes */
- if (reg & IDR5_GRAN64K)
- smmu->pgsize_bitmap |= SZ_64K | SZ_512M;
- if (reg & IDR5_GRAN16K)
- smmu->pgsize_bitmap |= SZ_16K | SZ_32M;
- if (reg & IDR5_GRAN4K)
- smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
+ smmu->pgsize_bitmap = smmu_idr5_to_pgsize(reg);
/* Input address size */
if (FIELD_GET(IDR5_VAX, reg) == IDR5_VAX_52_BIT)
smmu->features |= ARM_SMMU_FEAT_VAX;
- /* Output address size */
- switch (FIELD_GET(IDR5_OAS, reg)) {
- case IDR5_OAS_32_BIT:
- smmu->oas = 32;
- break;
- case IDR5_OAS_36_BIT:
- smmu->oas = 36;
- break;
- case IDR5_OAS_40_BIT:
- smmu->oas = 40;
- break;
- case IDR5_OAS_42_BIT:
- smmu->oas = 42;
- break;
- case IDR5_OAS_44_BIT:
- smmu->oas = 44;
- break;
- case IDR5_OAS_52_BIT:
- smmu->oas = 52;
+ smmu->oas = smmu_idr5_to_oas(reg);
+ if (smmu->oas == 52)
smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */
- break;
- default:
+ else if (!smmu->oas) {
dev_info(smmu->dev,
- "unknown output address size. Truncating to 48-bit\n");
- fallthrough;
- case IDR5_OAS_48_BIT:
+ "unknown output address size. Truncating to 48-bit\n");
smmu->oas = 48;
}
@@ -5032,10 +4908,6 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
dev_warn(smmu->dev,
"failed to set DMA mask for table walker\n");
- if ((smmu->features & ARM_SMMU_FEAT_TRANS_S1) &&
- (smmu->features & ARM_SMMU_FEAT_TRANS_S2))
- smmu->features |= ARM_SMMU_FEAT_NESTING;
-
arm_smmu_device_iidr_probe(smmu);
if (arm_smmu_sva_supported(smmu))
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 494e55a2dc34..842d0c9b883c 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -84,6 +84,12 @@ struct arm_vsmmu;
#define IIDR_REVISION GENMASK(15, 12)
#define IIDR_IMPLEMENTER GENMASK(11, 0)
+#define IIDR_IMPLEMENTER_ARM 0x43b
+#define IIDR_PRODUCTID_ARM_MMU_600 0x483
+#define IIDR_PRODUCTID_ARM_MMU_700 0x487
+#define IIDR_PRODUCTID_ARM_MMU_L1 0x48a
+#define IIDR_PRODUCTID_ARM_MMU_S3 0x498
+
#define ARM_SMMU_AIDR 0x1C
#define ARM_SMMU_CR0 0x20
@@ -1212,6 +1218,13 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,
struct arm_smmu_cmd *cmds, int n,
bool sync);
+u32 smmu_idr0_features(u32 reg);
+u32 smmu_idr3_features(u32 reg);
+u32 smmu_idr5_to_oas(u32 reg);
+unsigned long smmu_idr5_to_pgsize(u32 reg);
+unsigned long smmu_iidr_features(u32 reg, unsigned long features);
+unsigned long smmu_iidr_options(u32 reg, unsigned long options);
+
/* Queue functions shared between kernel and hyp. */
static inline bool queue_has_space(struct arm_smmu_ll_queue *q, u32 n)
{
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 06/24] KVM: arm64: iommu: Introduce IOMMU driver infrastructure
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (4 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 05/24] iommu/arm-smmu-v3: Move IDR parsing to common functions Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 07/24] KVM: arm64: iommu: Shadow host stage-2 page table Mostafa Saleh
` (17 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh,
Jean-Philippe Brucker
To establish DMA isolation, KVM needs an IOMMU driver which provides
ops implemented at EL2.
Only one driver can be used and is registered with
pkvm_iommu_register_driver() by passing pointer to the ops.
This must be called before module_init() which is the point KVM
initializes.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
arch/arm64/include/asm/kvm_host.h | 5 +++++
arch/arm64/kvm/Makefile | 2 +-
arch/arm64/kvm/hyp/include/nvhe/iommu.h | 13 +++++++++++++
arch/arm64/kvm/hyp/nvhe/Makefile | 3 ++-
arch/arm64/kvm/hyp/nvhe/iommu.c | 19 +++++++++++++++++++
arch/arm64/kvm/hyp/nvhe/setup.c | 10 ++++++++++
arch/arm64/kvm/iommu.c | 25 +++++++++++++++++++++++++
7 files changed, 75 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/kvm/hyp/include/nvhe/iommu.h
create mode 100644 arch/arm64/kvm/hyp/nvhe/iommu.c
create mode 100644 arch/arm64/kvm/iommu.c
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index bae2c4f92ef5..43821767ccab 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -1711,4 +1711,9 @@ static __always_inline enum fgt_group_id __fgt_reg_to_group_id(enum vcpu_sysreg
long kvm_get_cap_for_kvm_ioctl(unsigned int ioctl, long *ext);
+#ifndef __KVM_NVHE_HYPERVISOR__
+struct pkvm_iommu_ops;
+int pkvm_iommu_register_driver(struct pkvm_iommu_ops *hyp_ops);
+#endif
+
#endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index 59612d2f277c..0ddef54f7434 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -24,7 +24,7 @@ kvm-y += arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \
vgic/vgic-mmio.o vgic/vgic-mmio-v2.o \
vgic/vgic-mmio-v3.o vgic/vgic-kvm-device.o \
vgic/vgic-its.o vgic/vgic-debug.o vgic/vgic-v3-nested.o \
- vgic/vgic-v5.o
+ vgic/vgic-v5.o iommu.o
kvm-$(CONFIG_HW_PERF_EVENTS) += pmu-emul.o pmu.o
kvm-$(CONFIG_ARM64_PTR_AUTH) += pauth.o
diff --git a/arch/arm64/kvm/hyp/include/nvhe/iommu.h b/arch/arm64/kvm/hyp/include/nvhe/iommu.h
new file mode 100644
index 000000000000..df3d0cc5d4db
--- /dev/null
+++ b/arch/arm64/kvm/hyp/include/nvhe/iommu.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ARM64_KVM_NVHE_IOMMU_H__
+#define __ARM64_KVM_NVHE_IOMMU_H__
+
+#include <asm/kvm_host.h>
+
+struct pkvm_iommu_ops {
+ int (*init)(void);
+};
+
+int pkvm_iommu_init(void);
+
+#endif /* __ARM64_KVM_NVHE_IOMMU_H__ */
diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile
index 7c879292974d..b3e7473f18d2 100644
--- a/arch/arm64/kvm/hyp/nvhe/Makefile
+++ b/arch/arm64/kvm/hyp/nvhe/Makefile
@@ -24,7 +24,8 @@ CFLAGS_switch.nvhe.o += -Wno-override-init
hyp-obj-y := timer-sr.o sysreg-sr.o debug-sr.o switch.o tlb.o hyp-init.o host.o \
hyp-main.o hyp-smp.o psci-relay.o early_alloc.o page_alloc.o \
- cache.o setup.o mm.o mem_protect.o sys_regs.o pkvm.o stacktrace.o ffa.o
+ cache.o setup.o mm.o mem_protect.o sys_regs.o pkvm.o stacktrace.o ffa.o \
+ iommu.o
hyp-obj-y += ../vgic-v3-sr.o ../aarch32.o ../vgic-v2-cpuif-proxy.o ../entry.o \
../hyp-entry.o ../exception.o ../pgtable.o ../vgic-v5-sr.o clock.o
hyp-obj-y += ../../../kernel/smccc-call.o
diff --git a/arch/arm64/kvm/hyp/nvhe/iommu.c b/arch/arm64/kvm/hyp/nvhe/iommu.c
new file mode 100644
index 000000000000..ef456eff42d2
--- /dev/null
+++ b/arch/arm64/kvm/hyp/nvhe/iommu.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IOMMU operations for pKVM
+ *
+ * Copyright (C) 2022 Linaro Ltd.
+ */
+#include <nvhe/iommu.h>
+
+/* Only one set of ops supported */
+struct pkvm_iommu_ops *pkvm_iommu_ops;
+
+int pkvm_iommu_init(void)
+{
+ /* Keep DMA isolation optional. */
+ if (!pkvm_iommu_ops || !pkvm_iommu_ops->init)
+ return 0;
+
+ return pkvm_iommu_ops->init();
+}
diff --git a/arch/arm64/kvm/hyp/nvhe/setup.c b/arch/arm64/kvm/hyp/nvhe/setup.c
index 970c5cf342f5..c6698ecea4a2 100644
--- a/arch/arm64/kvm/hyp/nvhe/setup.c
+++ b/arch/arm64/kvm/hyp/nvhe/setup.c
@@ -14,6 +14,7 @@
#include <nvhe/early_alloc.h>
#include <nvhe/ffa.h>
#include <nvhe/gfp.h>
+#include <nvhe/iommu.h>
#include <nvhe/memory.h>
#include <nvhe/mem_protect.h>
#include <nvhe/mm.h>
@@ -333,6 +334,15 @@ void __noreturn __pkvm_init_finalise(void)
if (ret)
goto out;
+ /*
+ * IOMMU init is done at the the end as it setups and initializes many resources
+ * that would be leaked if the hypervisor fails after as there is no
+ * remove_iommu_driver() ops at the moment, that can be added later if necessary.
+ */
+ ret = pkvm_iommu_init();
+ if (ret)
+ goto out;
+
pkvm_hyp_vm_table_init(vm_table_base);
pkvm_ownership_selftest(selftest_base);
diff --git a/arch/arm64/kvm/iommu.c b/arch/arm64/kvm/iommu.c
new file mode 100644
index 000000000000..6492285012a4
--- /dev/null
+++ b/arch/arm64/kvm/iommu.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Google LLC
+ * Author: Mostafa Saleh <smostafa@google.com>
+ */
+
+#include <linux/kvm_host.h>
+
+extern struct pkvm_iommu_ops *kvm_nvhe_sym(pkvm_iommu_ops);
+
+static DEFINE_MUTEX(pkvm_iommu_reg_lock);
+
+int __init pkvm_iommu_register_driver(struct pkvm_iommu_ops *hyp_ops)
+{
+ guard(mutex)(&pkvm_iommu_reg_lock);
+
+ if (!is_protected_kvm_enabled() || is_kvm_arm_initialised())
+ return -EPERM;
+
+ if (kvm_nvhe_sym(pkvm_iommu_ops))
+ return -EBUSY;
+
+ kvm_nvhe_sym(pkvm_iommu_ops) = hyp_ops;
+ return 0;
+}
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 07/24] KVM: arm64: iommu: Shadow host stage-2 page table
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (5 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 06/24] KVM: arm64: iommu: Introduce IOMMU driver infrastructure Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 08/24] KVM: arm64: iommu: Add memory pool Mostafa Saleh
` (16 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Create a page-table for the IOMMU that shadows the host CPU stage-2
to establish DMA isolation.
An initial snapshot is created after the driver init, then
on every permission change a callback would be called for
the IOMMU driver to update the page table.
There are 3 different ways to add the callback:
1) In the high level memory transitions: (__pkvm_host_donate_hyp(),
__pkvm_host_donate_guest()...
2) In Lower level functions covering all transitions
- host_stage2_set_owner_metadata_locked() which covers:
- __pkvm_host_donate_hyp()
- __pkvm_host_donate_guest()
- __pkvm_host_donate_hyp()
- __pkvm_guest_unshare_host()
- host_stage2_set_owner_locked() only for ID_HOST which covers:
- __pkvm_hyp_donate_host()
- __pkvm_host_force_reclaim_page_guest()
- __pkvm_host_reclaim_page_guest()
- __pkvm_guest_share_host()
3) In the lowest level function __host_update_page_state(), which
requires only one callback. However, in that case the page state
is not enough as we might need to know the old state also.
Option #2 was implemented here.
For some cases, an SMMUv3 may be able to share the same page-table
used with the host CPU stage-2 directly.
However, this is too strict and requires changes to the core hypervisor
page-table code, plus it would require the hypervisor to handle IOMMU
page-faults. This can be added later as an optimization for SMMUV3.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
arch/arm64/kvm/hyp/include/nvhe/iommu.h | 4 +
arch/arm64/kvm/hyp/include/nvhe/mem_protect.h | 1 +
arch/arm64/kvm/hyp/nvhe/iommu.c | 129 +++++++++++++++++-
arch/arm64/kvm/hyp/nvhe/mem_protect.c | 27 ++--
4 files changed, 145 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/kvm/hyp/include/nvhe/iommu.h b/arch/arm64/kvm/hyp/include/nvhe/iommu.h
index df3d0cc5d4db..857d7dd2ebc3 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/iommu.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/iommu.h
@@ -3,11 +3,15 @@
#define __ARM64_KVM_NVHE_IOMMU_H__
#include <asm/kvm_host.h>
+#include <asm/kvm_pgtable.h>
struct pkvm_iommu_ops {
int (*init)(void);
+ int (*host_stage2_idmap)(phys_addr_t start, phys_addr_t end, int prot);
};
int pkvm_iommu_init(void);
+int pkvm_iommu_host_stage2_idmap(phys_addr_t start, phys_addr_t end,
+ enum kvm_pgtable_prot prot);
#endif /* __ARM64_KVM_NVHE_IOMMU_H__ */
diff --git a/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h b/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
index 51b0eb3844a9..99b821b3cf65 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
@@ -59,6 +59,7 @@ int __pkvm_host_test_clear_young_guest(u64 gfn, u64 nr_pages, bool mkold, struct
int __pkvm_host_mkyoung_guest(u64 gfn, struct pkvm_hyp_vcpu *vcpu);
bool addr_is_memory(phys_addr_t phys);
+
int host_stage2_idmap_locked(phys_addr_t addr, u64 size, enum kvm_pgtable_prot prot);
int host_stage2_set_owner_locked(phys_addr_t addr, u64 size, u8 owner_id);
int kvm_host_prepare_stage2(void *pgt_pool_base);
diff --git a/arch/arm64/kvm/hyp/nvhe/iommu.c b/arch/arm64/kvm/hyp/nvhe/iommu.c
index ef456eff42d2..08009609ec59 100644
--- a/arch/arm64/kvm/hyp/nvhe/iommu.c
+++ b/arch/arm64/kvm/hyp/nvhe/iommu.c
@@ -4,16 +4,137 @@
*
* Copyright (C) 2022 Linaro Ltd.
*/
+#include <linux/iommu.h>
+#include <asm/kvm_pkvm.h>
+
#include <nvhe/iommu.h>
+#include <nvhe/mem_protect.h>
+#include <nvhe/spinlock.h>
/* Only one set of ops supported */
struct pkvm_iommu_ops *pkvm_iommu_ops;
-int pkvm_iommu_init(void)
+/* Protected by host_mmu.lock */
+static bool pkvm_idmap_initialized;
+
+static inline int pkvm_to_iommu_prot(enum kvm_pgtable_prot prot)
{
- /* Keep DMA isolation optional. */
- if (!pkvm_iommu_ops || !pkvm_iommu_ops->init)
+ int iommu_prot = 0;
+
+ if (prot & KVM_PGTABLE_PROT_R)
+ iommu_prot |= IOMMU_READ;
+ if (prot & KVM_PGTABLE_PROT_W)
+ iommu_prot |= IOMMU_WRITE;
+
+ /* We don't understand that, might be dangerous. */
+ WARN_ON(prot & ~PKVM_HOST_MEM_PROT);
+ return iommu_prot;
+}
+
+/*
+ * IOMMU page tables are shadowed and not shared, that is mainly because:
+ * - Possible inconsistency between IOMMU and CPU features or format.
+ * - KVM relies on handling in page faults (BBM, lazy mapping).
+ */
+static int __snapshot_host_stage2(const struct kvm_pgtable_visit_ctx *ctx,
+ enum kvm_pgtable_walk_flags visit)
+{
+ u64 start = ctx->addr;
+ u64 block_end = ALIGN_DOWN(ctx->addr, kvm_granule_size(ctx->level)) +
+ kvm_granule_size(ctx->level);
+ u64 end = min(ctx->end, block_end);
+ kvm_pte_t pte = *ctx->ptep;
+ bool is_memory = *(bool *)ctx->arg;
+ int prot;
+
+ /*
+ * Keep annotated PTEs unmapped, and map everything else even lazily
+ * mapped PTEs(0), as the IOMMU can't handle page faults.
+ * That maps the whole address space which can be large, but that doesn't
+ * use a lot of memory as it will be mostly large block (1 GB with 4kb pages)
+ */
+ if (pte && !kvm_pte_valid(pte))
return 0;
- return pkvm_iommu_ops->init();
+ if (kvm_pte_valid(pte))
+ prot = pkvm_to_iommu_prot(kvm_pgtable_stage2_pte_prot(pte));
+ else
+ prot = IOMMU_READ | IOMMU_WRITE;
+
+ if (!is_memory)
+ prot |= IOMMU_MMIO;
+
+ return pkvm_iommu_ops->host_stage2_idmap(start, end, prot);
+}
+
+static int pkvm_iommu_snapshot_host_stage2(void)
+{
+ struct kvm_pgtable *pgt = &host_mmu.pgt;
+ bool is_memory;
+ struct kvm_pgtable_walker walker = {
+ .cb = __snapshot_host_stage2,
+ .flags = KVM_PGTABLE_WALK_LEAF,
+ .arg = &is_memory,
+ };
+ int ret = 0, i;
+ u64 start = 0;
+
+ hyp_spin_lock(&host_mmu.lock);
+ for (i = 0; i < hyp_memblock_nr; i++) {
+ struct memblock_region *reg = &hyp_memory[i];
+
+ if (start < reg->base) {
+ is_memory = false;
+ ret = kvm_pgtable_walk(pgt, start, reg->base - start, &walker);
+ if (ret)
+ goto out_unlock;
+ }
+
+ is_memory = true;
+ ret = kvm_pgtable_walk(pgt, reg->base, reg->size, &walker);
+ if (ret)
+ goto out_unlock;
+
+ start = reg->base + reg->size;
+ }
+
+ if (start < BIT(pgt->ia_bits)) {
+ is_memory = false;
+ ret = kvm_pgtable_walk(pgt, start, BIT(pgt->ia_bits) - start, &walker);
+ if (ret)
+ goto out_unlock;
+ }
+
+ pkvm_idmap_initialized = true;
+
+out_unlock:
+ hyp_spin_unlock(&host_mmu.lock);
+ return ret;
+}
+
+int pkvm_iommu_init(void)
+{
+ int ret;
+
+ /* Keep DMA isolation optional. */
+ if (!pkvm_iommu_ops || !pkvm_iommu_ops->init ||
+ !pkvm_iommu_ops->host_stage2_idmap)
+ return 0;
+
+ ret = pkvm_iommu_ops->init();
+ if (ret)
+ return ret;
+
+ return pkvm_iommu_snapshot_host_stage2();
+}
+
+int pkvm_iommu_host_stage2_idmap(phys_addr_t start, phys_addr_t end,
+ enum kvm_pgtable_prot prot)
+{
+ hyp_assert_lock_held(&host_mmu.lock);
+
+ if (!pkvm_idmap_initialized)
+ return 0;
+
+ return pkvm_iommu_ops->host_stage2_idmap(start, end, pkvm_to_iommu_prot(prot));
}
diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
index d803b3dd4cb4..ce610274bda0 100644
--- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
+++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
@@ -17,6 +17,7 @@
#include <nvhe/arm-smccc.h>
#include <nvhe/gfp.h>
+#include <nvhe/iommu.h>
#include <nvhe/memory.h>
#include <nvhe/mem_protect.h>
#include <nvhe/mm.h>
@@ -596,16 +597,15 @@ static int host_stage2_set_owner_metadata_locked(phys_addr_t addr, u64 size,
ret = host_stage2_try(kvm_pgtable_stage2_annotate, &host_mmu.pgt,
addr, size, &host_s2_pool,
KVM_HOST_INVALID_PTE_TYPE_DONATION, annotation);
- if (!ret) {
- /*
- * After stage2 maintenance has happened, but before the page
- * owner has changed.
- */
- pkvm_sme_dvmsync_fw_call();
- __host_update_page_state(addr, size, PKVM_NOPAGE);
- }
-
- return ret;
+ if (ret)
+ return ret;
+ /*
+ * After stage2 maintenance has happened, but before the page
+ * owner has changed.
+ */
+ pkvm_sme_dvmsync_fw_call();
+ __host_update_page_state(addr, size, PKVM_NOPAGE);
+ return pkvm_iommu_host_stage2_idmap(addr, addr + size, 0);
}
int host_stage2_set_owner_locked(phys_addr_t addr, u64 size, u8 owner_id)
@@ -618,8 +618,10 @@ int host_stage2_set_owner_locked(phys_addr_t addr, u64 size, u8 owner_id)
return -EPERM;
ret = host_stage2_idmap_locked(addr, size, PKVM_HOST_MEM_PROT);
- if (!ret)
- __host_update_page_state(addr, size, PKVM_PAGE_OWNED);
+ if (ret)
+ break;
+ __host_update_page_state(addr, size, PKVM_PAGE_OWNED);
+ ret = pkvm_iommu_host_stage2_idmap(addr, addr + size, PKVM_HOST_MEM_PROT);
break;
case PKVM_ID_HYP:
ret = host_stage2_set_owner_metadata_locked(addr, size,
@@ -1022,6 +1024,7 @@ int __pkvm_guest_share_host(struct pkvm_hyp_vcpu *vcpu, u64 gfn)
pkvm_mkstate(KVM_PGTABLE_PROT_RWX, PKVM_PAGE_SHARED_OWNED),
&vcpu->vcpu.arch.pkvm_memcache, 0));
WARN_ON(__host_set_page_state_range(phys, PAGE_SIZE, PKVM_PAGE_SHARED_BORROWED));
+ WARN_ON(pkvm_iommu_host_stage2_idmap(phys, phys + PAGE_SIZE, PKVM_HOST_MEM_PROT));
unlock:
guest_unlock_component(vm);
host_unlock_component();
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 08/24] KVM: arm64: iommu: Add memory pool
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (6 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 07/24] KVM: arm64: iommu: Shadow host stage-2 page table Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 09/24] KVM: arm64: iommu: Support DABT for IOMMU Mostafa Saleh
` (15 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
IOMMU drivers need to allocate memory for the shadow page table.
Similar to the host stage-2 CPU page table, the IOMMU pool
is allocated early from the carveout and it's memory is added to
a pool which the IOMMU driver can allocate from and reclaim to at
run time.
As this is too early for drivers to use initcalls, the number of
pages allocated is set from command line "kvm-arm.iommu_pgt_mem".
Later when the driver registers, it will pass how many pages it
needs, and if it was less than what was allocated, it will fail
to register.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../admin-guide/kernel-parameters.txt | 4 ++
arch/arm64/include/asm/kvm_host.h | 3 +-
arch/arm64/kvm/hyp/include/nvhe/iommu.h | 8 +++-
arch/arm64/kvm/hyp/nvhe/iommu.c | 21 +++++++++-
arch/arm64/kvm/hyp/nvhe/setup.c | 11 ++++-
arch/arm64/kvm/iommu.c | 42 ++++++++++++++++++-
arch/arm64/kvm/pkvm.c | 1 +
7 files changed, 85 insertions(+), 5 deletions(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index b5493a7f8f22..5cbac46bc941 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -3253,6 +3253,10 @@ Kernel parameters
trap: set WFI instruction trap
notrap: clear WFI instruction trap
+ kvm-arm.iommu_pgt_mem=nn[KMG]
+ [KVM, ARM, EARLY]
+ Memory allocated for the IOMMU pool from the KVM carveout
+ when running in protected mode.
kvm_cma_resv_ratio=n [PPC,EARLY]
Reserves given percentage from system memory area for
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 43821767ccab..8d3b4500b360 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -1713,7 +1713,8 @@ long kvm_get_cap_for_kvm_ioctl(unsigned int ioctl, long *ext);
#ifndef __KVM_NVHE_HYPERVISOR__
struct pkvm_iommu_ops;
-int pkvm_iommu_register_driver(struct pkvm_iommu_ops *hyp_ops);
+int pkvm_iommu_register_driver(struct pkvm_iommu_ops *hyp_ops, unsigned int nr_pages);
+unsigned int pkvm_iommu_pages(void);
#endif
#endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/kvm/hyp/include/nvhe/iommu.h b/arch/arm64/kvm/hyp/include/nvhe/iommu.h
index 857d7dd2ebc3..028e89a3448d 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/iommu.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/iommu.h
@@ -10,8 +10,14 @@ struct pkvm_iommu_ops {
int (*host_stage2_idmap)(phys_addr_t start, phys_addr_t end, int prot);
};
-int pkvm_iommu_init(void);
+int pkvm_iommu_init(void *pool_base, unsigned int nr_pages);
int pkvm_iommu_host_stage2_idmap(phys_addr_t start, phys_addr_t end,
enum kvm_pgtable_prot prot);
+
+/* Allocate pages from the IOMMU carveout, returns zeroed memory. */
+void *pkvm_iommu_donate_pages(u8 order);
+/* Free pages from pkvm_iommu_donate_pages(). Must use same size */
+void pkvm_iommu_reclaim_pages(void *ptr);
+
#endif /* __ARM64_KVM_NVHE_IOMMU_H__ */
diff --git a/arch/arm64/kvm/hyp/nvhe/iommu.c b/arch/arm64/kvm/hyp/nvhe/iommu.c
index 08009609ec59..8891cb7920c4 100644
--- a/arch/arm64/kvm/hyp/nvhe/iommu.c
+++ b/arch/arm64/kvm/hyp/nvhe/iommu.c
@@ -16,6 +16,7 @@ struct pkvm_iommu_ops *pkvm_iommu_ops;
/* Protected by host_mmu.lock */
static bool pkvm_idmap_initialized;
+static struct hyp_pool iommu_pages_pool;
static inline int pkvm_to_iommu_prot(enum kvm_pgtable_prot prot)
{
@@ -112,7 +113,7 @@ static int pkvm_iommu_snapshot_host_stage2(void)
return ret;
}
-int pkvm_iommu_init(void)
+int pkvm_iommu_init(void *pool_base, unsigned int nr_pages)
{
int ret;
@@ -121,6 +122,14 @@ int pkvm_iommu_init(void)
!pkvm_iommu_ops->host_stage2_idmap)
return 0;
+ if (!nr_pages)
+ return -ENOMEM;
+
+ ret = hyp_pool_init(&iommu_pages_pool, hyp_virt_to_pfn(pool_base),
+ nr_pages, 0);
+ if (ret)
+ return ret;
+
ret = pkvm_iommu_ops->init();
if (ret)
return ret;
@@ -138,3 +147,13 @@ int pkvm_iommu_host_stage2_idmap(phys_addr_t start, phys_addr_t end,
return pkvm_iommu_ops->host_stage2_idmap(start, end, pkvm_to_iommu_prot(prot));
}
+
+void *pkvm_iommu_donate_pages(u8 order)
+{
+ return hyp_alloc_pages(&iommu_pages_pool, order);
+}
+
+void pkvm_iommu_reclaim_pages(void *ptr)
+{
+ hyp_put_page(&iommu_pages_pool, ptr);
+}
diff --git a/arch/arm64/kvm/hyp/nvhe/setup.c b/arch/arm64/kvm/hyp/nvhe/setup.c
index c6698ecea4a2..39d59ff30f34 100644
--- a/arch/arm64/kvm/hyp/nvhe/setup.c
+++ b/arch/arm64/kvm/hyp/nvhe/setup.c
@@ -23,6 +23,8 @@
unsigned long hyp_nr_cpus;
+unsigned int hyp_kvm_iommu_pages;
+
#define hyp_percpu_size ((unsigned long)__per_cpu_end - \
(unsigned long)__per_cpu_start)
@@ -34,6 +36,7 @@ static void *selftest_base;
static void *ffa_proxy_pages;
static struct kvm_pgtable_mm_ops pkvm_pgtable_mm_ops;
static struct hyp_pool hpool;
+static void *iommu_base;
static int divide_memory_pool(void *virt, unsigned long size)
{
@@ -71,6 +74,12 @@ static int divide_memory_pool(void *virt, unsigned long size)
if (!ffa_proxy_pages)
return -ENOMEM;
+ if (hyp_kvm_iommu_pages) {
+ iommu_base = hyp_early_alloc_contig(hyp_kvm_iommu_pages);
+ if (!iommu_base)
+ return -ENOMEM;
+ }
+
return 0;
}
@@ -339,7 +348,7 @@ void __noreturn __pkvm_init_finalise(void)
* that would be leaked if the hypervisor fails after as there is no
* remove_iommu_driver() ops at the moment, that can be added later if necessary.
*/
- ret = pkvm_iommu_init();
+ ret = pkvm_iommu_init(iommu_base, hyp_kvm_iommu_pages);
if (ret)
goto out;
diff --git a/arch/arm64/kvm/iommu.c b/arch/arm64/kvm/iommu.c
index 6492285012a4..c80663b506c0 100644
--- a/arch/arm64/kvm/iommu.c
+++ b/arch/arm64/kvm/iommu.c
@@ -7,10 +7,11 @@
#include <linux/kvm_host.h>
extern struct pkvm_iommu_ops *kvm_nvhe_sym(pkvm_iommu_ops);
+extern unsigned int kvm_nvhe_sym(hyp_kvm_iommu_pages);
static DEFINE_MUTEX(pkvm_iommu_reg_lock);
-int __init pkvm_iommu_register_driver(struct pkvm_iommu_ops *hyp_ops)
+int pkvm_iommu_register_driver(struct pkvm_iommu_ops *hyp_ops, unsigned int nr_pages)
{
guard(mutex)(&pkvm_iommu_reg_lock);
@@ -20,6 +21,45 @@ int __init pkvm_iommu_register_driver(struct pkvm_iommu_ops *hyp_ops)
if (kvm_nvhe_sym(pkvm_iommu_ops))
return -EBUSY;
+ /* See kvm_iommu_pages() */
+ if (nr_pages > kvm_nvhe_sym(hyp_kvm_iommu_pages)) {
+ kvm_err("IOMMU pool needs 0x%x pages, check kvm-arm.iommu_pgt_mem", nr_pages);
+ return -ENOMEM;
+ }
+
kvm_nvhe_sym(pkvm_iommu_ops) = hyp_ops;
return 0;
}
+
+unsigned int pkvm_iommu_pages(void)
+{
+ /*
+ * This is used very early during setup_arch() before any initcalls
+ * or any drivers are registered.
+ * This value is set by a command line option.
+ * Later, when the driver is registered, it will pass the number
+ * pages needed for it's page tables, if it was more than what
+ * the system has already allocated, it will fail registration.
+ */
+ return kvm_nvhe_sym(hyp_kvm_iommu_pages);
+}
+
+/* Number of pages to reserve for iommu pool*/
+static int __init early_iommu_pgt_mem(char *arg)
+{
+ unsigned long long requested_size;
+
+ if (!arg)
+ return -EINVAL;
+
+ requested_size = memparse(arg, NULL);
+
+ if (requested_size > UINT_MAX) {
+ kvm_err("kvm-arm.iommu_pgt_mem is too large\n");
+ return -EINVAL;
+ }
+
+ kvm_nvhe_sym(hyp_kvm_iommu_pages) = requested_size >> PAGE_SHIFT;
+ return 0;
+}
+early_param("kvm-arm.iommu_pgt_mem", early_iommu_pgt_mem);
diff --git a/arch/arm64/kvm/pkvm.c b/arch/arm64/kvm/pkvm.c
index 053e4f733e4b..72ca1393c504 100644
--- a/arch/arm64/kvm/pkvm.c
+++ b/arch/arm64/kvm/pkvm.c
@@ -63,6 +63,7 @@ void __init kvm_hyp_reserve(void)
hyp_mem_pages += hyp_vmemmap_pages(STRUCT_HYP_PAGE_SIZE);
hyp_mem_pages += pkvm_selftest_pages();
hyp_mem_pages += hyp_ffa_proxy_pages();
+ hyp_mem_pages += pkvm_iommu_pages();
/*
* Try to allocate a PMD-aligned region to reduce TLB pressure once
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 09/24] KVM: arm64: iommu: Support DABT for IOMMU
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (7 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 08/24] KVM: arm64: iommu: Add memory pool Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 10/24] iommu/arm-smmu-v3-kvm: Add SMMUv3 driver Mostafa Saleh
` (14 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
The pKVM SMMUv3 driver needs to trap and emulate access to the MMIO
space of the SMMUv3 to provide emulation for the kernel driver.
Add a handler for DABTs for IOMMU drivers to be able to do so.
In case the host causes a data abort, check if it's part of IOMMU
emulation first.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
arch/arm64/kvm/hyp/include/nvhe/iommu.h | 3 ++-
arch/arm64/kvm/hyp/nvhe/iommu.c | 15 +++++++++++++++
arch/arm64/kvm/hyp/nvhe/mem_protect.c | 15 +++++++++++++++
3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/hyp/include/nvhe/iommu.h b/arch/arm64/kvm/hyp/include/nvhe/iommu.h
index 028e89a3448d..8b7521135792 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/iommu.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/iommu.h
@@ -8,6 +8,7 @@
struct pkvm_iommu_ops {
int (*init)(void);
int (*host_stage2_idmap)(phys_addr_t start, phys_addr_t end, int prot);
+ bool (*dabt_handler)(struct user_pt_regs *regs, u64 esr, u64 addr);
};
int pkvm_iommu_init(void *pool_base, unsigned int nr_pages);
@@ -19,5 +20,5 @@ int pkvm_iommu_host_stage2_idmap(phys_addr_t start, phys_addr_t end,
void *pkvm_iommu_donate_pages(u8 order);
/* Free pages from pkvm_iommu_donate_pages(). Must use same size */
void pkvm_iommu_reclaim_pages(void *ptr);
-
+bool pkvm_iommu_host_dabt_handler(struct user_pt_regs *regs, u64 esr, u64 addr);
#endif /* __ARM64_KVM_NVHE_IOMMU_H__ */
diff --git a/arch/arm64/kvm/hyp/nvhe/iommu.c b/arch/arm64/kvm/hyp/nvhe/iommu.c
index 8891cb7920c4..8ea9c8c23985 100644
--- a/arch/arm64/kvm/hyp/nvhe/iommu.c
+++ b/arch/arm64/kvm/hyp/nvhe/iommu.c
@@ -4,6 +4,10 @@
*
* Copyright (C) 2022 Linaro Ltd.
*/
+#include <asm/kvm_hyp.h>
+
+#include <hyp/adjust_pc.h>
+
#include <linux/iommu.h>
#include <asm/kvm_pkvm.h>
@@ -157,3 +161,14 @@ void pkvm_iommu_reclaim_pages(void *ptr)
{
hyp_put_page(&iommu_pages_pool, ptr);
}
+
+bool pkvm_iommu_host_dabt_handler(struct user_pt_regs *regs, u64 esr, u64 addr)
+{
+ if (pkvm_iommu_ops && pkvm_iommu_ops->dabt_handler &&
+ pkvm_iommu_ops->dabt_handler(regs, esr, addr)) {
+ /* DABT handled by the driver, skip to next instruction. */
+ kvm_skip_host_instr();
+ return true;
+ }
+ return false;
+}
diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
index ce610274bda0..b798a36e0ddb 100644
--- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
+++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
@@ -751,6 +751,12 @@ static void host_inject_mem_abort(struct kvm_cpu_context *host_ctxt)
inject_host_exception(esr);
}
+static bool is_mmio_dabt(u64 esr)
+{
+ return (ESR_ELx_EC(esr) == ESR_ELx_EC_DABT_LOW) &&
+ (esr & ESR_ELx_ISV);
+}
+
void handle_host_mem_abort(struct kvm_cpu_context *host_ctxt)
{
struct kvm_vcpu_fault_info fault;
@@ -773,6 +779,15 @@ void handle_host_mem_abort(struct kvm_cpu_context *host_ctxt)
BUG_ON(!(fault.hpfar_el2 & HPFAR_EL2_NS));
addr = FIELD_GET(HPFAR_EL2_FIPA, fault.hpfar_el2) << 12;
+ /*
+ * Emulate data aborts for IOMMU drivers, other access will be denied
+ * by host_stage2_adjust_range()
+ */
+ if (is_mmio_dabt(esr) && !addr_is_memory(addr) &&
+ pkvm_iommu_host_dabt_handler(&host_ctxt->regs,
+ esr, addr | FAR_TO_FIPA_OFFSET(fault.far_el2)))
+ return;
+
switch (host_stage2_idmap(addr)) {
case -EPERM:
host_inject_mem_abort(host_ctxt);
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 10/24] iommu/arm-smmu-v3-kvm: Add SMMUv3 driver
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (8 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 09/24] KVM: arm64: iommu: Support DABT for IOMMU Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 11/24] iommu/arm-smmu-v3-kvm: Add the kernel driver Mostafa Saleh
` (13 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Jean-Philippe Brucker,
Mostafa Saleh
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
Add the skeleton for an Arm SMMUv3 driver at EL2.
The driver rely on an array of SMMUv3s on the system, where at
init it will donate the array and the resources of the SMMUv3s
so they can't be changed by the host after de-privilege.
This array will be populated in the next patch.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
arch/arm64/kvm/hyp/nvhe/Makefile | 5 ++
drivers/iommu/arm/Kconfig | 9 ++
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 87 +++++++++++++++++++
.../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 27 ++++++
4 files changed, 128 insertions(+)
create mode 100644 drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
create mode 100644 drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile
index b3e7473f18d2..dcb75fb5b4f1 100644
--- a/arch/arm64/kvm/hyp/nvhe/Makefile
+++ b/arch/arm64/kvm/hyp/nvhe/Makefile
@@ -33,6 +33,11 @@ hyp-obj-$(CONFIG_LIST_HARDENED) += list_debug.o
hyp-obj-$(CONFIG_NVHE_EL2_TRACING) += trace.o events.o
hyp-obj-y += $(lib-objs)
+HYP_SMMU_V3_DRV_PATH = ../../../../../drivers/iommu/arm/arm-smmu-v3
+
+hyp-obj-$(CONFIG_ARM_SMMU_V3_PKVM) += $(HYP_SMMU_V3_DRV_PATH)/pkvm/arm-smmu-v3.o \
+ $(HYP_SMMU_V3_DRV_PATH)/arm-smmu-v3-common-lib.o
+
# Path to simple_ring_buffer.c
CFLAGS_trace.nvhe.o += -I$(srctree)/kernel/trace/
diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig
index 5fac08b89dee..916f4723238d 100644
--- a/drivers/iommu/arm/Kconfig
+++ b/drivers/iommu/arm/Kconfig
@@ -141,3 +141,12 @@ config QCOM_IOMMU
select ARM_DMA_USE_IOMMU
help
Support for IOMMU on certain Qualcomm SoCs.
+
+config ARM_SMMU_V3_PKVM
+ bool "ARM SMMUv3 support for protected Virtual Machines"
+ depends on KVM && ARM64 && ARM_SMMU_V3=y
+ help
+ Enable a SMMUv3 driver in the KVM hypervisor, to protect VMs against
+ memory accesses from devices owned by the host.
+
+ Say Y here if you intend to enable KVM in protected mode.
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
new file mode 100644
index 000000000000..fee5db6c9c20
--- /dev/null
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * pKVM hyp driver for the Arm SMMUv3
+ *
+ * Copyright (C) 2022 Linaro Ltd.
+ */
+#include <asm/kvm_hyp.h>
+
+#include <nvhe/iommu.h>
+#include <nvhe/mem_protect.h>
+
+#include "arm_smmu_v3.h"
+
+size_t __ro_after_init kvm_hyp_arm_smmu_v3_count;
+struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
+
+#define for_each_smmu(smmu) \
+ for ((smmu) = kvm_hyp_arm_smmu_v3_smmus; \
+ (smmu) != &kvm_hyp_arm_smmu_v3_smmus[kvm_hyp_arm_smmu_v3_count]; \
+ (smmu)++)
+
+/* Put the device in a state that can be probed by the host driver. */
+static void smmu_deinit_device(struct hyp_arm_smmu_v3_device *smmu)
+{
+ WARN_ON(__pkvm_hyp_donate_host_mmio(smmu->mmio_addr, smmu->mmio_size));
+ smmu->base = NULL;
+}
+
+static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
+{
+ unsigned long haddr;
+ int ret;
+
+ if (!PAGE_ALIGNED(smmu->mmio_addr | smmu->mmio_size))
+ return -EINVAL;
+
+ ret = __pkvm_host_donate_hyp_mmio(smmu->mmio_addr, smmu->mmio_size, &haddr);
+ if (ret)
+ return ret;
+
+ smmu->base = (void __iomem *)haddr;
+
+ return 0;
+}
+
+/* Called while is the host is still trusted. */
+static int smmu_init(void)
+{
+ size_t smmu_arr_size = PAGE_ALIGN(sizeof(*kvm_hyp_arm_smmu_v3_smmus) *
+ kvm_hyp_arm_smmu_v3_count);
+ struct hyp_arm_smmu_v3_device *smmu;
+ u64 pfn, nr_pages;
+ int ret;
+
+ kvm_hyp_arm_smmu_v3_smmus = kern_hyp_va(kvm_hyp_arm_smmu_v3_smmus);
+ pfn = hyp_virt_to_pfn(kvm_hyp_arm_smmu_v3_smmus);
+ nr_pages = smmu_arr_size >> PAGE_SHIFT;
+
+ ret = __pkvm_host_donate_hyp(pfn, nr_pages);
+ if (ret)
+ return ret;
+
+ for_each_smmu(smmu) {
+ ret = smmu_init_device(smmu);
+ if (ret)
+ goto out_reclaim_smmu;
+ }
+
+ return 0;
+
+out_reclaim_smmu:
+ while (smmu != kvm_hyp_arm_smmu_v3_smmus)
+ smmu_deinit_device(--smmu);
+ WARN_ON(__pkvm_hyp_donate_host(pfn, nr_pages));
+ return ret;
+}
+
+static int smmu_host_stage2_idmap(phys_addr_t start, phys_addr_t end, int prot)
+{
+ return 0;
+}
+
+/* Shared with the kernel driver in EL1 */
+struct pkvm_iommu_ops smmu_ops = {
+ .init = smmu_init,
+ .host_stage2_idmap = smmu_host_stage2_idmap,
+};
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
new file mode 100644
index 000000000000..0d9e48b201f5
--- /dev/null
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __KVM_ARM_SMMU_V3_H
+#define __KVM_ARM_SMMU_V3_H
+
+#include <asm/kvm_asm.h>
+
+/*
+ * Parameters from the trusted host:
+ * @mmio_addr base address of the SMMU registers
+ * @mmio_size size of the registers resource
+ *
+ * Other members are filled and used at runtime by the SMMU driver.
+ * @base Virtual address of SMMU registers
+ */
+struct hyp_arm_smmu_v3_device {
+ phys_addr_t mmio_addr;
+ size_t mmio_size;
+ void __iomem *base;
+};
+
+extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count);
+#define kvm_hyp_arm_smmu_v3_count kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count)
+
+extern struct hyp_arm_smmu_v3_device *kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_smmus);
+#define kvm_hyp_arm_smmu_v3_smmus kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_smmus)
+
+#endif /* __KVM_ARM_SMMU_V3_H */
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 11/24] iommu/arm-smmu-v3-kvm: Add the kernel driver
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (9 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 10/24] iommu/arm-smmu-v3-kvm: Add SMMUv3 driver Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 12/24] iommu/arm-smmu-v3-kvm: Probe SMMU HW Mostafa Saleh
` (12 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
When KVM runs in protected mode, and CONFIG_ARM_SMMU_V3_PKVM
is enabled, it will manage the SMMUv3 HW using trap and emulate
and present emulated SMMUs to the host kernel.
In that case, those SMMUs will be on the aux bus, so make it
possible to the driver to probe those devices.
Otherwise, everything else is the same as the KVM emulation
complies with the architecture,so the driver doesn't need
to be modified.
Suggested-by: Jason Gunthorpe <jgg@ziepe.ca>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
drivers/iommu/arm/arm-smmu-v3/Makefile | 1 +
.../iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c | 189 ++++++++++++++++++
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 43 ++++
.../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 2 +
4 files changed, 235 insertions(+)
create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c
diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm-smmu-v3/Makefile
index c9ce392e6d31..c3fc5c4a4a1e 100644
--- a/drivers/iommu/arm/arm-smmu-v3/Makefile
+++ b/drivers/iommu/arm/arm-smmu-v3/Makefile
@@ -4,5 +4,6 @@ arm_smmu_v3-y := arm-smmu-v3.o arm-smmu-v3-common-lib.o
arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) += arm-smmu-v3-iommufd.o
arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) += tegra241-cmdqv.o
+arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_PKVM) += arm-smmu-v3-kvm.o
obj-$(CONFIG_ARM_SMMU_V3_KUNIT_TEST) += arm-smmu-v3-test.o
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c
new file mode 100644
index 000000000000..68b78ed933d4
--- /dev/null
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * pKVM host driver for the Arm SMMUv3
+ *
+ * Copyright (C) 2022 Linaro Ltd.
+ */
+#include <asm/kvm_mmu.h>
+#include <asm/kvm_pkvm.h>
+
+#include <linux/auxiliary_bus.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include "arm-smmu-v3.h"
+#include "pkvm/arm_smmu_v3.h"
+
+extern struct pkvm_iommu_ops kvm_nvhe_sym(smmu_ops);
+
+static size_t kvm_arm_smmu_count;
+static struct hyp_arm_smmu_v3_device *kvm_arm_smmu_array;
+static size_t kvm_arm_smmu_cur;
+
+static void kvm_arm_smmu_array_free(void)
+{
+ int order;
+
+ order = get_order(kvm_arm_smmu_count * sizeof(*kvm_arm_smmu_array));
+ free_pages((unsigned long)kvm_arm_smmu_array, order);
+}
+
+static int kvm_arm_smmu_array_alloc(void)
+{
+ int smmu_order;
+ struct device_node *np;
+
+ for_each_compatible_node(np, NULL, "arm,smmu-v3")
+ kvm_arm_smmu_count++;
+
+ if (!kvm_arm_smmu_count)
+ return -ENODEV;
+ smmu_order = get_order(kvm_arm_smmu_count * sizeof(*kvm_arm_smmu_array));
+ kvm_arm_smmu_array = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, smmu_order);
+ if (!kvm_arm_smmu_array)
+ return -ENOMEM;
+ return 0;
+}
+
+static unsigned int smmu_hyp_pgt_pages(void)
+{
+ struct device_node *np = of_find_compatible_node(NULL, NULL, "arm,smmu-v3");
+
+ /*
+ * SMMUv3 uses the same format as the CPU stage-2 and hence have the same memory
+ * requirements, we add extra 500 pages for L2 STEs.
+ * Only one set of memory is allocated as the page table is shared between all
+ * the SMMUs.
+ */
+ if (np) {
+ of_node_put(np);
+ return host_s2_pgtable_pages() + 500;
+ }
+
+ return 0;
+}
+
+static struct platform_driver smmuv3_nesting_driver;
+static int smmuv3_nesting_probe(struct platform_device *pdev)
+{
+ struct hyp_arm_smmu_v3_device *smmu = &kvm_arm_smmu_array[kvm_arm_smmu_cur];
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+
+ /* Only device tree, ACPI not supported. */
+ if (!dev->of_node)
+ return -EINVAL;
+
+ if (kvm_arm_smmu_cur >= kvm_arm_smmu_count)
+ return -ENOSPC;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ if (of_property_read_bool(dev->of_node, "cavium,cn9900-broken-page1-regspace"))
+ return -EINVAL;
+
+ smmu->mmio_addr = res->start;
+ smmu->mmio_size = resource_size(res);
+ if (smmu->mmio_size < SZ_128K) {
+ dev_err(dev, "MMIO region too small(%pr)\n", res);
+ return -EINVAL;
+ }
+
+ if (of_dma_is_coherent(dev->of_node))
+ smmu->features |= ARM_SMMU_FEAT_COHERENCY;
+
+ kvm_arm_smmu_cur++;
+ return 0;
+}
+
+static int __init kvm_arm_smmu_v3_register(void)
+{
+ size_t nr_pages = smmu_hyp_pgt_pages();
+ int ret;
+
+ if (!is_protected_kvm_enabled() || !nr_pages)
+ return 0;
+
+ ret = kvm_arm_smmu_array_alloc();
+ if (ret)
+ goto out_err;
+
+ ret = platform_driver_probe(&smmuv3_nesting_driver, smmuv3_nesting_probe);
+ if (ret)
+ goto out_free;
+
+ ret = pkvm_iommu_register_driver(kern_hyp_va(lm_alias(&kvm_nvhe_sym(smmu_ops))),
+ nr_pages);
+ if (ret)
+ goto out_unregister;
+
+ /*
+ * These variables are stored in the nVHE image, and won't be accessible
+ * after KVM initialization. Ownership of kvm_arm_smmu_array will be
+ * transferred to the hypervisor as well.
+ */
+ kvm_hyp_arm_smmu_v3_smmus = kvm_arm_smmu_array;
+ kvm_hyp_arm_smmu_v3_count = kvm_arm_smmu_cur;
+ return ret;
+
+out_unregister:
+ platform_driver_unregister(&smmuv3_nesting_driver);
+out_free:
+ kvm_arm_smmu_array_free();
+out_err:
+ kvm_arm_smmu_count = 0;
+ kvm_arm_smmu_array = NULL;
+ return ret;
+};
+
+static int smmu_create_aux_device(struct device *dev, void *data)
+{
+ static int dev_id;
+ struct auxiliary_device *auxdev;
+
+ auxdev = __devm_auxiliary_device_create(dev, "protected_kvm",
+ "smmu_v3_emu", NULL, dev_id++);
+ if (!auxdev)
+ return -ENODEV;
+
+ auxdev->dev.parent = dev;
+ return 0;
+}
+
+static int kvm_arm_smmu_v3_post_init(void)
+{
+ if (!kvm_arm_smmu_count)
+ return 0;
+
+ /*
+ * If the hypervisor part of the driver fails, KVM will not initialise.
+ */
+ if (!is_kvm_arm_initialised()) {
+ kvm_arm_smmu_array_free();
+ platform_driver_unregister(&smmuv3_nesting_driver);
+ return 0;
+ }
+
+ WARN_ON(driver_for_each_device(&smmuv3_nesting_driver.driver, NULL,
+ NULL, smmu_create_aux_device));
+
+ return 0;
+}
+
+static const struct of_device_id smmuv3_nested_of_match[] = {
+ { .compatible = "arm,smmu-v3", },
+ { },
+};
+
+static struct platform_driver smmuv3_nesting_driver = {
+ .driver = {
+ .name = "smmuv3-nesting",
+ .of_match_table = smmuv3_nested_of_match,
+ .suppress_bind_attrs = true,
+ },
+};
+late_initcall(kvm_arm_smmu_v3_post_init);
+subsys_initcall(kvm_arm_smmu_v3_register);
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 674ff98706f6..49728d8076d9 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -11,6 +11,7 @@
#include <linux/acpi.h>
#include <linux/acpi_iort.h>
+#include <linux/auxiliary_bus.h>
#include <linux/bitops.h>
#include <linux/crash_dump.h>
#include <linux/delay.h>
@@ -5311,6 +5312,48 @@ static struct platform_driver arm_smmu_driver = {
module_driver(arm_smmu_driver, platform_driver_register,
arm_smmu_driver_unregister);
+#ifdef CONFIG_ARM_SMMU_V3_PKVM
+/*
+ * Now we have 2 devices, the aux device bound to this driver, and pdev
+ * which is the physical platform device bound to the KVM driver but not used.
+ * However, this driver keeps using the platform device for 2 reasons:
+ * 1) Simplicity: Avoiding changing big parts of the code assuming
+ * the underlying device is a platform device.
+ * 2) Dealing with DMA-API, irqs(MSIs), RPM... requires the physical device.
+ */
+
+static int arm_smmu_device_probe_emu(struct auxiliary_device *auxdev,
+ const struct auxiliary_device_id *id)
+{
+ struct device *parent = auxdev->dev.parent;
+
+ dev_info(&auxdev->dev, "Probing from %s\n", dev_name(parent));
+ return arm_smmu_device_probe(to_platform_device(parent));
+}
+
+static void arm_smmu_device_remove_emu(struct auxiliary_device *auxdev)
+{
+ arm_smmu_device_remove(to_platform_device(auxdev->dev.parent));
+}
+
+const struct auxiliary_device_id arm_smmu_aux_table[] = {
+ { .name = "protected_kvm.smmu_v3_emu" },
+ { },
+};
+
+struct auxiliary_driver arm_smmu_driver_emu = {
+ .driver = {
+ .suppress_bind_attrs = true,
+ },
+ .name = "arm-smmu-v3-emu",
+ .id_table = arm_smmu_aux_table,
+ .probe = arm_smmu_device_probe_emu,
+ .remove = arm_smmu_device_remove_emu,
+};
+
+module_auxiliary_driver(arm_smmu_driver_emu);
+#endif
+
MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
MODULE_AUTHOR("Will Deacon <will@kernel.org>");
MODULE_ALIAS("platform:arm-smmu-v3");
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
index 0d9e48b201f5..744ee2b7f0b4 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
@@ -8,6 +8,7 @@
* Parameters from the trusted host:
* @mmio_addr base address of the SMMU registers
* @mmio_size size of the registers resource
+ * @features Features of SMMUv3, subset of the main driver
*
* Other members are filled and used at runtime by the SMMU driver.
* @base Virtual address of SMMU registers
@@ -16,6 +17,7 @@ struct hyp_arm_smmu_v3_device {
phys_addr_t mmio_addr;
size_t mmio_size;
void __iomem *base;
+ u32 features;
};
extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count);
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 12/24] iommu/arm-smmu-v3-kvm: Probe SMMU HW
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (10 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 11/24] iommu/arm-smmu-v3-kvm: Add the kernel driver Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 13/24] iommu/arm-smmu-v3-kvm: Add MMIO emulation Mostafa Saleh
` (11 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Probe SMMU features from the IDR register space, most of
the logic is common with the kernel.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 54 +++++++++++++++++++
.../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 6 +++
2 files changed, 60 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index fee5db6c9c20..be5922d80184 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -10,6 +10,7 @@
#include <nvhe/mem_protect.h>
#include "arm_smmu_v3.h"
+#include "../arm-smmu-v3.h"
size_t __ro_after_init kvm_hyp_arm_smmu_v3_count;
struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
@@ -26,6 +27,53 @@ static void smmu_deinit_device(struct hyp_arm_smmu_v3_device *smmu)
smmu->base = NULL;
}
+/*
+ * Mini-probe and validation for the hypervisor.
+ */
+static int smmu_probe(struct hyp_arm_smmu_v3_device *smmu)
+{
+ u32 reg;
+
+ /* Similar to the kernel, rely on firmware override. */
+ if (!(smmu->features & ARM_SMMU_FEAT_COHERENCY))
+ return -EINVAL;
+
+ /* IDR0 */
+ reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0);
+
+ smmu->features |= smmu_idr0_features(reg);
+ if (!(smmu->features & (ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE)))
+ return -ENXIO;
+
+ reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1);
+ if (reg & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET | IDR1_REL))
+ return -EINVAL;
+
+ smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg);
+ /* Follows the kernel logic */
+ if (smmu->sid_bits <= STRTAB_SPLIT)
+ smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB;
+
+ reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3);
+ smmu->features |= smmu_idr3_features(reg);
+
+ reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5);
+ smmu->pgsize_bitmap = smmu_idr5_to_pgsize(reg);
+
+ smmu->oas = smmu_idr5_to_oas(reg);
+ if (smmu->oas == 52)
+ smmu->pgsize_bitmap |= 1ULL << 42;
+ else if (!smmu->oas)
+ smmu->oas = 48;
+
+ reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR);
+ smmu->features = smmu_iidr_features(reg, smmu->features);
+ if (!(smmu->features & ARM_SMMU_FEAT_NESTING))
+ return -ENXIO;
+
+ return 0;
+}
+
static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
{
unsigned long haddr;
@@ -39,8 +87,14 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
return ret;
smmu->base = (void __iomem *)haddr;
+ ret = smmu_probe(smmu);
+ if (ret)
+ goto out_ret;
return 0;
+out_ret:
+ smmu_deinit_device(smmu);
+ return ret;
}
/* Called while is the host is still trusted. */
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
index 744ee2b7f0b4..82b84673e85b 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
@@ -12,12 +12,18 @@
*
* Other members are filled and used at runtime by the SMMU driver.
* @base Virtual address of SMMU registers
+ * @oas PA size
+ * @pgsize_bitmap Supported page sizes
+ * @sid_bits Max number of SID bits supported
*/
struct hyp_arm_smmu_v3_device {
phys_addr_t mmio_addr;
size_t mmio_size;
void __iomem *base;
u32 features;
+ unsigned long oas;
+ unsigned long pgsize_bitmap;
+ unsigned int sid_bits;
};
extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count);
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 13/24] iommu/arm-smmu-v3-kvm: Add MMIO emulation
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (11 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 12/24] iommu/arm-smmu-v3-kvm: Probe SMMU HW Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 14/24] iommu/arm-smmu-v3-kvm: Shadow the command queue Mostafa Saleh
` (10 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Add data abort handler for the SMMUs, at the moment most registers
are just passthrough.
In the next patches CMDQ/STE emulation will be added which inserts
logic to some register access.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 159 ++++++++++++++++++
.../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 14 ++
2 files changed, 173 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index be5922d80184..af06c832fc6f 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -8,6 +8,7 @@
#include <nvhe/iommu.h>
#include <nvhe/mem_protect.h>
+#include <nvhe/trap_handler.h>
#include "arm_smmu_v3.h"
#include "../arm-smmu-v3.h"
@@ -82,6 +83,8 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
if (!PAGE_ALIGNED(smmu->mmio_addr | smmu->mmio_size))
return -EINVAL;
+ hyp_spin_lock_init(&smmu->lock);
+ hyp_spin_lock_init(&smmu->hw_lock);
ret = __pkvm_host_donate_hyp_mmio(smmu->mmio_addr, smmu->mmio_size, &haddr);
if (ret)
return ret;
@@ -120,6 +123,8 @@ static int smmu_init(void)
goto out_reclaim_smmu;
}
+ BUILD_BUG_ON(sizeof(hyp_spinlock_t) != sizeof(u32));
+
return 0;
out_reclaim_smmu:
@@ -129,6 +134,159 @@ static int smmu_init(void)
return ret;
}
+static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
+ struct user_pt_regs *regs,
+ u64 esr, u32 off)
+{
+ bool is_write = esr & ESR_ELx_WNR;
+ unsigned int len = BIT((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
+ int rd = (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
+ const u64 read_write = -1ULL;
+ const u64 no_access = 0;
+ u64 mask = no_access;
+ const u64 read_only = is_write ? no_access : read_write;
+ bool is_xzr = (rd == 31);
+ u64 val = is_xzr ? 0 : regs->regs[rd];
+
+ switch (off) {
+ case ARM_SMMU_IDR0:
+ if (len != sizeof(u32))
+ break;
+ /*
+ * Clear stage-2 support, hide MSI to avoid write back to cmdq,
+ * and hide ATS as it is not emulated or handled in TLB invalidation.
+ */
+ mask = read_only & ~(IDR0_S2P | IDR0_VMID16 | IDR0_MSI | IDR0_HYP | IDR0_ATS);
+ break;
+ /* Passthrough the register access for bisectiblity, handled later */
+ case ARM_SMMU_CMDQ_BASE:
+ case ARM_SMMU_CMDQ_PROD:
+ case ARM_SMMU_CMDQ_CONS:
+ case ARM_SMMU_STRTAB_BASE:
+ case ARM_SMMU_STRTAB_BASE_CFG:
+ case ARM_SMMU_GBPA:
+ mask = read_write;
+ break;
+ case ARM_SMMU_CR0:
+ if (len != sizeof(u32))
+ break;
+ mask = read_write;
+ break;
+ case ARM_SMMU_CR1: {
+ if (len != sizeof(u32))
+ break;
+ /* Don't mess with shareability/cacheability. */
+ if (is_write &&
+ (val != (FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) |
+ FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) |
+ FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) |
+ FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) |
+ FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) |
+ FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB))))
+ break;
+
+ mask = read_write;
+ break;
+ }
+
+ /* Allowed 32 bit registers. */
+ case ARM_SMMU_EVTQ_IRQ_CFG1:
+ case ARM_SMMU_EVTQ_IRQ_CFG2:
+ case ARM_SMMU_GERROR_IRQ_CFG1:
+ case ARM_SMMU_GERROR_IRQ_CFG2:
+ case ARM_SMMU_PRIQ_IRQ_CFG1:
+ case ARM_SMMU_PRIQ_IRQ_CFG2:
+ /* These are RES0 as MSI support is hidden. */
+ val = 0;
+ if (!is_write)
+ goto out_update_regs;
+ fallthrough;
+ case ARM_SMMU_EVTQ_PROD + SZ_64K:
+ case ARM_SMMU_EVTQ_CONS + SZ_64K:
+ case ARM_SMMU_PRIQ_PROD + SZ_64K:
+ case ARM_SMMU_PRIQ_CONS + SZ_64K:
+ case ARM_SMMU_GERRORN:
+ case ARM_SMMU_IRQ_CTRLACK:
+ case ARM_SMMU_IRQ_CTRL:
+ case ARM_SMMU_CR0ACK:
+ case ARM_SMMU_CR2:
+ if (len != sizeof(u32))
+ break;
+ mask = read_write;
+ break;
+ /* Allowed 64 bit registers. */
+ case ARM_SMMU_EVTQ_IRQ_CFG0:
+ case ARM_SMMU_PRIQ_IRQ_CFG0:
+ case ARM_SMMU_GERROR_IRQ_CFG0:
+ /* These are RES0 as MSI support is hidden. */
+ val = 0;
+ if (!is_write)
+ goto out_update_regs;
+ fallthrough;
+ case ARM_SMMU_EVTQ_BASE:
+ case ARM_SMMU_PRIQ_BASE:
+ if (len != sizeof(u64))
+ break;
+ mask = read_write;
+ break;
+ /* Allowed RO 32 bit registers. */
+ case ARM_SMMU_IIDR:
+ case ARM_SMMU_IDR5:
+ case ARM_SMMU_IDR3:
+ case ARM_SMMU_IDR1:
+ case ARM_SMMU_GERROR:
+ if (len != sizeof(u32))
+ break;
+ mask = read_only;
+ };
+
+ if (WARN_ON(!mask))
+ goto out_ret;
+
+ hyp_spin_lock(&smmu->hw_lock);
+ if (is_write) {
+ if (len == sizeof(u64))
+ writeq_relaxed(val & mask, smmu->base + off);
+ else
+ writel_relaxed(val & mask, smmu->base + off);
+
+ hyp_spin_unlock(&smmu->hw_lock);
+ return true;
+ }
+
+ if (len == sizeof(u64))
+ val = readq_relaxed(smmu->base + off) & mask;
+ else
+ val = readl_relaxed(smmu->base + off) & mask;
+ hyp_spin_unlock(&smmu->hw_lock);
+out_update_regs:
+ /*
+ * Device might be read senstive, so do it but ignore writing
+ * back for xzr.
+ */
+ if (!is_xzr)
+ regs->regs[rd] = val;
+
+out_ret:
+ return true;
+}
+
+static bool smmu_dabt_handler(struct user_pt_regs *regs, u64 esr, u64 addr)
+{
+ struct hyp_arm_smmu_v3_device *smmu;
+ bool ret;
+
+ for_each_smmu(smmu) {
+ if (addr < smmu->mmio_addr || addr >= smmu->mmio_addr + smmu->mmio_size)
+ continue;
+ hyp_spin_lock(&smmu->lock);
+ ret = smmu_dabt_device(smmu, regs, esr, addr - smmu->mmio_addr);
+ hyp_spin_unlock(&smmu->lock);
+ return ret;
+ }
+ return false;
+}
+
static int smmu_host_stage2_idmap(phys_addr_t start, phys_addr_t end, int prot)
{
return 0;
@@ -138,4 +296,5 @@ static int smmu_host_stage2_idmap(phys_addr_t start, phys_addr_t end, int prot)
struct pkvm_iommu_ops smmu_ops = {
.init = smmu_init,
.host_stage2_idmap = smmu_host_stage2_idmap,
+ .dabt_handler = smmu_dabt_handler,
};
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
index 82b84673e85b..2bda6e03c96c 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
@@ -4,6 +4,10 @@
#include <asm/kvm_asm.h>
+#ifdef __KVM_NVHE_HYPERVISOR__
+#include <nvhe/spinlock.h>
+#endif
+
/*
* Parameters from the trusted host:
* @mmio_addr base address of the SMMU registers
@@ -15,6 +19,9 @@
* @oas PA size
* @pgsize_bitmap Supported page sizes
* @sid_bits Max number of SID bits supported
+ * @lock Lock to protect SMMU emulation
+ * @hw_lock Lock to protect SMMU HW (as CMDQ)
+ Order smmu.lock => host_mmu.lock => smmu.hw_lock
*/
struct hyp_arm_smmu_v3_device {
phys_addr_t mmio_addr;
@@ -24,6 +31,13 @@ struct hyp_arm_smmu_v3_device {
unsigned long oas;
unsigned long pgsize_bitmap;
unsigned int sid_bits;
+#ifdef __KVM_NVHE_HYPERVISOR__
+ hyp_spinlock_t lock;
+ hyp_spinlock_t hw_lock;
+#else
+ u32 lock;
+ u32 hw_lock;
+#endif
};
extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count);
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 14/24] iommu/arm-smmu-v3-kvm: Shadow the command queue
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (12 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 13/24] iommu/arm-smmu-v3-kvm: Add MMIO emulation Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 15/24] iommu/arm-smmu-v3-kvm: Add CMDQ functions Mostafa Saleh
` (9 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
At boot allocate a command queue per SMMU which is used as a shadow
by the hypervisor.
The command queue size is 64K which is more than enough, as the
hypervisor would consume all the entries per a command queue prod
write, which means it can handle up to 4096 at a time.
Then, the host command queue needs to be pinned in a shared state, so
it can't be donated to VMs, and avoid tricking the hypervisor into
accessing them. This is done each time the command queue is enabled,
and undone each time the command queue is disabled.
The hypervisor won’t access the host command queue when it is disabled
from the host.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c | 25 ++++
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 123 +++++++++++++++++-
.../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 8 ++
3 files changed, 155 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c
index 68b78ed933d4..81a4cd539415 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c
@@ -15,6 +15,8 @@
#include "arm-smmu-v3.h"
#include "pkvm/arm_smmu_v3.h"
+#define SMMU_KVM_CMDQ_ORDER 4
+
extern struct pkvm_iommu_ops kvm_nvhe_sym(smmu_ops);
static size_t kvm_arm_smmu_count;
@@ -24,6 +26,15 @@ static size_t kvm_arm_smmu_cur;
static void kvm_arm_smmu_array_free(void)
{
int order;
+ int i;
+
+ for (i = 0 ; i < kvm_arm_smmu_cur ; ++i) {
+ struct hyp_arm_smmu_v3_device *smmu = &kvm_arm_smmu_array[i];
+
+ if (smmu->cmdq.base_dma)
+ free_pages((unsigned long)phys_to_virt(smmu->cmdq.base_dma),
+ SMMU_KVM_CMDQ_ORDER);
+ }
order = get_order(kvm_arm_smmu_count * sizeof(*kvm_arm_smmu_array));
free_pages((unsigned long)kvm_arm_smmu_array, order);
@@ -70,6 +81,7 @@ static int smmuv3_nesting_probe(struct platform_device *pdev)
struct hyp_arm_smmu_v3_device *smmu = &kvm_arm_smmu_array[kvm_arm_smmu_cur];
struct device *dev = &pdev->dev;
struct resource *res;
+ void *cmdq_base;
/* Only device tree, ACPI not supported. */
if (!dev->of_node)
@@ -92,6 +104,19 @@ static int smmuv3_nesting_probe(struct platform_device *pdev)
return -EINVAL;
}
+ /*
+ * Allocate the shadow command queue, it doesn't have to be the same
+ * size as the host.
+ * Only populate base_dma and llq.max_n_shift, the hypervisor will init
+ * the rest.
+ */
+ cmdq_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, SMMU_KVM_CMDQ_ORDER);
+ if (!cmdq_base)
+ return -ENOMEM;
+
+ smmu->cmdq.base_dma = virt_to_phys(cmdq_base);
+ smmu->cmdq.llq.max_n_shift = SMMU_KVM_CMDQ_ORDER + PAGE_SHIFT - CMDQ_ENT_SZ_SHIFT;
+
if (of_dma_is_coherent(dev->of_node))
smmu->features |= ARM_SMMU_FEAT_COHERENCY;
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index af06c832fc6f..9f76f4e82341 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -11,7 +11,6 @@
#include <nvhe/trap_handler.h>
#include "arm_smmu_v3.h"
-#include "../arm-smmu-v3.h"
size_t __ro_after_init kvm_hyp_arm_smmu_v3_count;
struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
@@ -21,10 +20,68 @@ struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
(smmu) != &kvm_hyp_arm_smmu_v3_smmus[kvm_hyp_arm_smmu_v3_count]; \
(smmu)++)
+#define cmdq_size(cmdq) ((1 << ((cmdq)->llq.max_n_shift)) * CMDQ_ENT_DWORDS * 8)
+
+static bool is_cmdq_enabled(struct hyp_arm_smmu_v3_device *smmu)
+{
+ return FIELD_GET(CR0_CMDQEN, smmu->cr0);
+}
+
+/*
+ * CMDQ, STE host copies are accessed by the hypervisor, we share them to
+ * - Prevent the host from passing protected VM memory.
+ * - Having them mapped in the hyp page table.
+ */
+static int smmu_share_pages(phys_addr_t addr, size_t size)
+{
+ size_t nr_pages = PAGE_ALIGN(size + (addr & ~PAGE_MASK)) >> PAGE_SHIFT;
+ phys_addr_t base = addr & PAGE_MASK;
+ int i, ret;
+
+ for (i = 0 ; i < nr_pages ; ++i) {
+ if (__pkvm_host_share_hyp((base + i * PAGE_SIZE) >> PAGE_SHIFT)) {
+ while (i--)
+ __pkvm_host_unshare_hyp((base + i * PAGE_SIZE) >> PAGE_SHIFT);
+ return -EPERM;
+ }
+ }
+
+ ret = hyp_pin_shared_mem(hyp_phys_to_virt(base),
+ hyp_phys_to_virt(base + nr_pages * PAGE_SIZE));
+ if (ret) {
+ for (i = 0 ; i < nr_pages ; ++i)
+ __pkvm_host_unshare_hyp((base + i * PAGE_SIZE) >> PAGE_SHIFT);
+ }
+
+ return ret;
+}
+
+static int smmu_unshare_pages(phys_addr_t addr, size_t size)
+{
+ size_t nr_pages = PAGE_ALIGN(size + (addr & ~PAGE_MASK)) >> PAGE_SHIFT;
+ phys_addr_t base = addr & PAGE_MASK;
+ int i, ret;
+
+ hyp_unpin_shared_mem(hyp_phys_to_virt(base),
+ hyp_phys_to_virt(base + nr_pages * PAGE_SIZE));
+
+ for (i = 0 ; i < nr_pages ; ++i) {
+ ret = __pkvm_host_unshare_hyp((base + i * PAGE_SIZE) >> PAGE_SHIFT);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
/* Put the device in a state that can be probed by the host driver. */
static void smmu_deinit_device(struct hyp_arm_smmu_v3_device *smmu)
{
WARN_ON(__pkvm_hyp_donate_host_mmio(smmu->mmio_addr, smmu->mmio_size));
+
+ if (smmu->cmdq.base)
+ WARN_ON(__pkvm_hyp_donate_host(smmu->cmdq.base_dma >> PAGE_SHIFT,
+ cmdq_size(&smmu->cmdq) >> PAGE_SHIFT));
smmu->base = NULL;
}
@@ -75,6 +132,31 @@ static int smmu_probe(struct hyp_arm_smmu_v3_device *smmu)
return 0;
}
+/*
+ * The kernel part of the driver will allocate the shadow cmdq,
+ * and zero it. This function only donates it.
+ */
+static int smmu_init_cmdq(struct hyp_arm_smmu_v3_device *smmu)
+{
+ size_t cmdq_nr_pages = cmdq_size(&smmu->cmdq) >> PAGE_SHIFT;
+ int ret;
+
+ ret = __pkvm_host_donate_hyp(smmu->cmdq.base_dma >> PAGE_SHIFT, cmdq_nr_pages);
+ if (ret)
+ return ret;
+
+ smmu->cmdq.base = hyp_phys_to_virt(smmu->cmdq.base_dma);
+ smmu->cmdq.prod_reg = smmu->base + ARM_SMMU_CMDQ_PROD;
+ smmu->cmdq.cons_reg = smmu->base + ARM_SMMU_CMDQ_CONS;
+ smmu->cmdq.q_base = smmu->cmdq.base_dma |
+ FIELD_PREP(Q_BASE_LOG2SIZE, smmu->cmdq.llq.max_n_shift);
+ smmu->cmdq.ent_dwords = CMDQ_ENT_DWORDS;
+ writel_relaxed(0, smmu->cmdq.prod_reg);
+ writel_relaxed(0, smmu->cmdq.cons_reg);
+ writeq_relaxed(smmu->cmdq.q_base, smmu->base + ARM_SMMU_CMDQ_BASE);
+ return 0;
+}
+
static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
{
unsigned long haddr;
@@ -94,7 +176,12 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
if (ret)
goto out_ret;
+ ret = smmu_init_cmdq(smmu);
+ if (ret)
+ goto out_ret;
+
return 0;
+
out_ret:
smmu_deinit_device(smmu);
return ret;
@@ -134,6 +221,23 @@ static int smmu_init(void)
return ret;
}
+static void smmu_emulate_cmdq_enable(struct hyp_arm_smmu_v3_device *smmu)
+{
+ u32 shift = smmu->cmdq_host.q_base & Q_BASE_LOG2SIZE;
+
+ smmu->cmdq_host.llq.max_n_shift = min(shift, 19);
+ smmu->cmdq_host.base_dma = smmu->cmdq_host.q_base & Q_BASE_ADDR_MASK;
+ smmu->cmdq_host.base_dma &= ~(cmdq_size(&smmu->cmdq_host) - 1);
+ WARN_ON(smmu_share_pages(smmu->cmdq_host.base_dma,
+ cmdq_size(&smmu->cmdq_host)));
+}
+
+static void smmu_emulate_cmdq_disable(struct hyp_arm_smmu_v3_device *smmu)
+{
+ WARN_ON(smmu_unshare_pages(smmu->cmdq_host.base_dma,
+ cmdq_size(&smmu->cmdq_host)));
+}
+
static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
struct user_pt_regs *regs,
u64 esr, u32 off)
@@ -160,6 +264,14 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
break;
/* Passthrough the register access for bisectiblity, handled later */
case ARM_SMMU_CMDQ_BASE:
+ if (is_write) {
+ /* Not allowed by the architecture */
+ if (is_cmdq_enabled(smmu))
+ break;
+ smmu->cmdq_host.q_base = val;
+ }
+ mask = read_write;
+ break;
case ARM_SMMU_CMDQ_PROD:
case ARM_SMMU_CMDQ_CONS:
case ARM_SMMU_STRTAB_BASE:
@@ -170,6 +282,15 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
case ARM_SMMU_CR0:
if (len != sizeof(u32))
break;
+ if (is_write) {
+ bool last_cmdq_en = is_cmdq_enabled(smmu);
+
+ smmu->cr0 = val;
+ if (!last_cmdq_en && is_cmdq_enabled(smmu))
+ smmu_emulate_cmdq_enable(smmu);
+ else if (last_cmdq_en && !is_cmdq_enabled(smmu))
+ smmu_emulate_cmdq_disable(smmu);
+ }
mask = read_write;
break;
case ARM_SMMU_CR1: {
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
index 2bda6e03c96c..74a7f62d93eb 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
@@ -8,6 +8,8 @@
#include <nvhe/spinlock.h>
#endif
+#include "../arm-smmu-v3.h"
+
/*
* Parameters from the trusted host:
* @mmio_addr base address of the SMMU registers
@@ -22,6 +24,9 @@
* @lock Lock to protect SMMU emulation
* @hw_lock Lock to protect SMMU HW (as CMDQ)
Order smmu.lock => host_mmu.lock => smmu.hw_lock
+ * @cmdq CMDQ as observed by HW
+ * @cmdq_host Host view of the CMDQ, only q_base and llq used.
+ * @cr0 Last value of CR0
*/
struct hyp_arm_smmu_v3_device {
phys_addr_t mmio_addr;
@@ -38,6 +43,9 @@ struct hyp_arm_smmu_v3_device {
u32 lock;
u32 hw_lock;
#endif
+ struct arm_smmu_queue cmdq;
+ struct arm_smmu_queue cmdq_host;
+ u32 cr0;
};
extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count);
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 15/24] iommu/arm-smmu-v3-kvm: Add CMDQ functions
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (13 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 14/24] iommu/arm-smmu-v3-kvm: Shadow the command queue Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 16/24] iommu/arm-smmu-v3-kvm: Emulate CMDQ for host Mostafa Saleh
` (8 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Add functions to access the command queue, there are 2 main usage:
- Hypervisor's own commands, as TLB invalidation, would use functions
as smmu_send_cmd(), which creates and sends a command.
- Add host commands to the shadow command queue, after being filtered,
these will be added with smmu_add_cmd_raw.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 14 ++-
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 109 ++++++++++++++++++
2 files changed, 117 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 842d0c9b883c..cbc4589e89a8 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -1226,19 +1226,21 @@ unsigned long smmu_iidr_features(u32 reg, unsigned long features);
unsigned long smmu_iidr_options(u32 reg, unsigned long options);
/* Queue functions shared between kernel and hyp. */
-static inline bool queue_has_space(struct arm_smmu_ll_queue *q, u32 n)
+static inline u32 queue_space(struct arm_smmu_ll_queue *q)
{
- u32 space, prod, cons;
+ u32 prod, cons;
prod = Q_IDX(q, q->prod);
cons = Q_IDX(q, q->cons);
if (Q_WRP(q, q->prod) == Q_WRP(q, q->cons))
- space = (1 << q->max_n_shift) - (prod - cons);
- else
- space = cons - prod;
+ return (1 << q->max_n_shift) - (prod - cons);
+ return cons - prod;
+}
- return space >= n;
+static inline bool queue_has_space(struct arm_smmu_ll_queue *q, u32 n)
+{
+ return queue_space(q) >= n;
}
static inline bool queue_full(struct arm_smmu_ll_queue *q)
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index 9f76f4e82341..8e798fd8fdaa 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -6,6 +6,7 @@
*/
#include <asm/kvm_hyp.h>
+#include <nvhe/clock.h>
#include <nvhe/iommu.h>
#include <nvhe/mem_protect.h>
#include <nvhe/trap_handler.h>
@@ -22,6 +23,36 @@ struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
#define cmdq_size(cmdq) ((1 << ((cmdq)->llq.max_n_shift)) * CMDQ_ENT_DWORDS * 8)
+#define ARM_SMMU_EL2_POLL_TIMEOUT_US 1000
+/*
+ * Wait until @cond is true, can use WFE, if polling on an SMMU and
+ * event that supports it.
+ * Return 0 on success, or -ETIMEDOUT
+ */
+#define smmu_wait(__use_wfe, __cond) \
+({ \
+ int __ret = 0; \
+ u64 start = hyp_clock_ns(); \
+ u64 timeout = ARM_SMMU_EL2_POLL_TIMEOUT_US * 1000; \
+ \
+ while (!(__cond)) { \
+ if (__use_wfe) { \
+ wfe(); \
+ if (__cond) \
+ break; \
+ } else { \
+ cpu_relax(); \
+ } \
+ if ((hyp_clock_ns() - start) >= timeout) { \
+ if (__cond) \
+ break; \
+ __ret = -ETIMEDOUT; \
+ break; \
+ } \
+ } \
+ __ret; \
+})
+
static bool is_cmdq_enabled(struct hyp_arm_smmu_v3_device *smmu)
{
return FIELD_GET(CR0_CMDQEN, smmu->cr0);
@@ -74,6 +105,84 @@ static int smmu_unshare_pages(phys_addr_t addr, size_t size)
return 0;
}
+__maybe_unused
+static bool smmu_cmdq_has_space(struct arm_smmu_queue *cmdq, u32 n)
+{
+ struct arm_smmu_ll_queue *llq = &cmdq->llq;
+
+ WRITE_ONCE(llq->cons, readl_relaxed(cmdq->cons_reg));
+ return queue_has_space(llq, n);
+}
+
+static bool smmu_cmdq_full(struct arm_smmu_queue *cmdq)
+{
+ struct arm_smmu_ll_queue *llq = &cmdq->llq;
+
+ WRITE_ONCE(llq->cons, readl_relaxed(cmdq->cons_reg));
+ return queue_full(llq);
+}
+
+static bool smmu_cmdq_empty(struct arm_smmu_queue *cmdq)
+{
+ struct arm_smmu_ll_queue *llq = &cmdq->llq;
+
+ WRITE_ONCE(llq->cons, readl_relaxed(cmdq->cons_reg));
+ return queue_empty(llq);
+}
+
+static void smmu_add_cmd_raw(struct hyp_arm_smmu_v3_device *smmu,
+ u64 *cmd)
+{
+ struct arm_smmu_queue *q = &smmu->cmdq;
+ struct arm_smmu_ll_queue *llq = &q->llq;
+
+ queue_write(Q_ENT(q, llq->prod), cmd, CMDQ_ENT_DWORDS);
+ llq->prod = queue_inc_prod_n(llq, 1);
+}
+
+static int smmu_add_cmd(struct hyp_arm_smmu_v3_device *smmu,
+ struct arm_smmu_cmd *cmd)
+{
+ int ret;
+
+ hyp_assert_lock_held(&smmu->hw_lock);
+ ret = smmu_wait(false, !smmu_cmdq_full(&smmu->cmdq));
+ if (ret)
+ return ret;
+
+ smmu_add_cmd_raw(smmu, cmd->data);
+ writel(smmu->cmdq.llq.prod, smmu->cmdq.prod_reg);
+ return 0;
+}
+
+static int smmu_sync_cmd(struct hyp_arm_smmu_v3_device *smmu)
+{
+ int ret;
+ struct arm_smmu_cmd cmd;
+
+ hyp_assert_lock_held(&smmu->hw_lock);
+ cmd = arm_smmu_make_cmd_sync(CMDQ_SYNC_0_CS_SEV, 0);
+ ret = smmu_add_cmd(smmu, &cmd);
+ if (ret)
+ return ret;
+
+ return smmu_wait(smmu->features & ARM_SMMU_FEAT_SEV,
+ smmu_cmdq_empty(&smmu->cmdq));
+}
+
+__maybe_unused
+static int smmu_send_cmd(struct hyp_arm_smmu_v3_device *smmu,
+ struct arm_smmu_cmd *cmd)
+{
+ int ret = smmu_add_cmd(smmu, cmd);
+
+ hyp_assert_lock_held(&smmu->hw_lock);
+ if (ret)
+ return ret;
+
+ return smmu_sync_cmd(smmu);
+}
+
/* Put the device in a state that can be probed by the host driver. */
static void smmu_deinit_device(struct hyp_arm_smmu_v3_device *smmu)
{
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 16/24] iommu/arm-smmu-v3-kvm: Emulate CMDQ for host
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (14 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 15/24] iommu/arm-smmu-v3-kvm: Add CMDQ functions Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 17/24] iommu/arm-smmu-v3-kvm: Shadow stream table Mostafa Saleh
` (7 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Don’t allow access to the command queue from the host:
- ARM_SMMU_CMDQ_BASE: Only allowed to be written when CMDQ is disabled, we
use it to keep track of the host command queue base.
Reads return the saved value.
- ARM_SMMU_CMDQ_PROD: Writes trigger command queue emulation which sanitise
and filters the whole range. Reads returns the host copy.
- ARM_SMMU_CMDQ_CONS: Writes move the sw copy of the cons, but the host
can’t skip commands once submitted. Reads return the emulated value and
the error bits in the actual cons.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 133 +++++++++++++++++-
1 file changed, 129 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index 8e798fd8fdaa..f62c9e8f2c59 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -105,7 +105,6 @@ static int smmu_unshare_pages(phys_addr_t addr, size_t size)
return 0;
}
-__maybe_unused
static bool smmu_cmdq_has_space(struct arm_smmu_queue *cmdq, u32 n)
{
struct arm_smmu_ll_queue *llq = &cmdq->llq;
@@ -330,6 +329,99 @@ static int smmu_init(void)
return ret;
}
+static bool smmu_filter_command(struct hyp_arm_smmu_v3_device *smmu, u64 *command)
+{
+ u64 type = FIELD_GET(CMDQ_0_OP, command[0]);
+
+ switch (type) {
+ case CMDQ_OP_CFGI_STE:
+ /* TBD: SHADOW_STE*/
+ break;
+ case CMDQ_OP_CFGI_ALL:
+ {
+ /*
+ * Linux doesn't use range STE invalidation, and only use this
+ * for CFGI_ALL, which is done on reset and not on an new STE
+ * being used.
+ * Although, this is not architectural we rely on the current Linux
+ * implementation.
+ */
+ if ((FIELD_GET(CMDQ_CFGI_1_RANGE, command[1]) != 31))
+ return true;
+ break;
+ }
+ case CMDQ_OP_TLBI_NH_ASID:
+ case CMDQ_OP_TLBI_NH_VA:
+ case 0x13: /* CMD_TLBI_NH_VAA: Not used by Linux */
+ {
+ /* Only allow VMID = 0 */
+ if (FIELD_GET(CMDQ_TLBI_0_VMID, command[0]) != 0)
+ return true;
+ break;
+ }
+ case CMDQ_OP_PREFETCH_CFG:
+ case CMDQ_OP_CFGI_CD:
+ case CMDQ_OP_CFGI_CD_ALL:
+ case CMDQ_OP_TLBI_NH_ALL:
+ case CMDQ_OP_TLBI_NSNH_ALL:
+ break;
+ case CMDQ_OP_CMD_SYNC:
+ if (FIELD_GET(CMDQ_SYNC_0_CS, command[0]) == CMDQ_SYNC_0_CS_IRQ) {
+ /* Allow it, but let the host timeout, as this should never happen. */
+ command[0] &= ~CMDQ_SYNC_0_CS;
+ command[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV);
+ command[1] &= ~CMDQ_SYNC_1_MSIADDR_MASK;
+ }
+ break;
+ default:
+ /* Deny unknown commands */
+ return true;
+ }
+
+ return false;
+}
+
+static int smmu_emulate_cmdq_insert(struct hyp_arm_smmu_v3_device *smmu)
+{
+ u64 *host_cmdq = hyp_phys_to_virt(smmu->cmdq_host.base_dma);
+ bool use_wfe = smmu->features & ARM_SMMU_FEAT_SEV, skip;
+ u64 cmd[CMDQ_ENT_DWORDS];
+ int idx, ret;
+ u32 space;
+
+ if (!is_cmdq_enabled(smmu))
+ return 0;
+
+ space = (1 << (smmu->cmdq_host.llq.max_n_shift)) - queue_space(&smmu->cmdq_host.llq);
+
+ /* Wait for the command queue to have some space. */
+ ret = smmu_wait(use_wfe, smmu_cmdq_has_space(&smmu->cmdq, space));
+ if (ret)
+ return ret;
+ hyp_spin_lock(&smmu->hw_lock);
+ while (space--) {
+ int i;
+
+ idx = Q_IDX(&smmu->cmdq_host.llq, smmu->cmdq_host.llq.cons);
+ queue_inc_cons(&smmu->cmdq_host.llq);
+
+ /* Copy the command to local buffer avoiding TOCTOU */
+ for (i = 0 ; i < CMDQ_ENT_DWORDS ; ++i)
+ cmd[i] = le64_to_cpu(READ_ONCE(host_cmdq[idx * CMDQ_ENT_DWORDS + i]));
+
+ skip = smmu_filter_command(smmu, cmd);
+ if (WARN_ON(skip))
+ continue;
+ smmu_add_cmd_raw(smmu, cmd);
+ }
+
+ writel(smmu->cmdq.llq.prod, smmu->cmdq.prod_reg);
+
+ ret = smmu_wait(use_wfe, smmu_cmdq_empty(&smmu->cmdq));
+ hyp_spin_unlock(&smmu->hw_lock);
+ return ret;
+}
+
static void smmu_emulate_cmdq_enable(struct hyp_arm_smmu_v3_device *smmu)
{
u32 shift = smmu->cmdq_host.q_base & Q_BASE_LOG2SIZE;
@@ -371,18 +463,51 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
*/
mask = read_only & ~(IDR0_S2P | IDR0_VMID16 | IDR0_MSI | IDR0_HYP | IDR0_ATS);
break;
- /* Passthrough the register access for bisectiblity, handled later */
case ARM_SMMU_CMDQ_BASE:
+ /*
+ * Although allowed to use smaller size, we rely on the SMMUv3 driver
+ * using 64-bit store instruction for simplicity.
+ */
+ if (len != sizeof(u64))
+ break;
if (is_write) {
/* Not allowed by the architecture */
if (is_cmdq_enabled(smmu))
break;
smmu->cmdq_host.q_base = val;
+ goto out_ret;
+ } else {
+ val = smmu->cmdq_host.q_base;
+ goto out_update_regs;
}
- mask = read_write;
- break;
case ARM_SMMU_CMDQ_PROD:
+ if (len != sizeof(u32))
+ break;
+ if (is_write) {
+ smmu->cmdq_host.llq.prod = val;
+ WARN_ON(smmu_emulate_cmdq_insert(smmu));
+ goto out_ret;
+ } else {
+ val = smmu->cmdq_host.llq.prod;
+ goto out_update_regs;
+ }
case ARM_SMMU_CMDQ_CONS:
+ if (len != sizeof(u32))
+ break;
+ if (is_write) {
+ if (WARN_ON(is_cmdq_enabled(smmu)))
+ break;
+
+ smmu->cmdq_host.llq.cons = val;
+ goto out_ret;
+ } else {
+ /* Propagate errors back to the host.*/
+ u32 cons = readl_relaxed(smmu->base + ARM_SMMU_CMDQ_CONS);
+
+ val = smmu->cmdq_host.llq.cons | (CMDQ_CONS_ERR & cons);
+ goto out_update_regs;
+ }
+ /* Passthrough the register access for bisectiblity, handled later */
case ARM_SMMU_STRTAB_BASE:
case ARM_SMMU_STRTAB_BASE_CFG:
case ARM_SMMU_GBPA:
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 17/24] iommu/arm-smmu-v3-kvm: Shadow stream table
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (15 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 16/24] iommu/arm-smmu-v3-kvm: Emulate CMDQ for host Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:58 ` [PATCH v7 18/24] iommu/arm-smmu-v3-kvm: Shadow STEs Mostafa Saleh
` (6 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Allocate the shadow stream table per SMMU.
We choose the size of that table to be 1MB which is the
max size used by host in the case of 2 levels.
All the host writes are still paththrough for bisectibility, that
is changed next where CFGI commands will be trapped and used to
update the shadow copy hypervisor that will be used by HW.
Similar to the command queue, the host stream table is
shared/unshared each time the SMMU is enabled/disabled.
Handling of L2 tables is also done in the next patch when
the shadowing is added.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c | 21 ++-
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 122 ++++++++++++++++++
.../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 10 ++
3 files changed, 152 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c
index 81a4cd539415..2cafb03995ea 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c
@@ -16,6 +16,13 @@
#include "pkvm/arm_smmu_v3.h"
#define SMMU_KVM_CMDQ_ORDER 4
+/*
+ * Use the max value of L1 the kernel uses, that also covers the worst case
+ * for linear tables as it is mandatory according to the spec to support 2
+ * lvl tables if SIDSIZE >= 7
+ */
+#define SMMU_KVM_STRTAB_ORDER (get_order(STRTAB_MAX_L1_ENTRIES * \
+ sizeof(struct arm_smmu_strtab_l1)))
extern struct pkvm_iommu_ops kvm_nvhe_sym(smmu_ops);
@@ -34,6 +41,9 @@ static void kvm_arm_smmu_array_free(void)
if (smmu->cmdq.base_dma)
free_pages((unsigned long)phys_to_virt(smmu->cmdq.base_dma),
SMMU_KVM_CMDQ_ORDER);
+ if (smmu->strtab_dma)
+ free_pages((unsigned long)phys_to_virt(smmu->strtab_dma),
+ SMMU_KVM_STRTAB_ORDER);
}
order = get_order(kvm_arm_smmu_count * sizeof(*kvm_arm_smmu_array));
@@ -80,8 +90,8 @@ static int smmuv3_nesting_probe(struct platform_device *pdev)
{
struct hyp_arm_smmu_v3_device *smmu = &kvm_arm_smmu_array[kvm_arm_smmu_cur];
struct device *dev = &pdev->dev;
+ void *cmdq_base, *strtab;
struct resource *res;
- void *cmdq_base;
/* Only device tree, ACPI not supported. */
if (!dev->of_node)
@@ -117,6 +127,15 @@ static int smmuv3_nesting_probe(struct platform_device *pdev)
smmu->cmdq.base_dma = virt_to_phys(cmdq_base);
smmu->cmdq.llq.max_n_shift = SMMU_KVM_CMDQ_ORDER + PAGE_SHIFT - CMDQ_ENT_SZ_SHIFT;
+ strtab = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, SMMU_KVM_STRTAB_ORDER);
+ if (!strtab) {
+ free_pages((unsigned long)cmdq_base, SMMU_KVM_CMDQ_ORDER);
+ return -ENOMEM;
+ }
+
+ smmu->strtab_dma = virt_to_phys(strtab);
+ smmu->strtab_size = PAGE_SIZE << SMMU_KVM_STRTAB_ORDER;
+
if (of_dma_is_coherent(dev->of_node))
smmu->features |= ARM_SMMU_FEAT_COHERENCY;
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index f62c9e8f2c59..3b133f24b4ca 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -16,6 +16,14 @@
size_t __ro_after_init kvm_hyp_arm_smmu_v3_count;
struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
+/* strtab accessors */
+#define strtab_log2size(smmu) (FIELD_GET(STRTAB_BASE_CFG_LOG2SIZE, (smmu)->host_ste_cfg))
+#define strtab_size(smmu) ((1UL << strtab_log2size(smmu)) * STRTAB_STE_DWORDS * 8)
+#define strtab_host_base(smmu) ((smmu)->host_ste_base & STRTAB_BASE_ADDR_MASK)
+#define strtab_split(smmu) (FIELD_GET(STRTAB_BASE_CFG_SPLIT, (smmu)->host_ste_cfg))
+#define strtab_l1_size(smmu) ((1UL << (strtab_log2size(smmu) - strtab_split(smmu))) * \
+ (sizeof(struct arm_smmu_strtab_l1)))
+
#define for_each_smmu(smmu) \
for ((smmu) = kvm_hyp_arm_smmu_v3_smmus; \
(smmu) != &kvm_hyp_arm_smmu_v3_smmus[kvm_hyp_arm_smmu_v3_count]; \
@@ -58,6 +66,11 @@ static bool is_cmdq_enabled(struct hyp_arm_smmu_v3_device *smmu)
return FIELD_GET(CR0_CMDQEN, smmu->cr0);
}
+static bool is_smmu_enabled(struct hyp_arm_smmu_v3_device *smmu)
+{
+ return FIELD_GET(CR0_SMMUEN, smmu->cr0);
+}
+
/*
* CMDQ, STE host copies are accessed by the hypervisor, we share them to
* - Prevent the host from passing protected VM memory.
@@ -190,6 +203,11 @@ static void smmu_deinit_device(struct hyp_arm_smmu_v3_device *smmu)
if (smmu->cmdq.base)
WARN_ON(__pkvm_hyp_donate_host(smmu->cmdq.base_dma >> PAGE_SHIFT,
cmdq_size(&smmu->cmdq) >> PAGE_SHIFT));
+
+ if (smmu->strtab_cfg.linear.table ||
+ smmu->strtab_cfg.l2.l1tab)
+ WARN_ON(__pkvm_hyp_donate_host(hyp_phys_to_pfn(smmu->strtab_dma),
+ smmu->strtab_size >> PAGE_SHIFT));
smmu->base = NULL;
}
@@ -265,6 +283,45 @@ static int smmu_init_cmdq(struct hyp_arm_smmu_v3_device *smmu)
return 0;
}
+static int smmu_init_strtab(struct hyp_arm_smmu_v3_device *smmu)
+{
+ struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
+ int ret;
+ u32 reg;
+
+ ret = __pkvm_host_donate_hyp(hyp_phys_to_pfn(smmu->strtab_dma),
+ smmu->strtab_size >> PAGE_SHIFT);
+ if (ret)
+ return ret;
+
+ if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
+ unsigned int last_sid_idx =
+ arm_smmu_strtab_l1_idx((1ULL << smmu->sid_bits) - 1);
+
+ cfg->l2.l1tab = hyp_phys_to_virt(smmu->strtab_dma);
+ cfg->l2.l1_dma = smmu->strtab_dma;
+ cfg->l2.num_l1_ents = min(last_sid_idx + 1, STRTAB_MAX_L1_ENTRIES);
+
+ reg = FIELD_PREP(STRTAB_BASE_CFG_FMT,
+ STRTAB_BASE_CFG_FMT_2LVL) |
+ FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE,
+ ilog2(cfg->l2.num_l1_ents) + STRTAB_SPLIT) |
+ FIELD_PREP(STRTAB_BASE_CFG_SPLIT, STRTAB_SPLIT);
+ } else {
+ cfg->linear.table = hyp_phys_to_virt(smmu->strtab_dma);
+ cfg->linear.ste_dma = smmu->strtab_dma;
+ cfg->linear.num_ents = 1UL << smmu->sid_bits;
+ reg = FIELD_PREP(STRTAB_BASE_CFG_FMT,
+ STRTAB_BASE_CFG_FMT_LINEAR) |
+ FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits);
+ }
+
+ writeq_relaxed((smmu->strtab_dma & STRTAB_BASE_ADDR_MASK) | STRTAB_BASE_RA,
+ smmu->base + ARM_SMMU_STRTAB_BASE);
+ writel_relaxed(reg, smmu->base + ARM_SMMU_STRTAB_BASE_CFG);
+ return 0;
+}
+
static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
{
unsigned long haddr;
@@ -288,6 +345,10 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
if (ret)
goto out_ret;
+ ret = smmu_init_strtab(smmu);
+ if (ret)
+ goto out_ret;
+
return 0;
out_ret:
@@ -422,6 +483,46 @@ static int smmu_emulate_cmdq_insert(struct hyp_arm_smmu_v3_device *smmu)
return ret;
}
+static int smmu_update_ste_shadow(struct hyp_arm_smmu_v3_device *smmu, bool enabled)
+{
+ size_t strtab_size;
+ u32 fmt = FIELD_GET(STRTAB_BASE_CFG_FMT, smmu->host_ste_cfg);
+
+ /* Linux doesn't change the fmt nor size of the strtab in the run time. */
+ if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
+ if ((fmt != STRTAB_BASE_CFG_FMT_2LVL) ||
+ (strtab_split(smmu) != STRTAB_SPLIT) ||
+ (strtab_log2size(smmu) > (ilog2(STRTAB_MAX_L1_ENTRIES) + STRTAB_SPLIT)) ||
+ (strtab_split(smmu) >= strtab_log2size(smmu)))
+ return -EINVAL;
+ strtab_size = strtab_l1_size(smmu);
+ } else {
+ if ((fmt != STRTAB_BASE_CFG_FMT_LINEAR) ||
+ (strtab_log2size(smmu) > smmu->sid_bits))
+ return -EINVAL;
+ strtab_size = strtab_size(smmu);
+ }
+
+ if (enabled)
+ return smmu_share_pages(strtab_host_base(smmu), strtab_size);
+
+ return smmu_unshare_pages(strtab_host_base(smmu), strtab_size);
+}
+
+static void smmu_emulate_enable(struct hyp_arm_smmu_v3_device *smmu)
+{
+ /* Enabling SMMU without CMDQ, means TLB invalidation won't work. */
+ if (WARN_ON(!is_cmdq_enabled(smmu)))
+ return;
+
+ WARN_ON(smmu_update_ste_shadow(smmu, true));
+}
+
+static void smmu_emulate_disable(struct hyp_arm_smmu_v3_device *smmu)
+{
+ WARN_ON(smmu_update_ste_shadow(smmu, false));
+}
+
static void smmu_emulate_cmdq_enable(struct hyp_arm_smmu_v3_device *smmu)
{
u32 shift = smmu->cmdq_host.q_base & Q_BASE_LOG2SIZE;
@@ -509,7 +610,23 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
}
/* Passthrough the register access for bisectiblity, handled later */
case ARM_SMMU_STRTAB_BASE:
+ if (is_write) {
+ /* Must only be written when SMMU_CR0.SMMUEN == 0.*/
+ if (is_smmu_enabled(smmu))
+ break;
+ smmu->host_ste_base = val;
+ }
+ mask = read_write;
+ break;
case ARM_SMMU_STRTAB_BASE_CFG:
+ if (is_write) {
+ /* Must only be written when SMMU_CR0.SMMUEN == 0.*/
+ if (is_smmu_enabled(smmu))
+ break;
+ smmu->host_ste_cfg = val;
+ }
+ mask = read_write;
+ break;
case ARM_SMMU_GBPA:
mask = read_write;
break;
@@ -518,12 +635,17 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
break;
if (is_write) {
bool last_cmdq_en = is_cmdq_enabled(smmu);
+ bool last_smmu_en = is_smmu_enabled(smmu);
smmu->cr0 = val;
if (!last_cmdq_en && is_cmdq_enabled(smmu))
smmu_emulate_cmdq_enable(smmu);
else if (last_cmdq_en && !is_cmdq_enabled(smmu))
smmu_emulate_cmdq_disable(smmu);
+ if (!last_smmu_en && is_smmu_enabled(smmu))
+ smmu_emulate_enable(smmu);
+ else if (last_smmu_en && !is_smmu_enabled(smmu))
+ smmu_emulate_disable(smmu);
}
mask = read_write;
break;
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
index 74a7f62d93eb..085aead009b6 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
@@ -15,6 +15,8 @@
* @mmio_addr base address of the SMMU registers
* @mmio_size size of the registers resource
* @features Features of SMMUv3, subset of the main driver
+ * @strtab_dma Phys address of stream table
+ * @strtab_size Stream table size
*
* Other members are filled and used at runtime by the SMMU driver.
* @base Virtual address of SMMU registers
@@ -27,6 +29,9 @@
* @cmdq CMDQ as observed by HW
* @cmdq_host Host view of the CMDQ, only q_base and llq used.
* @cr0 Last value of CR0
+ * @host_ste_cfg Host stream table config
+ * @host_ste_base Host stream table base
+ * @strtab_cfg Stream table as seen by HW
*/
struct hyp_arm_smmu_v3_device {
phys_addr_t mmio_addr;
@@ -46,6 +51,11 @@ struct hyp_arm_smmu_v3_device {
struct arm_smmu_queue cmdq;
struct arm_smmu_queue cmdq_host;
u32 cr0;
+ dma_addr_t strtab_dma;
+ size_t strtab_size;
+ u64 host_ste_cfg;
+ u64 host_ste_base;
+ struct arm_smmu_strtab_cfg strtab_cfg;
};
extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count);
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 18/24] iommu/arm-smmu-v3-kvm: Shadow STEs
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (16 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 17/24] iommu/arm-smmu-v3-kvm: Shadow stream table Mostafa Saleh
@ 2026-07-15 11:58 ` Mostafa Saleh
2026-07-15 11:59 ` [PATCH v7 19/24] iommu/arm-smmu-v3-kvm: Share other queues Mostafa Saleh
` (5 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Add STE emulation, when the host sends the CFGI_STE command.
Copy the STE as is to the shadow owned by the hypervisor, in the
next patch, stage-2 page table will be attached.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 127 +++++++++++++++++-
1 file changed, 121 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index 3b133f24b4ca..fba3b3e15780 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -23,6 +23,9 @@ struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
#define strtab_split(smmu) (FIELD_GET(STRTAB_BASE_CFG_SPLIT, (smmu)->host_ste_cfg))
#define strtab_l1_size(smmu) ((1UL << (strtab_log2size(smmu) - strtab_split(smmu))) * \
(sizeof(struct arm_smmu_strtab_l1)))
+#define strtab_hyp_base(smmu) ((smmu)->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? \
+ (u64 *)(smmu)->strtab_cfg.l2.l1tab :\
+ (u64 *)(smmu)->strtab_cfg.linear.table)
#define for_each_smmu(smmu) \
for ((smmu) = kvm_hyp_arm_smmu_v3_smmus; \
@@ -283,6 +286,94 @@ static int smmu_init_cmdq(struct hyp_arm_smmu_v3_device *smmu)
return 0;
}
+static int smmu_get_host_l2_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid,
+ struct arm_smmu_ste *host_ste_out)
+{
+ u64 *host_ste_base = hyp_phys_to_virt(strtab_host_base(smmu));
+ struct arm_smmu_strtab_l1 host_l1_desc;
+ struct arm_smmu_strtab_l2 *l2ptr;
+ phys_addr_t host_l2_tab;
+ int ret, i;
+
+ host_l1_desc.l2ptr = READ_ONCE(host_ste_base[arm_smmu_strtab_l1_idx(sid)]);
+ if (!(le64_to_cpu(host_l1_desc.l2ptr) & STRTAB_L1_DESC_SPAN))
+ return -EINVAL;
+
+ host_l2_tab = le64_to_cpu(host_l1_desc.l2ptr) & STRTAB_L1_DESC_L2PTR_MASK;
+ /* Share and pin the table before accessing it. */
+ ret = smmu_share_pages(host_l2_tab, sizeof(struct arm_smmu_strtab_l2));
+ if (ret)
+ return ret;
+
+ l2ptr = hyp_phys_to_virt(host_l2_tab);
+
+ for (i = 0 ; i < STRTAB_STE_DWORDS ; ++i)
+ host_ste_out->data[i] =
+ READ_ONCE(l2ptr->stes[arm_smmu_strtab_l2_idx(sid)].data[i]);
+
+ WARN_ON(smmu_unshare_pages(host_l2_tab, sizeof(struct arm_smmu_strtab_l2)));
+ return 0;
+}
+
+static int smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool leaf)
+{
+ struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
+ struct arm_smmu_ste *hyp_ste_ptr, *host_ste_ptr, host_ste_copy;
+ u64 *hyp_ste_base = strtab_hyp_base(smmu);
+ int ret, i;
+
+ /*
+ * Linux only uses leaf = 1, when leaf is 0, we need to verify that this
+ * is a 2 level table and reshadow of l2.
+ * Also, we rely on Linux only issuing CFGI_STE to attach a device when
+ * the SMMU is enabled.
+ */
+ if (!leaf || !is_smmu_enabled(smmu) ||
+ (sid >= (1UL << strtab_log2size(smmu))))
+ return -EINVAL;
+
+ if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)) {
+ struct arm_smmu_ste *hyp_table = (struct arm_smmu_ste *)hyp_ste_base;
+ u64 *host_ste_base = hyp_phys_to_virt(strtab_host_base(smmu));
+ struct arm_smmu_ste *host_table = (struct arm_smmu_ste *)host_ste_base;
+
+ if (sid >= cfg->linear.num_ents)
+ return -E2BIG;
+
+ hyp_ste_ptr = &hyp_table[sid];
+ host_ste_ptr = &host_table[sid];
+ } else {
+ struct arm_smmu_strtab_l1 *l1tab = (struct arm_smmu_strtab_l1 *)hyp_ste_base;
+ u32 l1_idx = arm_smmu_strtab_l1_idx(sid);
+ struct arm_smmu_strtab_l2 *l2ptr;
+
+ if (l1_idx >= cfg->l2.num_l1_ents)
+ return -E2BIG;
+
+ host_ste_ptr = &host_ste_copy;
+ ret = smmu_get_host_l2_ste(smmu, sid, host_ste_ptr);
+ if (ret)
+ return ret;
+
+ if (!l1tab[l1_idx].l2ptr) {
+ struct arm_smmu_strtab_l2 *l2table;
+
+ /* No hypervisor entry, first time the L2 is populated. */
+ l2table = pkvm_iommu_donate_pages(get_order(sizeof(*l2table)));
+ if (!l2table)
+ return -ENOMEM;
+ arm_smmu_write_strtab_l1_desc(&l1tab[l1_idx], hyp_virt_to_phys(l2table));
+ }
+ l2ptr = hyp_phys_to_virt(le64_to_cpu(l1tab[l1_idx].l2ptr) &
+ STRTAB_L1_DESC_L2PTR_MASK);
+ hyp_ste_ptr = &l2ptr->stes[arm_smmu_strtab_l2_idx(sid)];
+ }
+
+ for (i = 0 ; i < STRTAB_STE_DWORDS ; ++i)
+ WRITE_ONCE(hyp_ste_ptr->data[i], host_ste_ptr->data[i]);
+ return 0;
+}
+
static int smmu_init_strtab(struct hyp_arm_smmu_v3_device *smmu)
{
struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
@@ -396,8 +487,24 @@ static bool smmu_filter_command(struct hyp_arm_smmu_v3_device *smmu, u64 *comman
switch (type) {
case CMDQ_OP_CFGI_STE:
- /* TBD: SHADOW_STE*/
+ {
+ u32 leaf = FIELD_GET(CMDQ_CFGI_1_LEAF, command[1]);
+ u32 sid = FIELD_GET(CMDQ_CFGI_0_SID, command[0]);
+ bool ret;
+
+ /*
+ * If STE update is required flush the CMDQ and drop the lock as that
+ * might require to update the host page table and aquire its lock.
+ */
+ writel(smmu->cmdq.llq.prod, smmu->cmdq.prod_reg);
+ hyp_spin_unlock(&smmu->hw_lock);
+ ret = smmu_reshadow_ste(smmu, sid, leaf);
+ hyp_spin_lock(&smmu->hw_lock);
+ if (ret)
+ return true;
+
break;
+ }
case CMDQ_OP_CFGI_ALL:
{
/*
@@ -608,25 +715,33 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
val = smmu->cmdq_host.llq.cons | (CMDQ_CONS_ERR & cons);
goto out_update_regs;
}
- /* Passthrough the register access for bisectiblity, handled later */
case ARM_SMMU_STRTAB_BASE:
+ if (len != sizeof(u64))
+ break;
if (is_write) {
/* Must only be written when SMMU_CR0.SMMUEN == 0.*/
if (is_smmu_enabled(smmu))
break;
smmu->host_ste_base = val;
+ goto out_ret;
+ } else {
+ val = smmu->host_ste_base;
+ goto out_update_regs;
}
- mask = read_write;
- break;
case ARM_SMMU_STRTAB_BASE_CFG:
+ if (len != sizeof(u32))
+ break;
if (is_write) {
/* Must only be written when SMMU_CR0.SMMUEN == 0.*/
if (is_smmu_enabled(smmu))
break;
smmu->host_ste_cfg = val;
+ goto out_ret;
+ } else {
+ val = smmu->host_ste_cfg;
+ goto out_update_regs;
}
- mask = read_write;
- break;
+ /* Passthrough the register access for bisectiblity, handled later */
case ARM_SMMU_GBPA:
mask = read_write;
break;
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 19/24] iommu/arm-smmu-v3-kvm: Share other queues
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (17 preceding siblings ...)
2026-07-15 11:58 ` [PATCH v7 18/24] iommu/arm-smmu-v3-kvm: Shadow STEs Mostafa Saleh
@ 2026-07-15 11:59 ` Mostafa Saleh
2026-07-15 11:59 ` [PATCH v7 20/24] iommu/arm-smmu-v3-kvm: Emulate GBPA Mostafa Saleh
` (4 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Other queues as PRIQ and EVTQ doesn't need to be shadowed. However, we
need to make sure they are in a state that disallow them to be donated
to the hypervisor or guests. So, keep track of those and share them when
they get enabled.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 78 +++++++++++++++++--
.../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 8 ++
2 files changed, 81 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index fba3b3e15780..11de73640a6f 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -74,6 +74,16 @@ static bool is_smmu_enabled(struct hyp_arm_smmu_v3_device *smmu)
return FIELD_GET(CR0_SMMUEN, smmu->cr0);
}
+static bool is_evtq_enabled(struct hyp_arm_smmu_v3_device *smmu)
+{
+ return FIELD_GET(CR0_EVTQEN, smmu->cr0);
+}
+
+static bool is_priq_enabled(struct hyp_arm_smmu_v3_device *smmu)
+{
+ return FIELD_GET(CR0_PRIQEN, smmu->cr0);
+}
+
/*
* CMDQ, STE host copies are accessed by the hypervisor, we share them to
* - Prevent the host from passing protected VM memory.
@@ -647,6 +657,18 @@ static void smmu_emulate_cmdq_disable(struct hyp_arm_smmu_v3_device *smmu)
cmdq_size(&smmu->cmdq_host)));
}
+static void smmu_emulate_queue(struct hyp_arm_smmu_v3_device *smmu,
+ unsigned long q_base, size_t ent_size_shift)
+{
+ /* Q_BASE_ADDR_MASK is not enough as the SMMU also ignores bits > OAS */
+ phys_addr_t base = q_base & Q_BASE_ADDR_MASK & ((1ULL << smmu->oas) - 1);
+ size_t size = 1UL << (FIELD_GET(Q_BASE_LOG2SIZE, q_base) + ent_size_shift);
+
+ /* Queues are aligned to the size also. */
+ base &= ~(size - 1);
+ WARN_ON(smmu_share_pages(base, size));
+}
+
static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
struct user_pt_regs *regs,
u64 esr, u32 off)
@@ -751,12 +773,34 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
if (is_write) {
bool last_cmdq_en = is_cmdq_enabled(smmu);
bool last_smmu_en = is_smmu_enabled(smmu);
+ bool last_evtq_en = is_evtq_enabled(smmu);
+ bool last_priq_en = is_priq_enabled(smmu);
smmu->cr0 = val;
if (!last_cmdq_en && is_cmdq_enabled(smmu))
smmu_emulate_cmdq_enable(smmu);
else if (last_cmdq_en && !is_cmdq_enabled(smmu))
smmu_emulate_cmdq_disable(smmu);
+
+ /*
+ * Share PRI and EVTQ to avoid the host using them to write to
+ * protected memory. However, do not unshare the queues at disable
+ * as that is more complicated, unsharing from here can lead to
+ * use-after-unshare issues, and requires ordering with cr0ack.
+ * The host can disable those queue during shutdown, but it nevers
+ * changes the base address (even with RPM), so leave the queue
+ * shared and assert that multiple host writes does not change it.
+ */
+ if (!last_evtq_en && is_evtq_enabled(smmu) && !smmu->evtq_shared) {
+ smmu_emulate_queue(smmu, smmu->evtq_base, EVTQ_ENT_SZ_SHIFT);
+ smmu->evtq_shared = true;
+ }
+
+ if (!last_priq_en && is_priq_enabled(smmu) && !smmu->priq_shared) {
+ smmu_emulate_queue(smmu, smmu->priq_base, PRIQ_ENT_SZ_SHIFT);
+ smmu->priq_shared = true;
+ }
+
if (!last_smmu_en && is_smmu_enabled(smmu))
smmu_emulate_enable(smmu);
else if (last_smmu_en && !is_smmu_enabled(smmu))
@@ -780,6 +824,33 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
mask = read_write;
break;
}
+ case ARM_SMMU_EVTQ_BASE:
+ if (len != sizeof(u64))
+ break;
+
+ if (is_write) {
+ /* See ARM_SMMU_CR0 */
+ if (is_evtq_enabled(smmu) ||
+ (smmu->evtq_shared && (smmu->evtq_base != val)))
+ break;
+ smmu->evtq_base = val;
+ }
+ mask = read_write;
+ break;
+
+ case ARM_SMMU_PRIQ_BASE:
+ if (len != sizeof(u64))
+ break;
+
+ if (is_write) {
+ /* See ARM_SMMU_CR0 */
+ if (is_priq_enabled(smmu) ||
+ (smmu->priq_shared && (smmu->priq_base != val)))
+ break;
+ smmu->priq_base = val;
+ }
+ mask = read_write;
+ break;
/* Allowed 32 bit registers. */
case ARM_SMMU_EVTQ_IRQ_CFG1:
@@ -810,15 +881,12 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
case ARM_SMMU_EVTQ_IRQ_CFG0:
case ARM_SMMU_PRIQ_IRQ_CFG0:
case ARM_SMMU_GERROR_IRQ_CFG0:
+ if (len != sizeof(u64))
+ break;
/* These are RES0 as MSI support is hidden. */
val = 0;
if (!is_write)
goto out_update_regs;
- fallthrough;
- case ARM_SMMU_EVTQ_BASE:
- case ARM_SMMU_PRIQ_BASE:
- if (len != sizeof(u64))
- break;
mask = read_write;
break;
/* Allowed RO 32 bit registers. */
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
index 085aead009b6..d96801e433ef 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
@@ -32,6 +32,10 @@
* @host_ste_cfg Host stream table config
* @host_ste_base Host stream table base
* @strtab_cfg Stream table as seen by HW
+ * @evtq_base Host evtq base reg
+ * @priq_base Host priq base reg
+ * @evtq_shared Whether the EVTQ was setup
+ * @priq_shared Whether the PRIQ was setup
*/
struct hyp_arm_smmu_v3_device {
phys_addr_t mmio_addr;
@@ -56,6 +60,10 @@ struct hyp_arm_smmu_v3_device {
u64 host_ste_cfg;
u64 host_ste_base;
struct arm_smmu_strtab_cfg strtab_cfg;
+ unsigned long evtq_base;
+ unsigned long priq_base;
+ bool evtq_shared;
+ bool priq_shared;
};
extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count);
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 20/24] iommu/arm-smmu-v3-kvm: Emulate GBPA
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (18 preceding siblings ...)
2026-07-15 11:59 ` [PATCH v7 19/24] iommu/arm-smmu-v3-kvm: Share other queues Mostafa Saleh
@ 2026-07-15 11:59 ` Mostafa Saleh
2026-07-15 11:59 ` [PATCH v7 21/24] iommu/io-pgtable-arm: Support io-pgtable-arm in the hypervisor Mostafa Saleh
` (3 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
The last bit of emulation is GBPA. it must be always set to ABORT,
as when the SMMU is disabled it’s not allowed for the host to bypass
the SMMU.
That's is done by setting the GBPA to ABORT at init time, and host
writes are always ignored and host reads always return ABORT.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 32 +++++++++++++++++--
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index 11de73640a6f..45dbab1b18ad 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -139,6 +139,22 @@ static bool smmu_cmdq_has_space(struct arm_smmu_queue *cmdq, u32 n)
return queue_has_space(llq, n);
}
+static int smmu_abort_gbpa(struct hyp_arm_smmu_v3_device *smmu)
+{
+ int ret;
+ u32 reg;
+
+ ret = smmu_wait(false,
+ (readl_relaxed(smmu->base + ARM_SMMU_GBPA) & GBPA_UPDATE) == 0);
+ if (ret)
+ return ret;
+
+ reg = readl_relaxed(smmu->base + ARM_SMMU_GBPA);
+ writel_relaxed(GBPA_UPDATE | GBPA_ABORT | reg, smmu->base + ARM_SMMU_GBPA);
+ return smmu_wait(false,
+ (readl_relaxed(smmu->base + ARM_SMMU_GBPA) & GBPA_UPDATE) == 0);
+}
+
static bool smmu_cmdq_full(struct arm_smmu_queue *cmdq)
{
struct arm_smmu_ll_queue *llq = &cmdq->llq;
@@ -450,6 +466,10 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
if (ret)
goto out_ret;
+ ret = smmu_abort_gbpa(smmu);
+ if (ret)
+ goto out_ret;
+
return 0;
out_ret:
@@ -763,10 +783,16 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
val = smmu->host_ste_cfg;
goto out_update_regs;
}
- /* Passthrough the register access for bisectiblity, handled later */
case ARM_SMMU_GBPA:
- mask = read_write;
- break;
+ if (len != sizeof(u32))
+ break;
+
+ /* Ignore write, always read to abort. */
+ if (!is_write) {
+ val = GBPA_ABORT;
+ goto out_update_regs;
+ }
+ goto out_ret;
case ARM_SMMU_CR0:
if (len != sizeof(u32))
break;
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 21/24] iommu/io-pgtable-arm: Support io-pgtable-arm in the hypervisor
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (19 preceding siblings ...)
2026-07-15 11:59 ` [PATCH v7 20/24] iommu/arm-smmu-v3-kvm: Emulate GBPA Mostafa Saleh
@ 2026-07-15 11:59 ` Mostafa Saleh
2026-07-15 11:59 ` [PATCH v7 22/24] iommu/arm-smmu-v3-kvm: Shadow the CPU stage-2 page table Mostafa Saleh
` (2 subsequent siblings)
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
To be able to populate the shadow stage-2 in the hypervisor, compile
io-pgtable-arm object for the hypervisor.
That requires the hypervisor to support iommu-pages, re-defining some
functions as address conversion and stubbing some others as DMA-API.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
arch/arm64/kvm/hyp/nvhe/Makefile | 3 +-
.../arm/arm-smmu-v3/pkvm/io-pgtable-arm-hyp.h | 68 +++++++++++++++++++
drivers/iommu/io-pgtable-arm.c | 39 ++++++++---
drivers/iommu/io-pgtable-arm.h | 17 +++++
4 files changed, 117 insertions(+), 10 deletions(-)
create mode 100644 drivers/iommu/arm/arm-smmu-v3/pkvm/io-pgtable-arm-hyp.h
diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile
index dcb75fb5b4f1..35ac274ab2c0 100644
--- a/arch/arm64/kvm/hyp/nvhe/Makefile
+++ b/arch/arm64/kvm/hyp/nvhe/Makefile
@@ -36,7 +36,8 @@ hyp-obj-y += $(lib-objs)
HYP_SMMU_V3_DRV_PATH = ../../../../../drivers/iommu/arm/arm-smmu-v3
hyp-obj-$(CONFIG_ARM_SMMU_V3_PKVM) += $(HYP_SMMU_V3_DRV_PATH)/pkvm/arm-smmu-v3.o \
- $(HYP_SMMU_V3_DRV_PATH)/arm-smmu-v3-common-lib.o
+ $(HYP_SMMU_V3_DRV_PATH)/arm-smmu-v3-common-lib.o \
+ $(HYP_SMMU_V3_DRV_PATH)/../../io-pgtable-arm.o
# Path to simple_ring_buffer.c
CFLAGS_trace.nvhe.o += -I$(srctree)/kernel/trace/
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/io-pgtable-arm-hyp.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/io-pgtable-arm-hyp.h
new file mode 100644
index 000000000000..c9d20e781aed
--- /dev/null
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/io-pgtable-arm-hyp.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef IO_PGTABLE_ARM_HYP_H_
+#define IO_PGTABLE_ARM_HYP_H_
+
+#include <nvhe/memory.h>
+#include <nvhe/iommu.h>
+
+#undef WARN_ONCE
+#define WARN_ONCE(condition, format...) WARN_ON(condition)
+
+static inline void *iommu_alloc_pages_node_sz(int nid, gfp_t gfp, size_t size)
+{
+ return pkvm_iommu_donate_pages(get_order(size));
+}
+
+static inline void iommu_free_pages(void *virt)
+{
+ pkvm_iommu_reclaim_pages(virt);
+}
+
+static inline void *arm_lpae_alloc_data(size_t size)
+{
+ return pkvm_iommu_donate_pages(get_order(size));
+}
+
+static inline void arm_lpae_free_data(void *p)
+{
+ pkvm_iommu_reclaim_pages(p);
+}
+
+#undef phys_to_virt
+#define phys_to_virt(x) hyp_phys_to_virt(x)
+
+#undef virt_to_phys
+#define virt_to_phys(x) hyp_virt_to_phys(x)
+
+/* Stubs used by io-pgtable-arm but no relevant for hypervisor object. */
+#undef dma_map_single
+#define dma_map_single(d, p, s, dir) (virt_to_phys(p))
+
+#undef dma_unmap_single
+#define dma_unmap_single(d, a, s, r) do { (void)(d); (void)(a); (void)(s); (void)(r); } while (0)
+
+#define dma_mapping_error(...) (0)
+
+#undef dev_err
+#define dev_err(dev, format, ...)
+
+static inline int iommu_pages_start_incoherent(void *virt, struct device *dma_dev)
+{
+ return 0;
+}
+
+static inline void iommu_pages_free_incoherent(void *virt,
+ struct device *dma_dev)
+{
+}
+
+static inline void iommu_pages_flush_incoherent(struct device *dma_dev,
+ void *virt, size_t offset,
+ size_t len)
+{
+}
+
+struct io_pgtable_ops *kvm_alloc_io_pgtable_ops(enum io_pgtable_fmt fmt,
+ struct io_pgtable_cfg *cfg,
+ void *cookie);
+#endif /* IO_PGTABLE_ARM_HYP_H_ */
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 476c0e25631a..cf71087e4d3a 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -20,7 +20,6 @@
#include <asm/barrier.h>
#include "io-pgtable-arm.h"
-#include "iommu-pages.h"
#define ARM_LPAE_MAX_ADDR_BITS 52
#define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
@@ -301,6 +300,7 @@ static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
{
struct device *dev = cfg->iommu_dev;
void *pages;
+ int nid = dev ? dev_to_node(dev) : NUMA_NO_NODE;
/*
* For very small starting-level translation tables the HW requires a
@@ -311,7 +311,7 @@ static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
if (cfg->alloc)
return __arm_lpae_cfg_alloc(size, gfp, cfg, cookie);
- pages = iommu_alloc_pages_node_sz(dev_to_node(dev), gfp, size);
+ pages = iommu_alloc_pages_node_sz(nid, gfp, size);
if (!pages)
return NULL;
@@ -350,8 +350,7 @@ static void __arm_lpae_free_pages(void *pages, size_t size,
static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, int num_entries,
struct io_pgtable_cfg *cfg)
{
- dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep),
- sizeof(*ptep) * num_entries, DMA_TO_DEVICE);
+ iommu_pages_flush_incoherent(cfg->iommu_dev, ptep, 0, sizeof(*ptep) * num_entries);
}
static void __arm_lpae_clear_pte(arm_lpae_iopte *ptep, struct io_pgtable_cfg *cfg, int num_entries)
@@ -650,7 +649,7 @@ static void arm_lpae_free_pgtable(struct io_pgtable *iop)
struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
__arm_lpae_free_pgtable(data, data->start_level, data->pgd);
- kfree(data);
+ arm_lpae_free_data(data);
}
static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
@@ -964,7 +963,7 @@ arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS)
return NULL;
- data = kmalloc_obj(*data);
+ data = arm_lpae_alloc_data(sizeof(*data));
if (!data)
return NULL;
@@ -1091,7 +1090,7 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
return &data->iop;
out_free_data:
- kfree(data);
+ arm_lpae_free_data(data);
return NULL;
}
@@ -1187,7 +1186,7 @@ arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
return &data->iop;
out_free_data:
- kfree(data);
+ arm_lpae_free_data(data);
return NULL;
}
@@ -1266,7 +1265,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
return &data->iop;
out_free_data:
- kfree(data);
+ arm_lpae_free_data(data);
return NULL;
}
@@ -1299,3 +1298,25 @@ struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns = {
.alloc = arm_mali_lpae_alloc_pgtable,
.free = arm_lpae_free_pgtable,
};
+
+#ifdef __KVM_NVHE_HYPERVISOR__
+struct io_pgtable_ops *kvm_alloc_io_pgtable_ops(enum io_pgtable_fmt fmt,
+ struct io_pgtable_cfg *cfg,
+ void *cookie)
+{
+ struct io_pgtable *iop;
+
+ if (fmt != ARM_64_LPAE_S2)
+ return NULL;
+
+ iop = arm_64_lpae_alloc_pgtable_s2(cfg, cookie);
+ if (!iop)
+ return NULL;
+
+ iop->fmt = fmt;
+ iop->cookie = cookie;
+ iop->cfg = *cfg;
+
+ return &iop->ops;
+}
+#endif
\ No newline at end of file
diff --git a/drivers/iommu/io-pgtable-arm.h b/drivers/iommu/io-pgtable-arm.h
index ba7cfdf7afa0..fd5c5ff2b550 100644
--- a/drivers/iommu/io-pgtable-arm.h
+++ b/drivers/iommu/io-pgtable-arm.h
@@ -27,4 +27,21 @@
#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
+#ifndef __KVM_NVHE_HYPERVISOR__
+#include "iommu-pages.h"
+
+static inline void *arm_lpae_alloc_data(size_t size)
+{
+ return kmalloc(size, GFP_KERNEL);
+}
+
+static inline void arm_lpae_free_data(void *p)
+{
+ kfree(p);
+}
+
+#else
+#include "arm/arm-smmu-v3/pkvm/io-pgtable-arm-hyp.h"
+#endif
+
#endif /* IO_PGTABLE_ARM_H_ */
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 22/24] iommu/arm-smmu-v3-kvm: Shadow the CPU stage-2 page table
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (20 preceding siblings ...)
2026-07-15 11:59 ` [PATCH v7 21/24] iommu/io-pgtable-arm: Support io-pgtable-arm in the hypervisor Mostafa Saleh
@ 2026-07-15 11:59 ` Mostafa Saleh
2026-07-15 11:59 ` [PATCH v7 23/24] iommu/arm-smmu-v3-kvm: Enable nesting Mostafa Saleh
2026-07-15 11:59 ` [PATCH v7 24/24] KVM: arm64: Add documentation for pKVM DMA isolation Mostafa Saleh
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Based on the callbacks from the hypervisor, update the SMMUv3
Identity mapped page table.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 249 +++++++++++++++++-
.../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 2 +
2 files changed, 249 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index 45dbab1b18ad..f30757dd9b11 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -13,6 +13,9 @@
#include "arm_smmu_v3.h"
+#include <linux/io-pgtable.h>
+#include "../../../io-pgtable-arm.h"
+
size_t __ro_after_init kvm_hyp_arm_smmu_v3_count;
struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
@@ -64,6 +67,9 @@ struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
__ret; \
})
+/* Protected by host_mmu.lock from core code. */
+static struct io_pgtable *idmap_pgtable;
+
static bool is_cmdq_enabled(struct hyp_arm_smmu_v3_device *smmu)
{
return FIELD_GET(CR0_CMDQEN, smmu->cr0);
@@ -211,7 +217,6 @@ static int smmu_sync_cmd(struct hyp_arm_smmu_v3_device *smmu)
smmu_cmdq_empty(&smmu->cmdq));
}
-__maybe_unused
static int smmu_send_cmd(struct hyp_arm_smmu_v3_device *smmu,
struct arm_smmu_cmd *cmd)
{
@@ -224,6 +229,69 @@ static int smmu_send_cmd(struct hyp_arm_smmu_v3_device *smmu,
return smmu_sync_cmd(smmu);
}
+static void __smmu_add_cmd(void *__opaque, struct arm_smmu_cmdq_batch *unused,
+ struct arm_smmu_cmd *cmd)
+{
+ struct hyp_arm_smmu_v3_device *smmu = (struct hyp_arm_smmu_v3_device *)__opaque;
+
+ WARN_ON(smmu_add_cmd(smmu, cmd));
+}
+
+static int smmu_tlb_inv_range_smmu(struct hyp_arm_smmu_v3_device *smmu,
+ struct arm_smmu_cmd *cmd,
+ unsigned long iova, size_t size, size_t granule,
+ bool leaf)
+{
+ arm_smmu_tlb_inv_build(cmd, iova, size, granule,
+ PAGE_SHIFT, smmu->features & ARM_SMMU_FEAT_RANGE_INV,
+ smmu, leaf, __smmu_add_cmd, NULL);
+ return smmu_sync_cmd(smmu);
+}
+
+static void smmu_tlb_inv_range(unsigned long iova, size_t size, size_t granule,
+ bool leaf)
+{
+ struct arm_smmu_cmd cmd_s1 = arm_smmu_make_cmd_op(CMDQ_OP_TLBI_NH_ALL);
+ struct hyp_arm_smmu_v3_device *smmu;
+
+ for_each_smmu(smmu) {
+ struct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_TLBI_S2_IPA);
+
+ hyp_spin_lock(&smmu->hw_lock);
+ /*
+ * Don't bother if SMMU is disabled, this would be useful for the case
+ * when RPM is supported to avoid touching the SMMU MMIO when disabled.
+ * The hypervisor also asserts CMDQEN is enabled before the SMMU is
+ * enabled. As otherwise the host can prevent the hypervisor from doing
+ * TLB invalidations.
+ * When the SMMU is re-enabled the hypervisor clean the TLBs.
+ */
+ if (smmu->active) {
+ WARN_ON(smmu_tlb_inv_range_smmu(smmu, &cmd, iova, size, granule, leaf));
+ WARN_ON(smmu_send_cmd(smmu, &cmd_s1));
+ }
+ hyp_spin_unlock(&smmu->hw_lock);
+ }
+}
+
+static void smmu_tlb_flush_walk(unsigned long iova, size_t size,
+ size_t granule, void *cookie)
+{
+ smmu_tlb_inv_range(iova, size, granule, false);
+}
+
+static void smmu_tlb_add_page(struct iommu_iotlb_gather *gather,
+ unsigned long iova, size_t granule,
+ void *cookie)
+{
+ smmu_tlb_inv_range(iova, granule, granule, true);
+}
+
+static const struct iommu_flush_ops smmu_tlb_ops = {
+ .tlb_flush_walk = smmu_tlb_flush_walk,
+ .tlb_add_page = smmu_tlb_add_page,
+};
+
/* Put the device in a state that can be probed by the host driver. */
static void smmu_deinit_device(struct hyp_arm_smmu_v3_device *smmu)
{
@@ -477,6 +545,38 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
return ret;
}
+static int smmu_init_pgt(void)
+{
+ /* Default values overridden based on SMMUs common features. */
+ struct io_pgtable_cfg cfg = (struct io_pgtable_cfg) {
+ .tlb = &smmu_tlb_ops,
+ .pgsize_bitmap = -1,
+ .ias = 48,
+ .oas = 48,
+ .coherent_walk = true,
+ .quirks = IO_PGTABLE_QUIRK_NO_WARN,
+ };
+ struct hyp_arm_smmu_v3_device *smmu;
+ struct io_pgtable_ops *ops;
+
+ for_each_smmu(smmu) {
+ cfg.ias = min(cfg.ias, smmu->oas);
+ cfg.oas = min(cfg.oas, smmu->oas);
+ cfg.pgsize_bitmap &= smmu->pgsize_bitmap;
+ cfg.coherent_walk &= !!(smmu->features & ARM_SMMU_FEAT_COHERENCY);
+ }
+
+ /* At least PAGE_SIZE must be supported by all SMMUs*/
+ if ((cfg.pgsize_bitmap & PAGE_SIZE) == 0)
+ return -EINVAL;
+
+ ops = kvm_alloc_io_pgtable_ops(ARM_64_LPAE_S2, &cfg, NULL);
+ if (!ops)
+ return -ENOMEM;
+ idmap_pgtable = io_pgtable_ops_to_pgtable(ops);
+ return 0;
+}
+
/* Called while is the host is still trusted. */
static int smmu_init(void)
{
@@ -502,7 +602,10 @@ static int smmu_init(void)
BUILD_BUG_ON(sizeof(hyp_spinlock_t) != sizeof(u32));
- return 0;
+ ret = smmu_init_pgt();
+ if (ret)
+ goto out_reclaim_smmu;
+ return ret;
out_reclaim_smmu:
while (smmu != kvm_hyp_arm_smmu_v3_smmus)
@@ -646,6 +749,34 @@ static int smmu_update_ste_shadow(struct hyp_arm_smmu_v3_device *smmu, bool enab
return smmu_unshare_pages(strtab_host_base(smmu), strtab_size);
}
+static int smmu_flush_all_tlb(struct hyp_arm_smmu_v3_device *smmu)
+{
+ int ret;
+ u32 cr0;
+ struct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_TLBI_NSNH_ALL);
+
+ hyp_spin_lock(&smmu->hw_lock);
+ /*
+ * This must be called when the SMMU is getting enabled.
+ * First enable the cmdq and then invalidate the TLB.
+ */
+ cr0 = readl_relaxed(smmu->base + ARM_SMMU_CR0);
+ if (!(cr0 & CR0_CMDQEN)) {
+ cr0 |= CR0_CMDQEN;
+ writel_relaxed(cr0, smmu->base + ARM_SMMU_CR0);
+ ret = smmu_wait(false,
+ readl_relaxed(smmu->base + ARM_SMMU_CR0ACK) == cr0);
+ if (ret) {
+ hyp_spin_unlock(&smmu->hw_lock);
+ return ret;
+ }
+ }
+
+ ret = smmu_send_cmd(smmu, &cmd);
+ hyp_spin_unlock(&smmu->hw_lock);
+ return ret;
+}
+
static void smmu_emulate_enable(struct hyp_arm_smmu_v3_device *smmu)
{
/* Enabling SMMU without CMDQ, means TLB invalidation won't work. */
@@ -653,6 +784,8 @@ static void smmu_emulate_enable(struct hyp_arm_smmu_v3_device *smmu)
return;
WARN_ON(smmu_update_ste_shadow(smmu, true));
+ /* Clean the TLBs each time the SMMU is enabled. */
+ WARN_ON(smmu_flush_all_tlb(smmu));
}
static void smmu_emulate_disable(struct hyp_arm_smmu_v3_device *smmu)
@@ -673,6 +806,13 @@ static void smmu_emulate_cmdq_enable(struct hyp_arm_smmu_v3_device *smmu)
static void smmu_emulate_cmdq_disable(struct hyp_arm_smmu_v3_device *smmu)
{
+ /*
+ * We can not enable the SMMU if the CMDQ is enabled and similarly
+ * we can not disable the CMDQ if the SMMU is enabled, as that can
+ * lead to stale TLBs.
+ */
+ WARN_ON(is_smmu_enabled(smmu));
+
WARN_ON(smmu_unshare_pages(smmu->cmdq_host.base_dma,
cmdq_size(&smmu->cmdq_host)));
}
@@ -936,6 +1076,18 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
else
writel_relaxed(val & mask, smmu->base + off);
+ /*
+ * Make sure writes to CR0 are immediately observed, that is important
+ * when synchronizing with TLB invalidation as reading CR0 is enough
+ * to deduce the SMMU state, and we have to enforce the ack with the
+ * hw_lock aquired.
+ */
+ if (off == ARM_SMMU_CR0) {
+ WARN_ON(smmu_wait(false,
+ readl_relaxed(smmu->base + ARM_SMMU_CR0ACK) == (val & mask)));
+ smmu->active = !!(val & CR0_CMDQEN);
+ }
+
hyp_spin_unlock(&smmu->hw_lock);
return true;
}
@@ -973,8 +1125,101 @@ static bool smmu_dabt_handler(struct user_pt_regs *regs, u64 esr, u64 addr)
return false;
}
+static size_t smmu_pgsize_idmap(size_t size, u64 paddr, size_t pgsize_bitmap)
+{
+ size_t pgsizes;
+
+ /* Remove page sizes that are larger than the current size */
+ pgsizes = pgsize_bitmap & GENMASK_ULL(__fls(size), 0);
+
+ /* Remove page sizes that the address is not aligned to. */
+ if (likely(paddr))
+ pgsizes &= GENMASK_ULL(__ffs(paddr), 0);
+
+ WARN_ON(!pgsizes);
+
+ /* Return the largest page size that fits. */
+ return BIT(__fls(pgsizes));
+}
+
static int smmu_host_stage2_idmap(phys_addr_t start, phys_addr_t end, int prot)
{
+ size_t pgsize = PAGE_SIZE, pgcount, size;
+ struct io_pgtable *pgtable = idmap_pgtable;
+ int ret = 0;
+
+ end = min(end, BIT(pgtable->cfg.oas));
+ if (start >= end)
+ return 0;
+
+ size = end - start;
+ if (prot) {
+ size_t mapped;
+
+ if (!(prot & IOMMU_MMIO))
+ prot |= IOMMU_CACHE;
+
+ while (size) {
+ mapped = 0;
+ /*
+ * We handle pages size for memory and MMIO differently:
+ * - memory: Map everything with PAGE_SIZE, that is guaranteed to
+ * find memory as we allocated enough pages to cover the entire
+ * memory, we do that as io-pgtable-arm doesn't support
+ * split_blk_unmap logic any more, so we can't break blocks once
+ * mapped to tables.
+ * - MMIO: Unlike memory, pKVM allocate 1G to for all MMIO, while
+ * the MMIO space can be large, as it is assumed to cover the
+ * whole IAS that is not memory, we have to use block mappings,
+ * that is fine for MMIO as it is never donated at the moment,
+ * so we never need to unmap MMIO at the run time triggereing
+ * split block logic.
+ */
+ if (prot & IOMMU_MMIO)
+ pgsize = smmu_pgsize_idmap(size, start, pgtable->cfg.pgsize_bitmap);
+
+ pgcount = size / pgsize;
+ ret = pgtable->ops.map_pages(&pgtable->ops, start, start,
+ pgsize, pgcount, prot, 0, &mapped);
+ size -= mapped;
+ start += mapped;
+
+ if (ret == -EEXIST) {
+ /*
+ * It is possible to get EEXIST when a VM dies with pages
+ * in a shared state.
+ */
+ ret = 0;
+ size -= pgsize;
+ start += pgsize;
+ continue;
+ }
+ /* Map failures doesn't impact security, tolerate it. */
+ if (!mapped || ret)
+ break;
+ }
+ } else {
+ struct iommu_iotlb_gather gather;
+ size_t unmapped;
+
+ while (size) {
+ pgcount = size / pgsize;
+ iommu_iotlb_gather_init(&gather);
+ unmapped = pgtable->ops.unmap_pages(&pgtable->ops, start,
+ pgsize, pgcount, &gather);
+ size -= unmapped;
+ start += unmapped;
+ if (!unmapped)
+ break;
+ }
+ }
+
+ if (ret)
+ return ret;
+
+ if (WARN_ON(size))
+ return -EINVAL;
+
return 0;
}
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
index d96801e433ef..9599809b46fc 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h
@@ -29,6 +29,7 @@
* @cmdq CMDQ as observed by HW
* @cmdq_host Host view of the CMDQ, only q_base and llq used.
* @cr0 Last value of CR0
+ * @active Is SMMU HW cmdq usable, protected by hw_lock
* @host_ste_cfg Host stream table config
* @host_ste_base Host stream table base
* @strtab_cfg Stream table as seen by HW
@@ -55,6 +56,7 @@ struct hyp_arm_smmu_v3_device {
struct arm_smmu_queue cmdq;
struct arm_smmu_queue cmdq_host;
u32 cr0;
+ bool active;
dma_addr_t strtab_dma;
size_t strtab_size;
u64 host_ste_cfg;
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 23/24] iommu/arm-smmu-v3-kvm: Enable nesting
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (21 preceding siblings ...)
2026-07-15 11:59 ` [PATCH v7 22/24] iommu/arm-smmu-v3-kvm: Shadow the CPU stage-2 page table Mostafa Saleh
@ 2026-07-15 11:59 ` Mostafa Saleh
2026-07-15 11:59 ` [PATCH v7 24/24] KVM: arm64: Add documentation for pKVM DMA isolation Mostafa Saleh
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Now, as the hypervisor controls the command queue, stream table,
and shadows the stage-2 page table.
Enable stage-2 in case the host puts an STE in bypass or stage-1.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 109 ++++++++++++++++--
1 file changed, 102 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index f30757dd9b11..4625240a5de2 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -380,6 +380,59 @@ static int smmu_init_cmdq(struct hyp_arm_smmu_v3_device *smmu)
return 0;
}
+static int smmu_attach_stage_2(struct arm_smmu_ste *ste)
+{
+ unsigned long vttbr;
+ unsigned long ts, sl, ic, oc, sh, tg, ps;
+ unsigned long cfg;
+ struct io_pgtable_cfg *pgt_cfg = &idmap_pgtable->cfg;
+
+ cfg = FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(ste->data[0]));
+ if (!FIELD_GET(STRTAB_STE_0_V, le64_to_cpu(ste->data[0])) ||
+ (cfg == STRTAB_STE_0_CFG_ABORT)) {
+ ste->data[2] = 0;
+ ste->data[3] = 0;
+ return 0;
+ }
+ /* S2 is not advertised, that should never be attempted. */
+ if (cfg == STRTAB_STE_0_CFG_NESTED)
+ return -EINVAL;
+ vttbr = pgt_cfg->arm_lpae_s2_cfg.vttbr;
+ ps = pgt_cfg->arm_lpae_s2_cfg.vtcr.ps;
+ tg = pgt_cfg->arm_lpae_s2_cfg.vtcr.tg;
+ sh = pgt_cfg->arm_lpae_s2_cfg.vtcr.sh;
+ oc = pgt_cfg->arm_lpae_s2_cfg.vtcr.orgn;
+ ic = pgt_cfg->arm_lpae_s2_cfg.vtcr.irgn;
+ sl = pgt_cfg->arm_lpae_s2_cfg.vtcr.sl;
+ ts = pgt_cfg->arm_lpae_s2_cfg.vtcr.tsz;
+
+ ste->data[1] &= ~cpu_to_le64(STRTAB_STE_1_SHCFG);
+ ste->data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, STRTAB_STE_1_SHCFG_INCOMING));
+
+ ste->data[1] &= ~cpu_to_le64(STRTAB_STE_1_EATS | STRTAB_STE_1_S2FWB);
+
+ /* The host shouldn't write dwords 2 and 3, overwrite them. */
+ ste->data[2] = cpu_to_le64(FIELD_PREP(STRTAB_STE_2_VTCR,
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, ps) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, tg) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2SH0, sh) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2OR0, oc) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, ic) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, sl) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, ts)) |
+ FIELD_PREP(STRTAB_STE_2_S2VMID, 0) |
+ STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2R |
+ #ifdef __BIG_ENDIAN
+ STRTAB_STE_2_S2ENDI |
+#endif
+ STRTAB_STE_2_S2PTW);
+
+ ste->data[3] = cpu_to_le64(vttbr & STRTAB_STE_3_S2TTB_MASK);
+ /* Convert S1 => nested and bypass => S2 */
+ ste->data[0] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_0_CFG, cfg | BIT(1)));
+ return 0;
+}
+
static int smmu_get_host_l2_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid,
struct arm_smmu_ste *host_ste_out)
{
@@ -412,8 +465,12 @@ static int smmu_get_host_l2_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid,
static int smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool leaf)
{
struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
- struct arm_smmu_ste *hyp_ste_ptr, *host_ste_ptr, host_ste_copy;
+ struct arm_smmu_ste *hyp_ste_ptr;
u64 *hyp_ste_base = strtab_hyp_base(smmu);
+ struct arm_smmu_ste target = {};
+ struct arm_smmu_cmd cfgi_cmd = arm_smmu_make_cmd_cfgi_ste(sid, true);
+ bool cur_valid, target_valid;
+ u32 target_cfg;
int ret, i;
/*
@@ -435,7 +492,7 @@ static int smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool
return -E2BIG;
hyp_ste_ptr = &hyp_table[sid];
- host_ste_ptr = &host_table[sid];
+ memcpy(target.data, host_table[sid].data, STRTAB_STE_DWORDS << 3);
} else {
struct arm_smmu_strtab_l1 *l1tab = (struct arm_smmu_strtab_l1 *)hyp_ste_base;
u32 l1_idx = arm_smmu_strtab_l1_idx(sid);
@@ -444,8 +501,7 @@ static int smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool
if (l1_idx >= cfg->l2.num_l1_ents)
return -E2BIG;
- host_ste_ptr = &host_ste_copy;
- ret = smmu_get_host_l2_ste(smmu, sid, host_ste_ptr);
+ ret = smmu_get_host_l2_ste(smmu, sid, &target);
if (ret)
return ret;
@@ -463,9 +519,48 @@ static int smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool
hyp_ste_ptr = &l2ptr->stes[arm_smmu_strtab_l2_idx(sid)];
}
- for (i = 0 ; i < STRTAB_STE_DWORDS ; ++i)
- WRITE_ONCE(hyp_ste_ptr->data[i], host_ste_ptr->data[i]);
- return 0;
+ /*
+ * Summary of each host emulated state vs real HW.
+ * | Host | HW |
+ * ==============================
+ * | V=0 | V=0 |
+ * | Abort | Abort |
+ * | Bypass | S2 |
+ * | S1 | S1+S2 |
+ *
+ * For the host, any V=0 transition is not hitless, all other permutations of
+ * (abort, bypass, S1) transitions are hitless.
+ * For the HW state, any V=0 transition is not hitless, as all the S2 config is
+ * always the same (ttbr, vtcr...), all other transitions should be hitless too.
+ * However, the host is not trusted, which means that any V=0 <=> V=1 transitions
+ * or any transition to an abort STE we need to enforce writing order of the STE
+ * dword 0 and add CFGI.
+ * Otherwise, we write the STE in the opposite order to cover cases from abort
+ * to S2 or nested.
+ */
+ ret = smmu_attach_stage_2(&target);
+ if (ret)
+ return ret;
+ hyp_spin_lock(&smmu->hw_lock);
+ cur_valid = FIELD_GET(STRTAB_STE_0_V, le64_to_cpu(hyp_ste_ptr->data[0]));
+ target_cfg = FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(target.data[0]));
+ target_valid = FIELD_GET(STRTAB_STE_0_V, le64_to_cpu(target.data[0]));
+ if ((cur_valid && !target_valid) ||
+ (target_cfg == STRTAB_STE_0_CFG_ABORT)) {
+ WRITE_ONCE(hyp_ste_ptr->data[0], target.data[0]);
+ WARN_ON(smmu_send_cmd(smmu, &cfgi_cmd));
+ for (i = 1; i < STRTAB_STE_DWORDS; i++)
+ WRITE_ONCE(hyp_ste_ptr->data[i], target.data[i]);
+ } else {
+ for (i = 1; i < STRTAB_STE_DWORDS; i++)
+ WRITE_ONCE(hyp_ste_ptr->data[i], target.data[i]);
+ WARN_ON(smmu_send_cmd(smmu, &cfgi_cmd));
+ WRITE_ONCE(hyp_ste_ptr->data[0], target.data[0]);
+ }
+
+ ret = smmu_send_cmd(smmu, &cfgi_cmd);
+ hyp_spin_unlock(&smmu->hw_lock);
+ return ret;
}
static int smmu_init_strtab(struct hyp_arm_smmu_v3_device *smmu)
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 24/24] KVM: arm64: Add documentation for pKVM DMA isolation
2026-07-15 11:58 [PATCH v7 00/24] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
` (22 preceding siblings ...)
2026-07-15 11:59 ` [PATCH v7 23/24] iommu/arm-smmu-v3-kvm: Enable nesting Mostafa Saleh
@ 2026-07-15 11:59 ` Mostafa Saleh
23 siblings, 0 replies; 29+ messages in thread
From: Mostafa Saleh @ 2026-07-15 11:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kvmarm, iommu
Cc: catalin.marinas, will, maz, oliver.upton, joey.gouly,
suzuki.poulose, yuzenghui, joro, jgg, mark.rutland, qperret,
tabba, vdonnefort, sebastianene, keirf, Mostafa Saleh
Populate the section for DMA isolation in pKVM with the newly
added KVM IOMMU and pKVM SMMUv3 driver details.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
Documentation/virt/kvm/arm/pkvm.rst | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/Documentation/virt/kvm/arm/pkvm.rst b/Documentation/virt/kvm/arm/pkvm.rst
index 514992a79a83..ce67e2ae1f9a 100644
--- a/Documentation/virt/kvm/arm/pkvm.rst
+++ b/Documentation/virt/kvm/arm/pkvm.rst
@@ -77,7 +77,28 @@ Status: **Unimplemented.**
DMA isolation using an IOMMU
----------------------------
-Status: **Unimplemented.**
+Status: Supported for devices behind SMMUv3 supporting dual stages
+of translation.
+
+With ``CONFIG_ARM_SMMU_V3_PKVM``, the hypervisor will take over the SMMUs
+on the system and provide an architectural emulation to the kernel SMMUv3
+driver.
+
+If some devices are not behind an IOMMU or behind another IOMMU architecture,
+DMA isolation is not supported, as a driver must be provided for that.
+
+DMA isolation is enforced by dual stages of translation; similar to the CPU
+where a driver can register their ops through ``kvm_iommu_register_driver``
+and implement ``host_stage2_idmap`` to shadow the CPU page table.
+
+The page tables for the stage-2 SMMUv3 will be allocated from a pool created
+at boot with size configured from the command line "kvm-arm.iommu_pgt_mem"
+The size must cover the worst case scenario for leaf mappings of system memory.
+
+This implementation trusts the system firmware not to allow the untrusted
+host kernel to bypass the SMMUv3.
+For example, by resetting the power. In that case, it is the firmware's
+responsibility to save/restore the SMMUv3 state.
Proxying of Trustzone services
------------------------------
--
2.55.0.141.g00534a21ce-goog
^ permalink raw reply related [flat|nested] 29+ messages in thread