* [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 6:21 ` Philippe Mathieu-Daudé
2026-08-05 14:05 ` Daniel P. Berrangé
2026-07-24 0:09 ` [PATCH 02/27] hw/arm: implement TYPE_TARGET_SPECIFIC Pierrick Bouvier
` (27 subsequent siblings)
28 siblings, 2 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
In the next commits, We'll replace the logic to filter QOM types per
target from a static one (based on INTERFACES) to a runtime one, based
on is_available() function, that can be overriden per class.
Introduce the new interface we'll use for that.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
include/qemu/target-info-qom.h | 15 +++++++++++++++
target-info-qom.c | 5 +++++
2 files changed, 20 insertions(+)
diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
index 91be415ed33..83eb537333b 100644
--- a/include/qemu/target-info-qom.h
+++ b/include/qemu/target-info-qom.h
@@ -14,6 +14,21 @@
#define TYPE_TARGET_INFO "target-info"
+#define TYPE_TARGET_SPECIFIC "target-specific"
+
+typedef struct TargetSpecific TargetSpecific;
+
+typedef struct TargetSpecificClass {
+ InterfaceClass parent_class;
+
+ bool (*is_available)(void);
+} TargetSpecificClass;
+
+#define TARGET_SPECIFIC(obj) \
+ INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
+DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
+ TYPE_TARGET_SPECIFIC)
+
typedef struct TargetInfoQom {
Object parent_obj;
} TargetInfoQom;
diff --git a/target-info-qom.c b/target-info-qom.c
index 7958a5cc685..1388691657c 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -16,6 +16,11 @@
#include "hw/riscv/machines-qom.h"
static const TypeInfo target_info_types[] = {
+ {
+ .name = TYPE_TARGET_SPECIFIC,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(TargetSpecificClass),
+ },
{
.name = TYPE_TARGET_ARM_MACHINE,
.parent = TYPE_INTERFACE,
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-07-24 0:09 ` [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface Pierrick Bouvier
@ 2026-07-24 6:21 ` Philippe Mathieu-Daudé
2026-07-24 16:54 ` Pierrick Bouvier
2026-08-05 14:05 ` Daniel P. Berrangé
1 sibling, 1 reply; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-24 6:21 UTC (permalink / raw)
To: Pierrick Bouvier, qemu-devel
Cc: Nicholas Piggin, Daniel Henrique Barboza, Bernhard Beschow,
Anton Johansson, Alistair Francis, Peter Maydell,
Alistair Francis
On 24/7/26 02:09, Pierrick Bouvier wrote:
> In the next commits, We'll replace the logic to filter QOM types per
> target from a static one (based on INTERFACES) to a runtime one, based
> on is_available() function, that can be overriden per class.
>
> Introduce the new interface we'll use for that.
>
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
> include/qemu/target-info-qom.h | 15 +++++++++++++++
> target-info-qom.c | 5 +++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
> index 91be415ed33..83eb537333b 100644
> --- a/include/qemu/target-info-qom.h
> +++ b/include/qemu/target-info-qom.h
> @@ -14,6 +14,21 @@
>
> #define TYPE_TARGET_INFO "target-info"
>
> +#define TYPE_TARGET_SPECIFIC "target-specific"
> +
> +typedef struct TargetSpecific TargetSpecific;
> +
> +typedef struct TargetSpecificClass {
> + InterfaceClass parent_class;
> +
> + bool (*is_available)(void);
Hopefully we won't have to call this with heterogeneous machines.
Otherwise we might have to add another helper:
bool (*is_available_ti)(const TargetInfo *ti);
> +} TargetSpecificClass;
> +
> +#define TARGET_SPECIFIC(obj) \
> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
> + TYPE_TARGET_SPECIFIC)
> +
> typedef struct TargetInfoQom {
> Object parent_obj;
> } TargetInfoQom;
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-07-24 6:21 ` Philippe Mathieu-Daudé
@ 2026-07-24 16:54 ` Pierrick Bouvier
0 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 16:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Nicholas Piggin, Daniel Henrique Barboza, Bernhard Beschow,
Anton Johansson, Alistair Francis, Peter Maydell,
Alistair Francis
On 7/23/2026 11:21 PM, Philippe Mathieu-Daudé wrote:
> On 24/7/26 02:09, Pierrick Bouvier wrote:
>> In the next commits, We'll replace the logic to filter QOM types per
>> target from a static one (based on INTERFACES) to a runtime one, based
>> on is_available() function, that can be overriden per class.
>>
>> Introduce the new interface we'll use for that.
>>
>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>> ---
>> include/qemu/target-info-qom.h | 15 +++++++++++++++
>> target-info-qom.c | 5 +++++
>> 2 files changed, 20 insertions(+)
>>
>> diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-
>> info-qom.h
>> index 91be415ed33..83eb537333b 100644
>> --- a/include/qemu/target-info-qom.h
>> +++ b/include/qemu/target-info-qom.h
>> @@ -14,6 +14,21 @@
>> #define TYPE_TARGET_INFO "target-info"
>> +#define TYPE_TARGET_SPECIFIC "target-specific"
>> +
>> +typedef struct TargetSpecific TargetSpecific;
>> +
>> +typedef struct TargetSpecificClass {
>> + InterfaceClass parent_class;
>> +
>> + bool (*is_available)(void);
>
> Hopefully we won't have to call this with heterogeneous machines.
> Otherwise we might have to add another helper:
>
> bool (*is_available_ti)(const TargetInfo *ti);
>
It should not be needed, since meson build system filter files for which
CONFIG_X or target is not enabled, so they are excluded from the binary.
The case we deal with here is having two targets with two different
CONFIG_* sets, which makes additional types present at runtime for one
of those target.
>> +} TargetSpecificClass;
>> +
>> +#define TARGET_SPECIFIC(obj) \
>> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
>> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
>> + TYPE_TARGET_SPECIFIC)
>> +
>> typedef struct TargetInfoQom {
>> Object parent_obj;
>> } TargetInfoQom;
> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-07-24 0:09 ` [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface Pierrick Bouvier
2026-07-24 6:21 ` Philippe Mathieu-Daudé
@ 2026-08-05 14:05 ` Daniel P. Berrangé
2026-08-05 16:16 ` Pierrick Bouvier
1 sibling, 1 reply; 56+ messages in thread
From: Daniel P. Berrangé @ 2026-08-05 14:05 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
> In the next commits, We'll replace the logic to filter QOM types per
> target from a static one (based on INTERFACES) to a runtime one, based
> on is_available() function, that can be overriden per class.
>
> Introduce the new interface we'll use for that.
>
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
> include/qemu/target-info-qom.h | 15 +++++++++++++++
> target-info-qom.c | 5 +++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
> index 91be415ed33..83eb537333b 100644
> --- a/include/qemu/target-info-qom.h
> +++ b/include/qemu/target-info-qom.h
> @@ -14,6 +14,21 @@
>
> #define TYPE_TARGET_INFO "target-info"
>
> +#define TYPE_TARGET_SPECIFIC "target-specific"
> +
> +typedef struct TargetSpecific TargetSpecific;
> +
> +typedef struct TargetSpecificClass {
> + InterfaceClass parent_class;
> +
> + bool (*is_available)(void);
> +} TargetSpecificClass;
> +
> +#define TARGET_SPECIFIC(obj) \
> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
> + TYPE_TARGET_SPECIFIC)
Looking through the series,I don't really see the point
in this interface. Why is this not possible to do by
adding 'is_available' to MachineClass. It would make
the rest of the series simpler and especially avoid the
need to introduced yet more series of macros for defining
machine classes.
With regards,
Daniel
--
|: https://berrange.com ~~ https://hachyderm.io/@berrange :|
|: https://libvirt.org ~~ https://entangle-photo.org :|
|: https://pixelfed.art/berrange ~~ https://fstop138.berrange.com :|
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-05 14:05 ` Daniel P. Berrangé
@ 2026-08-05 16:16 ` Pierrick Bouvier
2026-08-05 16:53 ` Daniel P. Berrangé
0 siblings, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-08-05 16:16 UTC (permalink / raw)
To: Daniel P. Berrangé
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
> On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
>> In the next commits, We'll replace the logic to filter QOM types per
>> target from a static one (based on INTERFACES) to a runtime one, based
>> on is_available() function, that can be overriden per class.
>>
>> Introduce the new interface we'll use for that.
>>
>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>> ---
>> include/qemu/target-info-qom.h | 15 +++++++++++++++
>> target-info-qom.c | 5 +++++
>> 2 files changed, 20 insertions(+)
>>
>> diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
>> index 91be415ed33..83eb537333b 100644
>> --- a/include/qemu/target-info-qom.h
>> +++ b/include/qemu/target-info-qom.h
>> @@ -14,6 +14,21 @@
>>
>> #define TYPE_TARGET_INFO "target-info"
>>
>> +#define TYPE_TARGET_SPECIFIC "target-specific"
>> +
>> +typedef struct TargetSpecific TargetSpecific;
>> +
>> +typedef struct TargetSpecificClass {
>> + InterfaceClass parent_class;
>> +
>> + bool (*is_available)(void);
>> +} TargetSpecificClass;
>> +
>> +#define TARGET_SPECIFIC(obj) \
>> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
>> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
>> + TYPE_TARGET_SPECIFIC)
>
> Looking through the series,I don't really see the point
> in this interface. Why is this not possible to do by
> adding 'is_available' to MachineClass. It would make
> the rest of the series simpler and especially avoid the
> need to introduced yet more series of macros for defining
> machine classes.
>
We'll need the exact same interface for cpus, and devices also. IMHO, it
makes sense to have this in an external interface, instead of forcing it
to be present in all cpus/devices/machines. I also considered adding it
directly in Object class directly (would be the simplest), but I felt it
would be hard to motivate it.
What do you think?
> With regards,
> Daniel
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-05 16:16 ` Pierrick Bouvier
@ 2026-08-05 16:53 ` Daniel P. Berrangé
2026-08-05 19:10 ` Pierrick Bouvier
0 siblings, 1 reply; 56+ messages in thread
From: Daniel P. Berrangé @ 2026-08-05 16:53 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On Wed, Aug 05, 2026 at 09:16:20AM -0700, Pierrick Bouvier wrote:
> On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
> > On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
> >> In the next commits, We'll replace the logic to filter QOM types per
> >> target from a static one (based on INTERFACES) to a runtime one, based
> >> on is_available() function, that can be overriden per class.
> >>
> >> Introduce the new interface we'll use for that.
> >>
> >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> >> ---
> >> include/qemu/target-info-qom.h | 15 +++++++++++++++
> >> target-info-qom.c | 5 +++++
> >> 2 files changed, 20 insertions(+)
> >>
> >> diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
> >> index 91be415ed33..83eb537333b 100644
> >> --- a/include/qemu/target-info-qom.h
> >> +++ b/include/qemu/target-info-qom.h
> >> @@ -14,6 +14,21 @@
> >>
> >> #define TYPE_TARGET_INFO "target-info"
> >>
> >> +#define TYPE_TARGET_SPECIFIC "target-specific"
> >> +
> >> +typedef struct TargetSpecific TargetSpecific;
> >> +
> >> +typedef struct TargetSpecificClass {
> >> + InterfaceClass parent_class;
> >> +
> >> + bool (*is_available)(void);
> >> +} TargetSpecificClass;
> >> +
> >> +#define TARGET_SPECIFIC(obj) \
> >> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
> >> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
> >> + TYPE_TARGET_SPECIFIC)
> >
> > Looking through the series,I don't really see the point
> > in this interface. Why is this not possible to do by
> > adding 'is_available' to MachineClass. It would make
> > the rest of the series simpler and especially avoid the
> > need to introduced yet more series of macros for defining
> > machine classes.
> >
>
> We'll need the exact same interface for cpus, and devices also. IMHO, it
> makes sense to have this in an external interface, instead of forcing it
> to be present in all cpus/devices/machines. I also considered adding it
> directly in Object class directly (would be the simplest), but I felt it
> would be hard to motivate it.
I don't see a need for the common interface across cpus/devices/etc as
as code that's filtering only cares about the specific types. It also
definitely doesn't beloong in Object class, but the Object class could
be changed to make it simpler.
The object_class_get_list() method could get a 'bool filter(ObjectClass *cl)'
callback which could be invoked on each class to filter it.
That said I find it pretty undesirable as an approach that we're
registering classes that can't then be used in a given situation.
This has a ripple effect where every bit of code that iterates over
classes needs changing to add filtering after the fact. It is also
not great for scalability, as it means every QEMU process will have
the union of all classes for all targets registered, most of which
have to be discarded / ignored at runtime.
IMHO we should never register the classes to begin with.
The trick is dealing with dependencies/ordering during early startup.
eg taking one random example:
static void zynq_machine_register_types(void)
{
type_register_static(&zynq_machine_type);
}
IMHO we ought to be able to say in that:
static void zynq_machine_register_types(void)
{
if (target_arm()) {
type_register_static(&zynq_machine_type);
}
}
The problem is target_arm() depends on having parsed the '-target'
argument. The type register methods are called from qemu_init_subsystems(),
which is called before we have done CLI parsing. This looks fixable
though. We already have two iterations over argv in qemu_init().
We can move qemu_init_subsystems after the first iteration, and
process -target in the first iteration.
With regards,
Daniel
--
|: https://berrange.com ~~ https://hachyderm.io/@berrange :|
|: https://libvirt.org ~~ https://entangle-photo.org :|
|: https://pixelfed.art/berrange ~~ https://fstop138.berrange.com :|
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-05 16:53 ` Daniel P. Berrangé
@ 2026-08-05 19:10 ` Pierrick Bouvier
2026-08-06 10:21 ` Daniel P. Berrangé
0 siblings, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-08-05 19:10 UTC (permalink / raw)
To: Daniel P. Berrangé
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On 8/5/2026 9:53 AM, Daniel P. Berrangé wrote:
> On Wed, Aug 05, 2026 at 09:16:20AM -0700, Pierrick Bouvier wrote:
>> On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
>>> On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
>>>> In the next commits, We'll replace the logic to filter QOM types per
>>>> target from a static one (based on INTERFACES) to a runtime one, based
>>>> on is_available() function, that can be overriden per class.
>>>>
>>>> Introduce the new interface we'll use for that.
>>>>
>>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>>>> ---
>>>> include/qemu/target-info-qom.h | 15 +++++++++++++++
>>>> target-info-qom.c | 5 +++++
>>>> 2 files changed, 20 insertions(+)
>>>>
>>>> diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
>>>> index 91be415ed33..83eb537333b 100644
>>>> --- a/include/qemu/target-info-qom.h
>>>> +++ b/include/qemu/target-info-qom.h
>>>> @@ -14,6 +14,21 @@
>>>>
>>>> #define TYPE_TARGET_INFO "target-info"
>>>>
>>>> +#define TYPE_TARGET_SPECIFIC "target-specific"
>>>> +
>>>> +typedef struct TargetSpecific TargetSpecific;
>>>> +
>>>> +typedef struct TargetSpecificClass {
>>>> + InterfaceClass parent_class;
>>>> +
>>>> + bool (*is_available)(void);
>>>> +} TargetSpecificClass;
>>>> +
>>>> +#define TARGET_SPECIFIC(obj) \
>>>> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
>>>> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
>>>> + TYPE_TARGET_SPECIFIC)
>>>
>>> Looking through the series,I don't really see the point
>>> in this interface. Why is this not possible to do by
>>> adding 'is_available' to MachineClass. It would make
>>> the rest of the series simpler and especially avoid the
>>> need to introduced yet more series of macros for defining
>>> machine classes.
>>>
>>
>> We'll need the exact same interface for cpus, and devices also. IMHO, it
>> makes sense to have this in an external interface, instead of forcing it
>> to be present in all cpus/devices/machines. I also considered adding it
>> directly in Object class directly (would be the simplest), but I felt it
>> would be hard to motivate it.
>
> I don't see a need for the common interface across cpus/devices/etc as
> as code that's filtering only cares about the specific types. It also
> definitely doesn't beloong in Object class, but the Object class could
> be changed to make it simpler.
>
We agree on this.
> The object_class_get_list() method could get a 'bool filter(ObjectClass *cl)'
> callback which could be invoked on each class to filter it.
>
> That said I find it pretty undesirable as an approach that we're
> registering classes that can't then be used in a given situation.
> This has a ripple effect where every bit of code that iterates over
> classes needs changing to add filtering after the fact. It is also
> not great for scalability, as it means every QEMU process will have
> the union of all classes for all targets registered, most of which
> have to be discarded / ignored at runtime.
>
This is inherent to the nature of having a single binary.
We need to cover those two requirements:
1. having a filter mechanism (per target)
2. have all the classes accessible for the heterogeneous machines that
will be coming in the future
1. could be covered by what you describe, however, it breaks 2. For
this, you need to be able to register all types by design.
For listing cpus, machines and devices, we provide the filtering
functions associated. The surface of what we need to change is very
limited. There are less than 10 call sites with TYPE_{CPU, MACHINE, DEVICE}.
>
> IMHO we should never register the classes to begin with.
>
> The trick is dealing with dependencies/ordering during early startup.
>
> eg taking one random example:
>
> static void zynq_machine_register_types(void)
> {
> type_register_static(&zynq_machine_type);
> }
>
> IMHO we ought to be able to say in that:
>
> static void zynq_machine_register_types(void)
> {
> if (target_arm()) {
> type_register_static(&zynq_machine_type);
> }
> }
>
> The problem is target_arm() depends on having parsed the '-target'
> argument. The type register methods are called from qemu_init_subsystems(),
> which is called before we have done CLI parsing. This looks fixable
> though. We already have two iterations over argv in qemu_init().
>
> We can move qemu_init_subsystems after the first iteration, and
> process -target in the first iteration.
>
I already have all this implemented in the way you describe. However, as
explained above, we need to support 2, which brought the current design.
It would be bad to implement something and have to change it all again
in 6 months when we'll experiment with an heterogeneous machine.
We also made the promise (and we'll hold it) that single-binary will not
add yet another config.
So the last thing I would like to see is:
if (target_arm() || single_binary_...()) {
type_register_static(&my_heterogeneous_machine_type);
}
Unfortunately, if we stick to "register only types we can use", it
becomes the only way to solve it.
>
> With regards,
> Daniel
Regards,
Pierrick
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-05 19:10 ` Pierrick Bouvier
@ 2026-08-06 10:21 ` Daniel P. Berrangé
2026-08-06 14:52 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 56+ messages in thread
From: Daniel P. Berrangé @ 2026-08-06 10:21 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On Wed, Aug 05, 2026 at 12:10:27PM -0700, Pierrick Bouvier wrote:
> On 8/5/2026 9:53 AM, Daniel P. Berrangé wrote:
> > On Wed, Aug 05, 2026 at 09:16:20AM -0700, Pierrick Bouvier wrote:
> >> On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
> >>> On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
> >>>> In the next commits, We'll replace the logic to filter QOM types per
> >>>> target from a static one (based on INTERFACES) to a runtime one, based
> >>>> on is_available() function, that can be overriden per class.
> >>>>
> >>>> Introduce the new interface we'll use for that.
> >>>>
> >>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> >>>> ---
> >>>> include/qemu/target-info-qom.h | 15 +++++++++++++++
> >>>> target-info-qom.c | 5 +++++
> >>>> 2 files changed, 20 insertions(+)
> >>>>
> >>>> diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
> >>>> index 91be415ed33..83eb537333b 100644
> >>>> --- a/include/qemu/target-info-qom.h
> >>>> +++ b/include/qemu/target-info-qom.h
> >>>> @@ -14,6 +14,21 @@
> >>>>
> >>>> #define TYPE_TARGET_INFO "target-info"
> >>>>
> >>>> +#define TYPE_TARGET_SPECIFIC "target-specific"
> >>>> +
> >>>> +typedef struct TargetSpecific TargetSpecific;
> >>>> +
> >>>> +typedef struct TargetSpecificClass {
> >>>> + InterfaceClass parent_class;
> >>>> +
> >>>> + bool (*is_available)(void);
> >>>> +} TargetSpecificClass;
> >>>> +
> >>>> +#define TARGET_SPECIFIC(obj) \
> >>>> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
> >>>> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
> >>>> + TYPE_TARGET_SPECIFIC)
> >>>
> >>> Looking through the series,I don't really see the point
> >>> in this interface. Why is this not possible to do by
> >>> adding 'is_available' to MachineClass. It would make
> >>> the rest of the series simpler and especially avoid the
> >>> need to introduced yet more series of macros for defining
> >>> machine classes.
> >>>
> >>
> >> We'll need the exact same interface for cpus, and devices also. IMHO, it
> >> makes sense to have this in an external interface, instead of forcing it
> >> to be present in all cpus/devices/machines. I also considered adding it
> >> directly in Object class directly (would be the simplest), but I felt it
> >> would be hard to motivate it.
> >
> > I don't see a need for the common interface across cpus/devices/etc as
> > as code that's filtering only cares about the specific types. It also
> > definitely doesn't beloong in Object class, but the Object class could
> > be changed to make it simpler.
> >
>
> We agree on this.
>
> > The object_class_get_list() method could get a 'bool filter(ObjectClass *cl)'
> > callback which could be invoked on each class to filter it.
> >
> > That said I find it pretty undesirable as an approach that we're
> > registering classes that can't then be used in a given situation.
> > This has a ripple effect where every bit of code that iterates over
> > classes needs changing to add filtering after the fact. It is also
> > not great for scalability, as it means every QEMU process will have
> > the union of all classes for all targets registered, most of which
> > have to be discarded / ignored at runtime.
> >
>
> This is inherent to the nature of having a single binary.
> We need to cover those two requirements:
> 1. having a filter mechanism (per target)
> 2. have all the classes accessible for the heterogeneous machines that
> will be coming in the future
>
> 1. could be covered by what you describe, however, it breaks 2. For
> this, you need to be able to register all types by design.
Even the heterogeneous machines aren't going to need all the
classes from all 30+ targets that QEMU supports.
IIUC, the current approach relies on '--target <blah>' to select
which target we need. Would the heterogeneous machines not just
change that to allow "--target <this> --target <that>". It still
looks like we should be able to significantly limit what we
register for heterogeneous machines.
With regards,
Daniel
--
|: https://berrange.com ~~ https://hachyderm.io/@berrange :|
|: https://libvirt.org ~~ https://entangle-photo.org :|
|: https://pixelfed.art/berrange ~~ https://fstop138.berrange.com :|
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-06 10:21 ` Daniel P. Berrangé
@ 2026-08-06 14:52 ` Philippe Mathieu-Daudé
2026-08-06 16:38 ` Pierrick Bouvier
2026-08-06 16:52 ` Daniel P. Berrangé
0 siblings, 2 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-06 14:52 UTC (permalink / raw)
To: Daniel P. Berrangé, Pierrick Bouvier
Cc: qemu-devel, Nicholas Piggin, Daniel Henrique Barboza,
Bernhard Beschow, Anton Johansson, Alistair Francis,
Peter Maydell, Alistair Francis
On 6/8/26 12:21, Daniel P. Berrangé wrote:
> On Wed, Aug 05, 2026 at 12:10:27PM -0700, Pierrick Bouvier wrote:
>> On 8/5/2026 9:53 AM, Daniel P. Berrangé wrote:
>>> On Wed, Aug 05, 2026 at 09:16:20AM -0700, Pierrick Bouvier wrote:
>>>> On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
>>>>> On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
>>>>>> In the next commits, We'll replace the logic to filter QOM types per
>>>>>> target from a static one (based on INTERFACES) to a runtime one, based
>>>>>> on is_available() function, that can be overriden per class.
>>>>>>
>>>>>> Introduce the new interface we'll use for that.
>>>>>>
>>>>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>>>>>> ---
>>>>>> include/qemu/target-info-qom.h | 15 +++++++++++++++
>>>>>> target-info-qom.c | 5 +++++
>>>>>> 2 files changed, 20 insertions(+)
>>>>>>
>>>>>> diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
>>>>>> index 91be415ed33..83eb537333b 100644
>>>>>> --- a/include/qemu/target-info-qom.h
>>>>>> +++ b/include/qemu/target-info-qom.h
>>>>>> @@ -14,6 +14,21 @@
>>>>>>
>>>>>> #define TYPE_TARGET_INFO "target-info"
>>>>>>
>>>>>> +#define TYPE_TARGET_SPECIFIC "target-specific"
>>>>>> +
>>>>>> +typedef struct TargetSpecific TargetSpecific;
>>>>>> +
>>>>>> +typedef struct TargetSpecificClass {
>>>>>> + InterfaceClass parent_class;
>>>>>> +
>>>>>> + bool (*is_available)(void);
>>>>>> +} TargetSpecificClass;
>>>>>> +
>>>>>> +#define TARGET_SPECIFIC(obj) \
>>>>>> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
>>>>>> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
>>>>>> + TYPE_TARGET_SPECIFIC)
>>>>>
>>>>> Looking through the series,I don't really see the point
>>>>> in this interface. Why is this not possible to do by
>>>>> adding 'is_available' to MachineClass. It would make
>>>>> the rest of the series simpler and especially avoid the
>>>>> need to introduced yet more series of macros for defining
>>>>> machine classes.
>>>>>
>>>>
>>>> We'll need the exact same interface for cpus, and devices also. IMHO, it
>>>> makes sense to have this in an external interface, instead of forcing it
>>>> to be present in all cpus/devices/machines. I also considered adding it
>>>> directly in Object class directly (would be the simplest), but I felt it
>>>> would be hard to motivate it.
>>>
>>> I don't see a need for the common interface across cpus/devices/etc as
>>> as code that's filtering only cares about the specific types. It also
>>> definitely doesn't beloong in Object class, but the Object class could
>>> be changed to make it simpler.
>>>
>>
>> We agree on this.
>>
>>> The object_class_get_list() method could get a 'bool filter(ObjectClass *cl)'
>>> callback which could be invoked on each class to filter it.
>>>
>>> That said I find it pretty undesirable as an approach that we're
>>> registering classes that can't then be used in a given situation.
>>> This has a ripple effect where every bit of code that iterates over
>>> classes needs changing to add filtering after the fact. It is also
>>> not great for scalability, as it means every QEMU process will have
>>> the union of all classes for all targets registered, most of which
>>> have to be discarded / ignored at runtime.
>>>
>>
>> This is inherent to the nature of having a single binary.
>> We need to cover those two requirements:
>> 1. having a filter mechanism (per target)
>> 2. have all the classes accessible for the heterogeneous machines that
>> will be coming in the future
>>
>> 1. could be covered by what you describe, however, it breaks 2. For
>> this, you need to be able to register all types by design.
>
>
> Even the heterogeneous machines aren't going to need all the
> classes from all 30+ targets that QEMU supports.
>
> IIUC, the current approach relies on '--target <blah>' to select
> which target we need. Would the heterogeneous machines not just
> change that to allow "--target <this> --target <that>". It still
> looks like we should be able to significantly limit what we
> register for heterogeneous machines.
Heterogeneous binary won't filter anything at runtime (if we want
to filter components we already have Kconfig at compile time).
"--target <foo>" is only needed to have a single binary backward
compatible. If you use it, you fall back to single architecture
(our current binaries). If you want anything heterogeneous, you
can not use it. This will be by design.
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-06 14:52 ` Philippe Mathieu-Daudé
@ 2026-08-06 16:38 ` Pierrick Bouvier
2026-08-06 18:15 ` Daniel P. Berrangé
2026-08-06 16:52 ` Daniel P. Berrangé
1 sibling, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-08-06 16:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Daniel P. Berrangé
Cc: qemu-devel, Nicholas Piggin, Daniel Henrique Barboza,
Bernhard Beschow, Anton Johansson, Alistair Francis,
Peter Maydell, Alistair Francis
On 8/6/2026 7:52 AM, Philippe Mathieu-Daudé wrote:
> On 6/8/26 12:21, Daniel P. Berrangé wrote:
>> On Wed, Aug 05, 2026 at 12:10:27PM -0700, Pierrick Bouvier wrote:
>>> On 8/5/2026 9:53 AM, Daniel P. Berrangé wrote:
>>>> On Wed, Aug 05, 2026 at 09:16:20AM -0700, Pierrick Bouvier wrote:
>>>>> On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
>>>>>> On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
>>>>>>> In the next commits, We'll replace the logic to filter QOM types per
>>>>>>> target from a static one (based on INTERFACES) to a runtime one,
>>>>>>> based
>>>>>>> on is_available() function, that can be overriden per class.
>>>>>>>
>>>>>>> Introduce the new interface we'll use for that.
>>>>>>>
>>>>>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>>>>>>> ---
>>>>>>> include/qemu/target-info-qom.h | 15 +++++++++++++++
>>>>>>> target-info-qom.c | 5 +++++
>>>>>>> 2 files changed, 20 insertions(+)
>>>>>>>
>>>>>>> diff --git a/include/qemu/target-info-qom.h b/include/qemu/
>>>>>>> target-info-qom.h
>>>>>>> index 91be415ed33..83eb537333b 100644
>>>>>>> --- a/include/qemu/target-info-qom.h
>>>>>>> +++ b/include/qemu/target-info-qom.h
>>>>>>> @@ -14,6 +14,21 @@
>>>>>>> #define TYPE_TARGET_INFO "target-info"
>>>>>>> +#define TYPE_TARGET_SPECIFIC "target-specific"
>>>>>>> +
>>>>>>> +typedef struct TargetSpecific TargetSpecific;
>>>>>>> +
>>>>>>> +typedef struct TargetSpecificClass {
>>>>>>> + InterfaceClass parent_class;
>>>>>>> +
>>>>>>> + bool (*is_available)(void);
>>>>>>> +} TargetSpecificClass;
>>>>>>> +
>>>>>>> +#define TARGET_SPECIFIC(obj) \
>>>>>>> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
>>>>>>> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
>>>>>>> + TYPE_TARGET_SPECIFIC)
>>>>>>
>>>>>> Looking through the series,I don't really see the point
>>>>>> in this interface. Why is this not possible to do by
>>>>>> adding 'is_available' to MachineClass. It would make
>>>>>> the rest of the series simpler and especially avoid the
>>>>>> need to introduced yet more series of macros for defining
>>>>>> machine classes.
>>>>>>
>>>>>
>>>>> We'll need the exact same interface for cpus, and devices also.
>>>>> IMHO, it
>>>>> makes sense to have this in an external interface, instead of
>>>>> forcing it
>>>>> to be present in all cpus/devices/machines. I also considered
>>>>> adding it
>>>>> directly in Object class directly (would be the simplest), but I
>>>>> felt it
>>>>> would be hard to motivate it.
>>>>
>>>> I don't see a need for the common interface across cpus/devices/etc as
>>>> as code that's filtering only cares about the specific types. It also
>>>> definitely doesn't beloong in Object class, but the Object class could
>>>> be changed to make it simpler.
>>>>
>>>
>>> We agree on this.
>>>
>>>> The object_class_get_list() method could get a 'bool
>>>> filter(ObjectClass *cl)'
>>>> callback which could be invoked on each class to filter it.
>>>>
>>>> That said I find it pretty undesirable as an approach that we're
>>>> registering classes that can't then be used in a given situation.
>>>> This has a ripple effect where every bit of code that iterates over
>>>> classes needs changing to add filtering after the fact. It is also
>>>> not great for scalability, as it means every QEMU process will have
>>>> the union of all classes for all targets registered, most of which
>>>> have to be discarded / ignored at runtime.
>>>>
>>>
>>> This is inherent to the nature of having a single binary.
>>> We need to cover those two requirements:
>>> 1. having a filter mechanism (per target)
>>> 2. have all the classes accessible for the heterogeneous machines that
>>> will be coming in the future
>>>
>>> 1. could be covered by what you describe, however, it breaks 2. For
>>> this, you need to be able to register all types by design.
>>
>>
>> Even the heterogeneous machines aren't going to need all the
>> classes from all 30+ targets that QEMU supports.
>>
>> IIUC, the current approach relies on '--target <blah>' to select
>> which target we need. Would the heterogeneous machines not just
>> change that to allow "--target <this> --target <that>". It still
>> looks like we should be able to significantly limit what we
>> register for heterogeneous machines.
>
> Heterogeneous binary won't filter anything at runtime (if we want
> to filter components we already have Kconfig at compile time).
>
> "--target <foo>" is only needed to have a single binary backward
> compatible. If you use it, you fall back to single architecture
> (our current binaries). If you want anything heterogeneous, you
> can not use it. This will be by design.
I've been thinking about it yesterday, and we could apply the paradigm
"register only classes that will be used". For heterogeneous machine,
either we'll provide a "none" target, which enables all target, or use
--target aarch64,riscv64, like Daniel proposed.
I will implement what Daniel asked for v2.
However, please be aware it will be probably be more invasive and
verbose, since we'll need to add macros and stuff to have conditional
type_register_static.
I would like to avoid doing a change you asked, and have no further
comment after that or something like "it was better before".
Do we agree on this Daniel?
Regards,
Pierrick
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-06 16:38 ` Pierrick Bouvier
@ 2026-08-06 18:15 ` Daniel P. Berrangé
2026-08-06 21:04 ` Pierrick Bouvier
2026-08-10 22:26 ` Pierrick Bouvier
0 siblings, 2 replies; 56+ messages in thread
From: Daniel P. Berrangé @ 2026-08-06 18:15 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: Philippe Mathieu-Daudé, qemu-devel, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On Thu, Aug 06, 2026 at 09:38:43AM -0700, Pierrick Bouvier wrote:
> On 8/6/2026 7:52 AM, Philippe Mathieu-Daudé wrote:
> > On 6/8/26 12:21, Daniel P. Berrangé wrote:
> >> On Wed, Aug 05, 2026 at 12:10:27PM -0700, Pierrick Bouvier wrote:
> >>> On 8/5/2026 9:53 AM, Daniel P. Berrangé wrote:
> >>>> On Wed, Aug 05, 2026 at 09:16:20AM -0700, Pierrick Bouvier wrote:
> >>>>> On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
> >>>>>> On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
> >>>>>>> In the next commits, We'll replace the logic to filter QOM types per
> >>>>>>> target from a static one (based on INTERFACES) to a runtime one,
> >>>>>>> based
> >>>>>>> on is_available() function, that can be overriden per class.
> >>>>>>>
> >>>>>>> Introduce the new interface we'll use for that.
> >>>>>>>
> >>>>>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> >>>>>>> ---
> >>>>>>> include/qemu/target-info-qom.h | 15 +++++++++++++++
> >>>>>>> target-info-qom.c | 5 +++++
> >>>>>>> 2 files changed, 20 insertions(+)
> >>>>>>>
> >>>>>>> diff --git a/include/qemu/target-info-qom.h b/include/qemu/
> >>>>>>> target-info-qom.h
> >>>>>>> index 91be415ed33..83eb537333b 100644
> >>>>>>> --- a/include/qemu/target-info-qom.h
> >>>>>>> +++ b/include/qemu/target-info-qom.h
> >>>>>>> @@ -14,6 +14,21 @@
> >>>>>>> #define TYPE_TARGET_INFO "target-info"
> >>>>>>> +#define TYPE_TARGET_SPECIFIC "target-specific"
> >>>>>>> +
> >>>>>>> +typedef struct TargetSpecific TargetSpecific;
> >>>>>>> +
> >>>>>>> +typedef struct TargetSpecificClass {
> >>>>>>> + InterfaceClass parent_class;
> >>>>>>> +
> >>>>>>> + bool (*is_available)(void);
> >>>>>>> +} TargetSpecificClass;
> >>>>>>> +
> >>>>>>> +#define TARGET_SPECIFIC(obj) \
> >>>>>>> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
> >>>>>>> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
> >>>>>>> + TYPE_TARGET_SPECIFIC)
> >>>>>>
> >>>>>> Looking through the series,I don't really see the point
> >>>>>> in this interface. Why is this not possible to do by
> >>>>>> adding 'is_available' to MachineClass. It would make
> >>>>>> the rest of the series simpler and especially avoid the
> >>>>>> need to introduced yet more series of macros for defining
> >>>>>> machine classes.
> >>>>>>
> >>>>>
> >>>>> We'll need the exact same interface for cpus, and devices also.
> >>>>> IMHO, it
> >>>>> makes sense to have this in an external interface, instead of
> >>>>> forcing it
> >>>>> to be present in all cpus/devices/machines. I also considered
> >>>>> adding it
> >>>>> directly in Object class directly (would be the simplest), but I
> >>>>> felt it
> >>>>> would be hard to motivate it.
> >>>>
> >>>> I don't see a need for the common interface across cpus/devices/etc as
> >>>> as code that's filtering only cares about the specific types. It also
> >>>> definitely doesn't beloong in Object class, but the Object class could
> >>>> be changed to make it simpler.
> >>>>
> >>>
> >>> We agree on this.
> >>>
> >>>> The object_class_get_list() method could get a 'bool
> >>>> filter(ObjectClass *cl)'
> >>>> callback which could be invoked on each class to filter it.
> >>>>
> >>>> That said I find it pretty undesirable as an approach that we're
> >>>> registering classes that can't then be used in a given situation.
> >>>> This has a ripple effect where every bit of code that iterates over
> >>>> classes needs changing to add filtering after the fact. It is also
> >>>> not great for scalability, as it means every QEMU process will have
> >>>> the union of all classes for all targets registered, most of which
> >>>> have to be discarded / ignored at runtime.
> >>>>
> >>>
> >>> This is inherent to the nature of having a single binary.
> >>> We need to cover those two requirements:
> >>> 1. having a filter mechanism (per target)
> >>> 2. have all the classes accessible for the heterogeneous machines that
> >>> will be coming in the future
> >>>
> >>> 1. could be covered by what you describe, however, it breaks 2. For
> >>> this, you need to be able to register all types by design.
> >>
> >>
> >> Even the heterogeneous machines aren't going to need all the
> >> classes from all 30+ targets that QEMU supports.
> >>
> >> IIUC, the current approach relies on '--target <blah>' to select
> >> which target we need. Would the heterogeneous machines not just
> >> change that to allow "--target <this> --target <that>". It still
> >> looks like we should be able to significantly limit what we
> >> register for heterogeneous machines.
> >
> > Heterogeneous binary won't filter anything at runtime (if we want
> > to filter components we already have Kconfig at compile time).
> >
> > "--target <foo>" is only needed to have a single binary backward
> > compatible. If you use it, you fall back to single architecture
> > (our current binaries). If you want anything heterogeneous, you
> > can not use it. This will be by design.
>
> I've been thinking about it yesterday, and we could apply the paradigm
> "register only classes that will be used". For heterogeneous machine,
> either we'll provide a "none" target, which enables all target, or use
> --target aarch64,riscv64, like Daniel proposed.
>
> I will implement what Daniel asked for v2.
> However, please be aware it will be probably be more invasive and
> verbose, since we'll need to add macros and stuff to have conditional
> type_register_static.
>
> I would like to avoid doing a change you asked, and have no further
> comment after that or something like "it was better before".
> Do we agree on this Daniel?
That is an unreasonable request - I can't approve of a patch series
that doesn't exist yet.
I can only say that I don't think the current series is a desirable
approach and make suggestions of what I think is (hopefully) a
better way.
Something else that I didn't consider previously is possible interaction
with modules. Much of our use of modules is to make backends loadable,
but we've got a few loadable devices too. It seems likely that with the
single binary model we'll have greater motivation to make more device &
machine code into loadable modules, as people have repeatedly pushed us
to have a lower mandatory footprint for QEMU.
The loadable modules relies on some metadata defined in the source
code alongside the type info. For example
static const TypeInfo emulated_card_info = {
.name = TYPE_EMULATED_CCID,
.parent = TYPE_CCID_CARD,
.instance_size = sizeof(EmulatedState),
.class_init = emulated_class_initfn,
};
module_obj(TYPE_EMULATED_CCID);
module_kconfig(USB);
In particular it feels like the module_kconfig() and module_arch()
metadata have overlap with what you're trying todo in this series.
So I wonder if we could generalize the module metadata so that it
serves a broader set of use cases. Instead of having to manually
write conditional logic in XXX_register_type() methods, perhaps we
can do the right thing automatically in type_register() using the
metadata we collect from the code ?
With regards,
Daniel
--
|: https://berrange.com ~~ https://hachyderm.io/@berrange :|
|: https://libvirt.org ~~ https://entangle-photo.org :|
|: https://pixelfed.art/berrange ~~ https://fstop138.berrange.com :|
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-06 18:15 ` Daniel P. Berrangé
@ 2026-08-06 21:04 ` Pierrick Bouvier
2026-08-10 22:26 ` Pierrick Bouvier
1 sibling, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-08-06 21:04 UTC (permalink / raw)
To: Daniel P. Berrangé
Cc: Philippe Mathieu-Daudé, qemu-devel, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On 8/6/2026 11:15 AM, Daniel P. Berrangé wrote:
> On Thu, Aug 06, 2026 at 09:38:43AM -0700, Pierrick Bouvier wrote:
>> On 8/6/2026 7:52 AM, Philippe Mathieu-Daudé wrote:
>>> On 6/8/26 12:21, Daniel P. Berrangé wrote:
>>>> On Wed, Aug 05, 2026 at 12:10:27PM -0700, Pierrick Bouvier wrote:
>>>>> On 8/5/2026 9:53 AM, Daniel P. Berrangé wrote:
>>>>>> On Wed, Aug 05, 2026 at 09:16:20AM -0700, Pierrick Bouvier wrote:
>>>>>>> On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
>>>>>>>> On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
>>>>>>>>> In the next commits, We'll replace the logic to filter QOM types per
>>>>>>>>> target from a static one (based on INTERFACES) to a runtime one,
>>>>>>>>> based
>>>>>>>>> on is_available() function, that can be overriden per class.
>>>>>>>>>
>>>>>>>>> Introduce the new interface we'll use for that.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>>>>>>>>> ---
>>>>>>>>> include/qemu/target-info-qom.h | 15 +++++++++++++++
>>>>>>>>> target-info-qom.c | 5 +++++
>>>>>>>>> 2 files changed, 20 insertions(+)
>>>>>>>>>
>>>>>>>>> diff --git a/include/qemu/target-info-qom.h b/include/qemu/
>>>>>>>>> target-info-qom.h
>>>>>>>>> index 91be415ed33..83eb537333b 100644
>>>>>>>>> --- a/include/qemu/target-info-qom.h
>>>>>>>>> +++ b/include/qemu/target-info-qom.h
>>>>>>>>> @@ -14,6 +14,21 @@
>>>>>>>>> #define TYPE_TARGET_INFO "target-info"
>>>>>>>>> +#define TYPE_TARGET_SPECIFIC "target-specific"
>>>>>>>>> +
>>>>>>>>> +typedef struct TargetSpecific TargetSpecific;
>>>>>>>>> +
>>>>>>>>> +typedef struct TargetSpecificClass {
>>>>>>>>> + InterfaceClass parent_class;
>>>>>>>>> +
>>>>>>>>> + bool (*is_available)(void);
>>>>>>>>> +} TargetSpecificClass;
>>>>>>>>> +
>>>>>>>>> +#define TARGET_SPECIFIC(obj) \
>>>>>>>>> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
>>>>>>>>> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
>>>>>>>>> + TYPE_TARGET_SPECIFIC)
>>>>>>>>
>>>>>>>> Looking through the series,I don't really see the point
>>>>>>>> in this interface. Why is this not possible to do by
>>>>>>>> adding 'is_available' to MachineClass. It would make
>>>>>>>> the rest of the series simpler and especially avoid the
>>>>>>>> need to introduced yet more series of macros for defining
>>>>>>>> machine classes.
>>>>>>>>
>>>>>>>
>>>>>>> We'll need the exact same interface for cpus, and devices also.
>>>>>>> IMHO, it
>>>>>>> makes sense to have this in an external interface, instead of
>>>>>>> forcing it
>>>>>>> to be present in all cpus/devices/machines. I also considered
>>>>>>> adding it
>>>>>>> directly in Object class directly (would be the simplest), but I
>>>>>>> felt it
>>>>>>> would be hard to motivate it.
>>>>>>
>>>>>> I don't see a need for the common interface across cpus/devices/etc as
>>>>>> as code that's filtering only cares about the specific types. It also
>>>>>> definitely doesn't beloong in Object class, but the Object class could
>>>>>> be changed to make it simpler.
>>>>>>
>>>>>
>>>>> We agree on this.
>>>>>
>>>>>> The object_class_get_list() method could get a 'bool
>>>>>> filter(ObjectClass *cl)'
>>>>>> callback which could be invoked on each class to filter it.
>>>>>>
>>>>>> That said I find it pretty undesirable as an approach that we're
>>>>>> registering classes that can't then be used in a given situation.
>>>>>> This has a ripple effect where every bit of code that iterates over
>>>>>> classes needs changing to add filtering after the fact. It is also
>>>>>> not great for scalability, as it means every QEMU process will have
>>>>>> the union of all classes for all targets registered, most of which
>>>>>> have to be discarded / ignored at runtime.
>>>>>>
>>>>>
>>>>> This is inherent to the nature of having a single binary.
>>>>> We need to cover those two requirements:
>>>>> 1. having a filter mechanism (per target)
>>>>> 2. have all the classes accessible for the heterogeneous machines that
>>>>> will be coming in the future
>>>>>
>>>>> 1. could be covered by what you describe, however, it breaks 2. For
>>>>> this, you need to be able to register all types by design.
>>>>
>>>>
>>>> Even the heterogeneous machines aren't going to need all the
>>>> classes from all 30+ targets that QEMU supports.
>>>>
>>>> IIUC, the current approach relies on '--target <blah>' to select
>>>> which target we need. Would the heterogeneous machines not just
>>>> change that to allow "--target <this> --target <that>". It still
>>>> looks like we should be able to significantly limit what we
>>>> register for heterogeneous machines.
>>>
>>> Heterogeneous binary won't filter anything at runtime (if we want
>>> to filter components we already have Kconfig at compile time).
>>>
>>> "--target <foo>" is only needed to have a single binary backward
>>> compatible. If you use it, you fall back to single architecture
>>> (our current binaries). If you want anything heterogeneous, you
>>> can not use it. This will be by design.
>>
>> I've been thinking about it yesterday, and we could apply the paradigm
>> "register only classes that will be used". For heterogeneous machine,
>> either we'll provide a "none" target, which enables all target, or use
>> --target aarch64,riscv64, like Daniel proposed.
>>
>> I will implement what Daniel asked for v2.
>> However, please be aware it will be probably be more invasive and
>> verbose, since we'll need to add macros and stuff to have conditional
>> type_register_static.
>>
>> I would like to avoid doing a change you asked, and have no further
>> comment after that or something like "it was better before".
>> Do we agree on this Daniel?
>
> That is an unreasonable request - I can't approve of a patch series
> that doesn't exist yet.
>
> I can only say that I don't think the current series is a desirable
> approach and make suggestions of what I think is (hopefully) a
> better way.
>
That's always welcome, but there is a difference between a suggestion
and insisting on something. Suggestions can be ignored.
>
> Something else that I didn't consider previously is possible interaction
> with modules. Much of our use of modules is to make backends loadable,
> but we've got a few loadable devices too. It seems likely that with the
> single binary model we'll have greater motivation to make more device &
> machine code into loadable modules, as people have repeatedly pushed us
> to have a lower mandatory footprint for QEMU.
>
> The loadable modules relies on some metadata defined in the source
> code alongside the type info. For example
>
> static const TypeInfo emulated_card_info = {
> .name = TYPE_EMULATED_CCID,
> .parent = TYPE_CCID_CARD,
> .instance_size = sizeof(EmulatedState),
> .class_init = emulated_class_initfn,
> };
> module_obj(TYPE_EMULATED_CCID);
> module_kconfig(USB);
>
> In particular it feels like the module_kconfig() and module_arch()
> metadata have overlap with what you're trying todo in this series.
>
> So I wonder if we could generalize the module metadata so that it
> serves a broader set of use cases. Instead of having to manually
> write conditional logic in XXX_register_type() methods, perhaps we
> can do the right thing automatically in type_register() using the
> metadata we collect from the code ?
>
We came from a specific need "We need to filter machines, cpus and
devices per target" to "Let's make all the types filterable in a generic
way that unify modules and the rest we have". This is some serious and
dangerous over engineering.
Feel free to have fun and send us the series implementing that.
> With regards,
> Daniel
Regards
Pierrick
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-06 18:15 ` Daniel P. Berrangé
2026-08-06 21:04 ` Pierrick Bouvier
@ 2026-08-10 22:26 ` Pierrick Bouvier
1 sibling, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-08-10 22:26 UTC (permalink / raw)
To: Daniel P. Berrangé
Cc: Philippe Mathieu-Daudé, qemu-devel, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On 8/6/2026 11:15 AM, Daniel P. Berrangé wrote:
> On Thu, Aug 06, 2026 at 09:38:43AM -0700, Pierrick Bouvier wrote:
>> On 8/6/2026 7:52 AM, Philippe Mathieu-Daudé wrote:
>>> On 6/8/26 12:21, Daniel P. Berrangé wrote:
>>>> On Wed, Aug 05, 2026 at 12:10:27PM -0700, Pierrick Bouvier wrote:
>>>>> On 8/5/2026 9:53 AM, Daniel P. Berrangé wrote:
>>>>>> On Wed, Aug 05, 2026 at 09:16:20AM -0700, Pierrick Bouvier wrote:
>>>>>>> On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
>>>>>>>> On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
>>>>>>>>> In the next commits, We'll replace the logic to filter QOM types per
>>>>>>>>> target from a static one (based on INTERFACES) to a runtime one,
>>>>>>>>> based
>>>>>>>>> on is_available() function, that can be overriden per class.
>>>>>>>>>
>>>>>>>>> Introduce the new interface we'll use for that.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>>>>>>>>> ---
>>>>>>>>> include/qemu/target-info-qom.h | 15 +++++++++++++++
>>>>>>>>> target-info-qom.c | 5 +++++
>>>>>>>>> 2 files changed, 20 insertions(+)
>>>>>>>>>
>>>>>>>>> diff --git a/include/qemu/target-info-qom.h b/include/qemu/
>>>>>>>>> target-info-qom.h
>>>>>>>>> index 91be415ed33..83eb537333b 100644
>>>>>>>>> --- a/include/qemu/target-info-qom.h
>>>>>>>>> +++ b/include/qemu/target-info-qom.h
>>>>>>>>> @@ -14,6 +14,21 @@
>>>>>>>>> #define TYPE_TARGET_INFO "target-info"
>>>>>>>>> +#define TYPE_TARGET_SPECIFIC "target-specific"
>>>>>>>>> +
>>>>>>>>> +typedef struct TargetSpecific TargetSpecific;
>>>>>>>>> +
>>>>>>>>> +typedef struct TargetSpecificClass {
>>>>>>>>> + InterfaceClass parent_class;
>>>>>>>>> +
>>>>>>>>> + bool (*is_available)(void);
>>>>>>>>> +} TargetSpecificClass;
>>>>>>>>> +
>>>>>>>>> +#define TARGET_SPECIFIC(obj) \
>>>>>>>>> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
>>>>>>>>> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
>>>>>>>>> + TYPE_TARGET_SPECIFIC)
>>>>>>>>
>>>>>>>> Looking through the series,I don't really see the point
>>>>>>>> in this interface. Why is this not possible to do by
>>>>>>>> adding 'is_available' to MachineClass. It would make
>>>>>>>> the rest of the series simpler and especially avoid the
>>>>>>>> need to introduced yet more series of macros for defining
>>>>>>>> machine classes.
>>>>>>>>
>>>>>>>
>>>>>>> We'll need the exact same interface for cpus, and devices also.
>>>>>>> IMHO, it
>>>>>>> makes sense to have this in an external interface, instead of
>>>>>>> forcing it
>>>>>>> to be present in all cpus/devices/machines. I also considered
>>>>>>> adding it
>>>>>>> directly in Object class directly (would be the simplest), but I
>>>>>>> felt it
>>>>>>> would be hard to motivate it.
>>>>>>
>>>>>> I don't see a need for the common interface across cpus/devices/etc as
>>>>>> as code that's filtering only cares about the specific types. It also
>>>>>> definitely doesn't beloong in Object class, but the Object class could
>>>>>> be changed to make it simpler.
>>>>>>
>>>>>
>>>>> We agree on this.
>>>>>
>>>>>> The object_class_get_list() method could get a 'bool
>>>>>> filter(ObjectClass *cl)'
>>>>>> callback which could be invoked on each class to filter it.
>>>>>>
>>>>>> That said I find it pretty undesirable as an approach that we're
>>>>>> registering classes that can't then be used in a given situation.
>>>>>> This has a ripple effect where every bit of code that iterates over
>>>>>> classes needs changing to add filtering after the fact. It is also
>>>>>> not great for scalability, as it means every QEMU process will have
>>>>>> the union of all classes for all targets registered, most of which
>>>>>> have to be discarded / ignored at runtime.
>>>>>>
>>>>>
>>>>> This is inherent to the nature of having a single binary.
>>>>> We need to cover those two requirements:
>>>>> 1. having a filter mechanism (per target)
>>>>> 2. have all the classes accessible for the heterogeneous machines that
>>>>> will be coming in the future
>>>>>
>>>>> 1. could be covered by what you describe, however, it breaks 2. For
>>>>> this, you need to be able to register all types by design.
>>>>
>>>>
>>>> Even the heterogeneous machines aren't going to need all the
>>>> classes from all 30+ targets that QEMU supports.
>>>>
>>>> IIUC, the current approach relies on '--target <blah>' to select
>>>> which target we need. Would the heterogeneous machines not just
>>>> change that to allow "--target <this> --target <that>". It still
>>>> looks like we should be able to significantly limit what we
>>>> register for heterogeneous machines.
>>>
>>> Heterogeneous binary won't filter anything at runtime (if we want
>>> to filter components we already have Kconfig at compile time).
>>>
>>> "--target <foo>" is only needed to have a single binary backward
>>> compatible. If you use it, you fall back to single architecture
>>> (our current binaries). If you want anything heterogeneous, you
>>> can not use it. This will be by design.
>>
>> I've been thinking about it yesterday, and we could apply the paradigm
>> "register only classes that will be used". For heterogeneous machine,
>> either we'll provide a "none" target, which enables all target, or use
>> --target aarch64,riscv64, like Daniel proposed.
>>
>> I will implement what Daniel asked for v2.
>> However, please be aware it will be probably be more invasive and
>> verbose, since we'll need to add macros and stuff to have conditional
>> type_register_static.
>>
>> I would like to avoid doing a change you asked, and have no further
>> comment after that or something like "it was better before".
>> Do we agree on this Daniel?
>
> That is an unreasonable request - I can't approve of a patch series
> that doesn't exist yet.
>
> I can only say that I don't think the current series is a desirable
> approach and make suggestions of what I think is (hopefully) a
> better way.
>
>
> Something else that I didn't consider previously is possible interaction
> with modules. Much of our use of modules is to make backends loadable,
> but we've got a few loadable devices too. It seems likely that with the
> single binary model we'll have greater motivation to make more device &
> machine code into loadable modules, as people have repeatedly pushed us
> to have a lower mandatory footprint for QEMU.
>
> The loadable modules relies on some metadata defined in the source
> code alongside the type info. For example
>
> static const TypeInfo emulated_card_info = {
> .name = TYPE_EMULATED_CCID,
> .parent = TYPE_CCID_CARD,
> .instance_size = sizeof(EmulatedState),
> .class_init = emulated_class_initfn,
> };
> module_obj(TYPE_EMULATED_CCID);
> module_kconfig(USB);
>
> In particular it feels like the module_kconfig() and module_arch()
> metadata have overlap with what you're trying todo in this series.
>
> So I wonder if we could generalize the module metadata so that it
> serves a broader set of use cases. Instead of having to manually
> write conditional logic in XXX_register_type() methods, perhaps we
> can do the right thing automatically in type_register() using the
> metadata we collect from the code ?
>
I have been experimenting today with static filtering of types, as you
suggested, and came up with two possibilities. Before implementing this
for all types, I would like to get some feedback on which way is the
best for you.
1. Add a new callback is_available to TypeInfo, similar to existing
interface.
Pros: local information is present in type definition, making obvious
why a type is available or not. Very easy to implement
since only type_register_static has to be modified to check it.
Cons: Add a new field to each existing type. Not the end of the world
in terms of memory consumption, but worth mentioning.
2. Add conditional around each type_register_static, or add an
alternative type_register_static_cond function.
Pros: I don't see any
Cons: Decouples type information from type definition, makes it harder
to follow why a type is available or not. Much more verbose since
we need to modify all type_register_static buried in macros.
Based on this, I'm much more in favor or 1. The fact availability
information is in the same location than type definition is the biggest
advantage for me.
On example given above, this would give something like this:
static const TypeInfo emulated_card_info = {
.name = TYPE_EMULATED_CCID,
.parent = TYPE_CCID_CARD,
.instance_size = sizeof(EmulatedState),
.class_init = emulated_class_initfn,
.is_available = target_config_X,
};
Would that work for you?
Do you have a 3rd way to offer to solve the problem we have?
> With regards,
> Daniel
Thanks,
Pierrick
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-06 14:52 ` Philippe Mathieu-Daudé
2026-08-06 16:38 ` Pierrick Bouvier
@ 2026-08-06 16:52 ` Daniel P. Berrangé
2026-08-06 20:21 ` Pierrick Bouvier
1 sibling, 1 reply; 56+ messages in thread
From: Daniel P. Berrangé @ 2026-08-06 16:52 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Pierrick Bouvier, qemu-devel, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On Thu, Aug 06, 2026 at 04:52:20PM +0200, Philippe Mathieu-Daudé wrote:
> On 6/8/26 12:21, Daniel P. Berrangé wrote:
> > On Wed, Aug 05, 2026 at 12:10:27PM -0700, Pierrick Bouvier wrote:
> > > On 8/5/2026 9:53 AM, Daniel P. Berrangé wrote:
> > > > On Wed, Aug 05, 2026 at 09:16:20AM -0700, Pierrick Bouvier wrote:
> > > > > On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
> > > > > > On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
> > > > > > > In the next commits, We'll replace the logic to filter QOM types per
> > > > > > > target from a static one (based on INTERFACES) to a runtime one, based
> > > > > > > on is_available() function, that can be overriden per class.
> > > > > > >
> > > > > > > Introduce the new interface we'll use for that.
> > > > > > >
> > > > > > > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> > > > > > > ---
> > > > > > > include/qemu/target-info-qom.h | 15 +++++++++++++++
> > > > > > > target-info-qom.c | 5 +++++
> > > > > > > 2 files changed, 20 insertions(+)
> > > > > > >
> > > > > > > diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
> > > > > > > index 91be415ed33..83eb537333b 100644
> > > > > > > --- a/include/qemu/target-info-qom.h
> > > > > > > +++ b/include/qemu/target-info-qom.h
> > > > > > > @@ -14,6 +14,21 @@
> > > > > > > #define TYPE_TARGET_INFO "target-info"
> > > > > > > +#define TYPE_TARGET_SPECIFIC "target-specific"
> > > > > > > +
> > > > > > > +typedef struct TargetSpecific TargetSpecific;
> > > > > > > +
> > > > > > > +typedef struct TargetSpecificClass {
> > > > > > > + InterfaceClass parent_class;
> > > > > > > +
> > > > > > > + bool (*is_available)(void);
> > > > > > > +} TargetSpecificClass;
> > > > > > > +
> > > > > > > +#define TARGET_SPECIFIC(obj) \
> > > > > > > + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
> > > > > > > +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
> > > > > > > + TYPE_TARGET_SPECIFIC)
> > > > > >
> > > > > > Looking through the series,I don't really see the point
> > > > > > in this interface. Why is this not possible to do by
> > > > > > adding 'is_available' to MachineClass. It would make
> > > > > > the rest of the series simpler and especially avoid the
> > > > > > need to introduced yet more series of macros for defining
> > > > > > machine classes.
> > > > > >
> > > > >
> > > > > We'll need the exact same interface for cpus, and devices also. IMHO, it
> > > > > makes sense to have this in an external interface, instead of forcing it
> > > > > to be present in all cpus/devices/machines. I also considered adding it
> > > > > directly in Object class directly (would be the simplest), but I felt it
> > > > > would be hard to motivate it.
> > > >
> > > > I don't see a need for the common interface across cpus/devices/etc as
> > > > as code that's filtering only cares about the specific types. It also
> > > > definitely doesn't beloong in Object class, but the Object class could
> > > > be changed to make it simpler.
> > > >
> > >
> > > We agree on this.
> > >
> > > > The object_class_get_list() method could get a 'bool filter(ObjectClass *cl)'
> > > > callback which could be invoked on each class to filter it.
> > > >
> > > > That said I find it pretty undesirable as an approach that we're
> > > > registering classes that can't then be used in a given situation.
> > > > This has a ripple effect where every bit of code that iterates over
> > > > classes needs changing to add filtering after the fact. It is also
> > > > not great for scalability, as it means every QEMU process will have
> > > > the union of all classes for all targets registered, most of which
> > > > have to be discarded / ignored at runtime.
> > > >
> > >
> > > This is inherent to the nature of having a single binary.
> > > We need to cover those two requirements:
> > > 1. having a filter mechanism (per target)
> > > 2. have all the classes accessible for the heterogeneous machines that
> > > will be coming in the future
> > >
> > > 1. could be covered by what you describe, however, it breaks 2. For
> > > this, you need to be able to register all types by design.
> >
> >
> > Even the heterogeneous machines aren't going to need all the
> > classes from all 30+ targets that QEMU supports.
> >
> > IIUC, the current approach relies on '--target <blah>' to select
> > which target we need. Would the heterogeneous machines not just
> > change that to allow "--target <this> --target <that>". It still
> > looks like we should be able to significantly limit what we
> > register for heterogeneous machines.
>
> Heterogeneous binary won't filter anything at runtime (if we want
> to filter components we already have Kconfig at compile time).
>
> "--target <foo>" is only needed to have a single binary backward
> compatible. If you use it, you fall back to single architecture
> (our current binaries). If you want anything heterogeneous, you
> can not use it. This will be by design.
I wonder if we've got a disconnect in our respective understanding
of what we're aiming to create ? You seem to be suggesting heterogeneous
binary and single binary are not ultimately the same thing, but I saw
heterogeneous machines as a new feature of the single binary.
IOW my interpretation is that the end point that we eventually reach
is that we have "qemu-system" as a binary, and that can be used
to host **anything** we want to deliver, whether that's a traditional
machine like x86 'i440fx', or aarch64 'virt', or some new fancy
machine which has multiple heterogeneous CPU types.
All the existing qemu-system-$TARGET machines would go away,
becoming hardlinks to "qemu-system" where argv0 name represents
an implicit $TARGET.
What machines you could see when doing "qemu-system --machine help"
would depend on which/how many "--target NAME" args you enable.
qemu-system -target x86_64 -machine help
-> x86_64 machines
(equiv of qemu-system-x86_64)
qemu-system -target aarch64
-> aarch64 machines
(equiv of qemu-system-aarch64)
qemu-system -target x86_64,aarch64
-> aarch64 machines
-> x86_64 machines
-> aarch64+x86_64 machines
(equiv of qemu-system-aarch64 plus qemu-system-x86_64 plus new heterogenous machines)
qemu-system -target x86_64,aarch64,riscv64
-> aarch64 machines
-> x86_64 machines
-> riscv64 machines
-> aarch64+x86_64 machines
-> aarch64+riscv64 machines
-> riscv64+x86_64 machines
-> aarch64+riscv64+x86_64 machines
(equiv of qemu-system-aarch64 plus qemu-system-x86_64
plus qemu-system-riscv64 plus new heterogenous machines
for any combo of x86_64, aarch64 and riscv64)
With regards,
Daniel
--
|: https://berrange.com ~~ https://hachyderm.io/@berrange :|
|: https://libvirt.org ~~ https://entangle-photo.org :|
|: https://pixelfed.art/berrange ~~ https://fstop138.berrange.com :|
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-06 16:52 ` Daniel P. Berrangé
@ 2026-08-06 20:21 ` Pierrick Bouvier
2026-08-10 15:56 ` Daniel P. Berrangé
0 siblings, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-08-06 20:21 UTC (permalink / raw)
To: Daniel P. Berrangé, Philippe Mathieu-Daudé
Cc: qemu-devel, Nicholas Piggin, Daniel Henrique Barboza,
Bernhard Beschow, Anton Johansson, Alistair Francis,
Peter Maydell, Alistair Francis
On 8/6/2026 9:52 AM, Daniel P. Berrangé wrote:
> On Thu, Aug 06, 2026 at 04:52:20PM +0200, Philippe Mathieu-Daudé wrote:
>> On 6/8/26 12:21, Daniel P. Berrangé wrote:
>>> On Wed, Aug 05, 2026 at 12:10:27PM -0700, Pierrick Bouvier wrote:
>>>> On 8/5/2026 9:53 AM, Daniel P. Berrangé wrote:
>>>>> On Wed, Aug 05, 2026 at 09:16:20AM -0700, Pierrick Bouvier wrote:
>>>>>> On 8/5/2026 7:05 AM, Daniel P. Berrangé wrote:
>>>>>>> On Fri, Jul 24, 2026 at 12:09:21AM +0000, Pierrick Bouvier wrote:
>>>>>>>> In the next commits, We'll replace the logic to filter QOM types per
>>>>>>>> target from a static one (based on INTERFACES) to a runtime one, based
>>>>>>>> on is_available() function, that can be overriden per class.
>>>>>>>>
>>>>>>>> Introduce the new interface we'll use for that.
>>>>>>>>
>>>>>>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>>>>>>>> ---
>>>>>>>> include/qemu/target-info-qom.h | 15 +++++++++++++++
>>>>>>>> target-info-qom.c | 5 +++++
>>>>>>>> 2 files changed, 20 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
>>>>>>>> index 91be415ed33..83eb537333b 100644
>>>>>>>> --- a/include/qemu/target-info-qom.h
>>>>>>>> +++ b/include/qemu/target-info-qom.h
>>>>>>>> @@ -14,6 +14,21 @@
>>>>>>>> #define TYPE_TARGET_INFO "target-info"
>>>>>>>> +#define TYPE_TARGET_SPECIFIC "target-specific"
>>>>>>>> +
>>>>>>>> +typedef struct TargetSpecific TargetSpecific;
>>>>>>>> +
>>>>>>>> +typedef struct TargetSpecificClass {
>>>>>>>> + InterfaceClass parent_class;
>>>>>>>> +
>>>>>>>> + bool (*is_available)(void);
>>>>>>>> +} TargetSpecificClass;
>>>>>>>> +
>>>>>>>> +#define TARGET_SPECIFIC(obj) \
>>>>>>>> + INTERFACE_CHECK(TargetSpecific, (obj), TYPE_TARGET_SPECIFIC)
>>>>>>>> +DECLARE_CLASS_CHECKERS(TargetSpecificClass, TARGET_SPECIFIC,
>>>>>>>> + TYPE_TARGET_SPECIFIC)
>>>>>>>
>>>>>>> Looking through the series,I don't really see the point
>>>>>>> in this interface. Why is this not possible to do by
>>>>>>> adding 'is_available' to MachineClass. It would make
>>>>>>> the rest of the series simpler and especially avoid the
>>>>>>> need to introduced yet more series of macros for defining
>>>>>>> machine classes.
>>>>>>>
>>>>>>
>>>>>> We'll need the exact same interface for cpus, and devices also. IMHO, it
>>>>>> makes sense to have this in an external interface, instead of forcing it
>>>>>> to be present in all cpus/devices/machines. I also considered adding it
>>>>>> directly in Object class directly (would be the simplest), but I felt it
>>>>>> would be hard to motivate it.
>>>>>
>>>>> I don't see a need for the common interface across cpus/devices/etc as
>>>>> as code that's filtering only cares about the specific types. It also
>>>>> definitely doesn't beloong in Object class, but the Object class could
>>>>> be changed to make it simpler.
>>>>>
>>>>
>>>> We agree on this.
>>>>
>>>>> The object_class_get_list() method could get a 'bool filter(ObjectClass *cl)'
>>>>> callback which could be invoked on each class to filter it.
>>>>>
>>>>> That said I find it pretty undesirable as an approach that we're
>>>>> registering classes that can't then be used in a given situation.
>>>>> This has a ripple effect where every bit of code that iterates over
>>>>> classes needs changing to add filtering after the fact. It is also
>>>>> not great for scalability, as it means every QEMU process will have
>>>>> the union of all classes for all targets registered, most of which
>>>>> have to be discarded / ignored at runtime.
>>>>>
>>>>
>>>> This is inherent to the nature of having a single binary.
>>>> We need to cover those two requirements:
>>>> 1. having a filter mechanism (per target)
>>>> 2. have all the classes accessible for the heterogeneous machines that
>>>> will be coming in the future
>>>>
>>>> 1. could be covered by what you describe, however, it breaks 2. For
>>>> this, you need to be able to register all types by design.
>>>
>>>
>>> Even the heterogeneous machines aren't going to need all the
>>> classes from all 30+ targets that QEMU supports.
>>>
>>> IIUC, the current approach relies on '--target <blah>' to select
>>> which target we need. Would the heterogeneous machines not just
>>> change that to allow "--target <this> --target <that>". It still
>>> looks like we should be able to significantly limit what we
>>> register for heterogeneous machines.
>>
>> Heterogeneous binary won't filter anything at runtime (if we want
>> to filter components we already have Kconfig at compile time).
>>
>> "--target <foo>" is only needed to have a single binary backward
>> compatible. If you use it, you fall back to single architecture
>> (our current binaries). If you want anything heterogeneous, you
>> can not use it. This will be by design.
>
> I wonder if we've got a disconnect in our respective understanding
> of what we're aiming to create ? You seem to be suggesting heterogeneous
> binary and single binary are not ultimately the same thing, but I saw
> heterogeneous machines as a new feature of the single binary.
>
Single-binary is a step toward heterogeneous emulation, but not (yet) a
new feature of it.
We have been talking about how we would like to approach heterogeneous
emulation problem, but didn't share that
publicly. We submitted a talk for next KVM Forum to present our ideas.
In short: before being able to have any heterogeneous machine, we need
to solve all global state issues we identified so far: sysbus, global
memory address space, cpu indexing, etc. This work will be conducted
with a downstream "fake" machine that we have no plan to upstream.
Our long term goal is to be able to run two kernels on two different
socs with different architectures, different address spaces and set of
devices, unconnected to each other. This would prove we have effectively
achieved heterogeneous emulation.
*Once*, and only *once* all the problems above will be solved, we'll
consider what the command line should be for that. We have some ideas,
but I don't want to present them here and now, because there are many
questions left.
> IOW my interpretation is that the end point that we eventually reach
> is that we have "qemu-system" as a binary, and that can be used
> to host **anything** we want to deliver, whether that's a traditional
> machine like x86 'i440fx', or aarch64 'virt', or some new fancy
> machine which has multiple heterogeneous CPU types.
>
Current scope of single-binary qemu-system is only to do a single
target, without any functional change compared to existing binaries.
> All the existing qemu-system-$TARGET machines would go away,
> becoming hardlinks to "qemu-system" where argv0 name represents
> an implicit $TARGET.
>
That's correct. It will take time though, and qemu-system + existing
binaries will cohabit for a while.
>
> What machines you could see when doing "qemu-system --machine help"
> would depend on which/how many "--target NAME" args you enable.
>
> qemu-system -target x86_64 -machine help
> -> x86_64 machines
> (equiv of qemu-system-x86_64)
>
> qemu-system -target aarch64
> -> aarch64 machines
> (equiv of qemu-system-aarch64)
>
> qemu-system -target x86_64,aarch64
> -> aarch64 machines
> -> x86_64 machines
> -> aarch64+x86_64 machines
> (equiv of qemu-system-aarch64 plus qemu-system-x86_64 plus new heterogenous machines)
>
> qemu-system -target x86_64,aarch64,riscv64
> -> aarch64 machines
> -> x86_64 machines
> -> riscv64 machines
> -> aarch64+x86_64 machines
> -> aarch64+riscv64 machines
> -> riscv64+x86_64 machines
> -> aarch64+riscv64+x86_64 machines
> (equiv of qemu-system-aarch64 plus qemu-system-x86_64
> plus qemu-system-riscv64 plus new heterogenous machines
> for any combo of x86_64, aarch64 and riscv64)
>
This is where we have a gap in our understanding.
The goal is not to enable multiple targets, not in this way at least.
I give you a simple example about why it's a bad design:
What is the semantic of such a line?
$ qemu-system -target x86_64,aarch64,riscv64 -M virt -cpu max
We now created an ambiguous command line, is virt the virt riscv64 or
aarch64? How about cpu?
Someone with over engineering tendencies will come with the idea:
"Ok let's prefix machine and cpu with target".
$ qemu-system -target x86_64,aarch64,riscv64 -M aarch64:virt -cpu
aarch64:max
And then, someone will say:
$ qemu-system -target x86_64,aarch64,riscv64 -M aarch64:virt -cpu
riscv64:max
And then, we will all go to hell for creating such a thing.
The only sane solution is to restrict to a single -target, and have the
exact same behavior than current binaries. No change, no breakage.
For heterogeneous machines, we want to propose a very different
approach, that requires all QOM types to be registered. Once again, it's
not the time to present/solve that, but it's why we implemented this
runtime filtering instead of exposing only some types.
>
> With regards,
> Daniel
Finally, I would like to make one thing *crystal* clear.
It's totally ok for you (or anyone) to come on any series, review, and
criticize design, as long as a good suggestion is provided. That's the
force of our community.
However, dropping on a series, saying "NO", "do X", and stop following
it after that is not ok. It happened two months ago, when adding
target-info QOM
(https://patchew.org/QEMU/20260505224826.2698753-1-pierrick.bouvier@oss.qualcomm.com/),
where you suggested and insisted on the wrong design, despite arguments
against it. After, you've been "busy" and stopped answering.
Whether you're busy or not does not matter at all, if you engage in such
a change, you have to ensure you can be present in the next iterations.
It's not the first time you stop answering to a thread when you run out
of arguments or things don't go in your way, and this passive-aggressive
behavior have to stop.
You can be an architect for things, but you can't leave out in the
middle of the construction when it needs you, that's unprofessional. If
you don't have time, don't engage in the first place: pick your battles.
Given this, can you confirm you understood the consequences of asking to
modify current design to register only types needed, and you are ready
to review and accept it will be more verbose than current design? If
yes, I can happily spend my time on refactoring it.
Regards,
Pierrick
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-06 20:21 ` Pierrick Bouvier
@ 2026-08-10 15:56 ` Daniel P. Berrangé
2026-08-10 16:11 ` Pierrick Bouvier
0 siblings, 1 reply; 56+ messages in thread
From: Daniel P. Berrangé @ 2026-08-10 15:56 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: Philippe Mathieu-Daudé, qemu-devel, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On Thu, Aug 06, 2026 at 01:21:13PM -0700, Pierrick Bouvier wrote:
> On 8/6/2026 9:52 AM, Daniel P. Berrangé wrote:
> >
> > What machines you could see when doing "qemu-system --machine help"
> > would depend on which/how many "--target NAME" args you enable.
> >
> > qemu-system -target x86_64 -machine help
> > -> x86_64 machines
> > (equiv of qemu-system-x86_64)
> >
> > qemu-system -target aarch64
> > -> aarch64 machines
> > (equiv of qemu-system-aarch64)
> >
> > qemu-system -target x86_64,aarch64
> > -> aarch64 machines
> > -> x86_64 machines
> > -> aarch64+x86_64 machines
> > (equiv of qemu-system-aarch64 plus qemu-system-x86_64 plus new heterogenous machines)
> >
> > qemu-system -target x86_64,aarch64,riscv64
> > -> aarch64 machines
> > -> x86_64 machines
> > -> riscv64 machines
> > -> aarch64+x86_64 machines
> > -> aarch64+riscv64 machines
> > -> riscv64+x86_64 machines
> > -> aarch64+riscv64+x86_64 machines
> > (equiv of qemu-system-aarch64 plus qemu-system-x86_64
> > plus qemu-system-riscv64 plus new heterogenous machines
> > for any combo of x86_64, aarch64 and riscv64)
> >
>
> This is where we have a gap in our understanding.
> The goal is not to enable multiple targets, not in this way at least.
>
> I give you a simple example about why it's a bad design:
> What is the semantic of such a line?
> $ qemu-system -target x86_64,aarch64,riscv64 -M virt -cpu max
> We now created an ambiguous command line, is virt the virt riscv64 or
> aarch64? How about cpu?
The ambiguity needs fixing before we can have multiple different
targets in the same binary. I would expect you're going to hit a
failure before QEMU even tries to process that command line, as
QOM class names must be unique and you'll have two separate
classes called 'virt-machine' AFAICT.
> Someone with over engineering tendencies will come with the idea:
> "Ok let's prefix machine and cpu with target".
> $ qemu-system -target x86_64,aarch64,riscv64 -M aarch64:virt -cpu
> aarch64:max
>
> And then, someone will say:
> $ qemu-system -target x86_64,aarch64,riscv64 -M aarch64:virt -cpu
> riscv64:max
> And then, we will all go to hell for creating such a thing.
I wouldn't suggest we need to prefix an arch name for *everything*,
as most type names will not clash. "virt" and "max" are two
exceptions but most machine names and CPU names will be unique
across architectures.
IOW, just those clashing names need fixing, 'aarch64-virt'
and 'aarch64-max', but not the rest.
Saying this is "going to hell" is overly dramatic. It is just
an expected result of fixing a handful of cases where we got
away without having properly unique naming today.
> The only sane solution is to restrict to a single -target, and have the
> exact same behavior than current binaries. No change, no breakage.
I think we're going to need to have changes this area.
To deal with the transition we'll need to support aliases
like "virt" that resolve to either "aarch64_virt" or "riscv64_virt"
depending on target specific context, or raise an error if it is
ambiguous in a fully heterogenous context.
> For heterogeneous machines, we want to propose a very different
> approach, that requires all QOM types to be registered. Once again, it's
> not the time to present/solve that, but it's why we implemented this
> runtime filtering instead of exposing only some types.
AFAIK, QEMU won't be able to register all QOM types, as it will have
multiple different classes called 'virt-machine' and will (should)
trigger an assert until they're given unique names.
With regards,
Daniel
--
|: https://berrange.com ~~ https://hachyderm.io/@berrange :|
|: https://libvirt.org ~~ https://entangle-photo.org :|
|: https://pixelfed.art/berrange ~~ https://fstop138.berrange.com :|
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
2026-08-10 15:56 ` Daniel P. Berrangé
@ 2026-08-10 16:11 ` Pierrick Bouvier
0 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-08-10 16:11 UTC (permalink / raw)
To: Daniel P. Berrangé
Cc: Philippe Mathieu-Daudé, qemu-devel, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On 8/10/2026 8:56 AM, Daniel P. Berrangé wrote:
> On Thu, Aug 06, 2026 at 01:21:13PM -0700, Pierrick Bouvier wrote:
>> On 8/6/2026 9:52 AM, Daniel P. Berrangé wrote:
>>>
>>> What machines you could see when doing "qemu-system --machine help"
>>> would depend on which/how many "--target NAME" args you enable.
>>>
>>> qemu-system -target x86_64 -machine help
>>> -> x86_64 machines
>>> (equiv of qemu-system-x86_64)
>>>
>>> qemu-system -target aarch64
>>> -> aarch64 machines
>>> (equiv of qemu-system-aarch64)
>>>
>>> qemu-system -target x86_64,aarch64
>>> -> aarch64 machines
>>> -> x86_64 machines
>>> -> aarch64+x86_64 machines
>>> (equiv of qemu-system-aarch64 plus qemu-system-x86_64 plus new heterogenous machines)
>>>
>>> qemu-system -target x86_64,aarch64,riscv64
>>> -> aarch64 machines
>>> -> x86_64 machines
>>> -> riscv64 machines
>>> -> aarch64+x86_64 machines
>>> -> aarch64+riscv64 machines
>>> -> riscv64+x86_64 machines
>>> -> aarch64+riscv64+x86_64 machines
>>> (equiv of qemu-system-aarch64 plus qemu-system-x86_64
>>> plus qemu-system-riscv64 plus new heterogenous machines
>>> for any combo of x86_64, aarch64 and riscv64)
>>>
>>
>> This is where we have a gap in our understanding.
>> The goal is not to enable multiple targets, not in this way at least.
>>
>> I give you a simple example about why it's a bad design:
>> What is the semantic of such a line?
>> $ qemu-system -target x86_64,aarch64,riscv64 -M virt -cpu max
>> We now created an ambiguous command line, is virt the virt riscv64 or
>> aarch64? How about cpu?
>
> The ambiguity needs fixing before we can have multiple different
> targets in the same binary. I would expect you're going to hit a
> failure before QEMU even tries to process that command line, as
> QOM class names must be unique and you'll have two separate
> classes called 'virt-machine' AFAICT.
>
That's why it's interesting to fix this issue, as we add more targets.
We met this issue with max cpu between arm and aarch64. There is no
"generic solution" and we'll tackle issues one after another, like we
did so far.
>> Someone with over engineering tendencies will come with the idea:
>> "Ok let's prefix machine and cpu with target".
>> $ qemu-system -target x86_64,aarch64,riscv64 -M aarch64:virt -cpu
>> aarch64:max
>>
>> And then, someone will say:
>> $ qemu-system -target x86_64,aarch64,riscv64 -M aarch64:virt -cpu
>> riscv64:max
>> And then, we will all go to hell for creating such a thing.
>
> I wouldn't suggest we need to prefix an arch name for *everything*,
> as most type names will not clash. "virt" and "max" are two
> exceptions but most machine names and CPU names will be unique
> across architectures.
>
> IOW, just those clashing names need fixing, 'aarch64-virt'
> and 'aarch64-max', but not the rest.
>
So now, should it be the default name for existing binary, or just for
single-binary? This approach creates more and more problem.
> Saying this is "going to hell" is overly dramatic. It is just
> an expected result of fixing a handful of cases where we got
> away without having properly unique naming today.
>
Sorry for not being a native speaker. The meaning I wanted to express is
that we would commit a sin, and end up in hell because of that.
>> The only sane solution is to restrict to a single -target, and have the
>> exact same behavior than current binaries. No change, no breakage.
>
> I think we're going to need to have changes this area.
>
> To deal with the transition we'll need to support aliases
> like "virt" that resolve to either "aarch64_virt" or "riscv64_virt"
> depending on target specific context, or raise an error if it is
> ambiguous in a fully heterogenous context.
>
How about we wait to have a single-binary before solving issues to which
we're not exposed yet? We don't even have a prototype upstream, and
we're already trying to solve issues we'll have in 6 months. One lesson
of our work so far was that trying to fix things before they happen
just create more delay and problems.
>> For heterogeneous machines, we want to propose a very different
>> approach, that requires all QOM types to be registered. Once again, it's
>> not the time to present/solve that, but it's why we implemented this
>> runtime filtering instead of exposing only some types.
>
> AFAIK, QEMU won't be able to register all QOM types, as it will have
> multiple different classes called 'virt-machine' and will (should)
> trigger an assert until they're given unique names.
>
See the first paragraph in my answer above.
> With regards,
> Daniel
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 02/27] hw/arm: implement TYPE_TARGET_SPECIFIC
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 03/27] target-info: add target_riscv32 and target_base_riscv Pierrick Bouvier
` (26 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
For now, we still keep existing TYPE_TARGET_.*_MACHINE mechanic to not
break existing binaries. As a result, we add TYPE_TARGET_SPECIFIC to
list of interfaces *_machine_interfaces.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/arm/aspeed_ast1040_evb.c | 1 +
hw/arm/aspeed_ast10x0_evb.c | 2 ++
hw/arm/aspeed_ast2400_palmetto.c | 1 +
hw/arm/aspeed_ast2400_quanta-q71l.c | 1 +
hw/arm/aspeed_ast2400_supermicrox11.c | 1 +
hw/arm/aspeed_ast2500_evb.c | 1 +
hw/arm/aspeed_ast2500_g220a.c | 1 +
hw/arm/aspeed_ast2500_romulus.c | 1 +
hw/arm/aspeed_ast2500_supermicro-x11spi.c | 1 +
hw/arm/aspeed_ast2500_tiogapass.c | 1 +
hw/arm/aspeed_ast2500_witherspoon.c | 1 +
hw/arm/aspeed_ast2500_yosemitev2.c | 1 +
hw/arm/aspeed_ast2600_anacapa.c | 1 +
hw/arm/aspeed_ast2600_bletchley.c | 1 +
hw/arm/aspeed_ast2600_catalina.c | 1 +
hw/arm/aspeed_ast2600_evb.c | 1 +
hw/arm/aspeed_ast2600_fby35.c | 1 +
hw/arm/aspeed_ast2600_fuji.c | 1 +
hw/arm/aspeed_ast2600_gb200nvl.c | 1 +
hw/arm/aspeed_ast2600_rainier.c | 1 +
hw/arm/aspeed_ast27x0-fc.c | 1 +
hw/arm/aspeed_ast27x0_evb.c | 2 ++
hw/arm/b-l475e-iot01a.c | 1 +
hw/arm/bananapi_m2u.c | 1 +
hw/arm/collie.c | 1 +
hw/arm/cubieboard.c | 1 +
hw/arm/digic_boards.c | 1 +
hw/arm/exynos4_boards.c | 2 ++
hw/arm/imx25_pdk.c | 1 +
hw/arm/imx8mm-evk.c | 1 +
hw/arm/imx8mp-evk.c | 1 +
hw/arm/integratorcp.c | 1 +
hw/arm/kzm.c | 1 +
hw/arm/max78000fthr.c | 1 +
hw/arm/mcimx6ul-evk.c | 1 +
hw/arm/mcimx7d-sabre.c | 1 +
hw/arm/microbit.c | 1 +
hw/arm/mps2-tz.c | 4 ++++
hw/arm/mps2.c | 4 ++++
hw/arm/mps3r.c | 1 +
hw/arm/msf2-som.c | 1 +
hw/arm/musca.c | 2 ++
hw/arm/musicpal.c | 1 +
hw/arm/netduino2.c | 1 +
hw/arm/netduinoplus2.c | 1 +
hw/arm/npcm7xx_boards.c | 5 +++++
hw/arm/npcm8xx_boards.c | 1 +
hw/arm/olimex-stm32-h405.c | 1 +
hw/arm/omap_sx1.c | 2 ++
hw/arm/orangepi.c | 1 +
hw/arm/raspi.c | 5 +++++
hw/arm/raspi4b.c | 1 +
hw/arm/realview.c | 4 ++++
hw/arm/sabrelite.c | 1 +
hw/arm/sbsa-ref.c | 1 +
hw/arm/stellaris.c | 2 ++
hw/arm/stm32vldiscovery.c | 1 +
hw/arm/versatilepb.c | 2 ++
hw/arm/vexpress.c | 2 ++
hw/arm/virt.c | 1 +
hw/arm/xilinx_zynq.c | 1 +
hw/arm/xlnx-versal-virt.c | 2 ++
hw/arm/xlnx-zcu102.c | 1 +
include/hw/arm/machines-qom.h | 2 ++
target/arm/machine.c | 4 ++++
65 files changed, 95 insertions(+)
diff --git a/hw/arm/aspeed_ast1040_evb.c b/hw/arm/aspeed_ast1040_evb.c
index 2b93d4dfbc5..0b52612432e 100644
--- a/hw/arm/aspeed_ast1040_evb.c
+++ b/hw/arm/aspeed_ast1040_evb.c
@@ -61,6 +61,7 @@ static void ast1040_evb_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_ast1040_evb_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast10x0_evb.c b/hw/arm/aspeed_ast10x0_evb.c
index c19563d1f0a..ed858a35b52 100644
--- a/hw/arm/aspeed_ast10x0_evb.c
+++ b/hw/arm/aspeed_ast10x0_evb.c
@@ -79,6 +79,7 @@ static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
@@ -99,6 +100,7 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
static void aspeed_minibmc_machine_ast1060_evb_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2400_palmetto.c b/hw/arm/aspeed_ast2400_palmetto.c
index 776aa43a45d..b3dcb559b4e 100644
--- a/hw/arm/aspeed_ast2400_palmetto.c
+++ b/hw/arm/aspeed_ast2400_palmetto.c
@@ -54,6 +54,7 @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_palmetto_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2400_quanta-q71l.c b/hw/arm/aspeed_ast2400_quanta-q71l.c
index 42ad2a2303f..04d5445bae6 100644
--- a/hw/arm/aspeed_ast2400_quanta-q71l.c
+++ b/hw/arm/aspeed_ast2400_quanta-q71l.c
@@ -60,6 +60,7 @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2400_supermicrox11.c b/hw/arm/aspeed_ast2400_supermicrox11.c
index 88cdb01fc76..ab16ffa4e3a 100644
--- a/hw/arm/aspeed_ast2400_supermicrox11.c
+++ b/hw/arm/aspeed_ast2400_supermicrox11.c
@@ -54,6 +54,7 @@ static void supermicrox11_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2500_evb.c b/hw/arm/aspeed_ast2500_evb.c
index 8b5cb67be9b..76b1d8dc5cf 100644
--- a/hw/arm/aspeed_ast2500_evb.c
+++ b/hw/arm/aspeed_ast2500_evb.c
@@ -41,6 +41,7 @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2500_g220a.c b/hw/arm/aspeed_ast2500_g220a.c
index 3f979a78e57..e0ba88c47a5 100644
--- a/hw/arm/aspeed_ast2500_g220a.c
+++ b/hw/arm/aspeed_ast2500_g220a.c
@@ -65,6 +65,7 @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_g220a_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2500_romulus.c b/hw/arm/aspeed_ast2500_romulus.c
index 91b660e74bb..5031539f288 100644
--- a/hw/arm/aspeed_ast2500_romulus.c
+++ b/hw/arm/aspeed_ast2500_romulus.c
@@ -36,6 +36,7 @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_romulus_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2500_supermicro-x11spi.c b/hw/arm/aspeed_ast2500_supermicro-x11spi.c
index a2450aa9623..b2362d45d8f 100644
--- a/hw/arm/aspeed_ast2500_supermicro-x11spi.c
+++ b/hw/arm/aspeed_ast2500_supermicro-x11spi.c
@@ -50,6 +50,7 @@ static void supermicro_x11spi_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2500_tiogapass.c b/hw/arm/aspeed_ast2500_tiogapass.c
index 186dbc1da30..de0129a4991 100644
--- a/hw/arm/aspeed_ast2500_tiogapass.c
+++ b/hw/arm/aspeed_ast2500_tiogapass.c
@@ -63,6 +63,7 @@ static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_tiogapass_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2500_witherspoon.c b/hw/arm/aspeed_ast2500_witherspoon.c
index 28d437fec08..e77bbc6a697 100644
--- a/hw/arm/aspeed_ast2500_witherspoon.c
+++ b/hw/arm/aspeed_ast2500_witherspoon.c
@@ -86,6 +86,7 @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_witherspoon_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2500_yosemitev2.c b/hw/arm/aspeed_ast2500_yosemitev2.c
index eaa75bcccbb..3ceda60c0f2 100644
--- a/hw/arm/aspeed_ast2500_yosemitev2.c
+++ b/hw/arm/aspeed_ast2500_yosemitev2.c
@@ -64,6 +64,7 @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2600_anacapa.c b/hw/arm/aspeed_ast2600_anacapa.c
index a1c8111a934..5ef86e175f7 100644
--- a/hw/arm/aspeed_ast2600_anacapa.c
+++ b/hw/arm/aspeed_ast2600_anacapa.c
@@ -334,6 +334,7 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_anacapa_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2600_bletchley.c b/hw/arm/aspeed_ast2600_bletchley.c
index b7e84db1438..e3f3a383113 100644
--- a/hw/arm/aspeed_ast2600_bletchley.c
+++ b/hw/arm/aspeed_ast2600_bletchley.c
@@ -69,6 +69,7 @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_bletchley_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catalina.c
index 65495a524ea..269a2ac8332 100644
--- a/hw/arm/aspeed_ast2600_catalina.c
+++ b/hw/arm/aspeed_ast2600_catalina.c
@@ -637,6 +637,7 @@ static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_catalina_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2600_evb.c b/hw/arm/aspeed_ast2600_evb.c
index c43d2687c1c..4c0dc6b625f 100644
--- a/hw/arm/aspeed_ast2600_evb.c
+++ b/hw/arm/aspeed_ast2600_evb.c
@@ -34,6 +34,7 @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2600_fby35.c b/hw/arm/aspeed_ast2600_fby35.c
index f6244270704..bca31e5a0bf 100644
--- a/hw/arm/aspeed_ast2600_fby35.c
+++ b/hw/arm/aspeed_ast2600_fby35.c
@@ -153,6 +153,7 @@ static void fby35_reset(MachineState *state, ResetType type)
static void aspeed_machine_fby35_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2600_fuji.c b/hw/arm/aspeed_ast2600_fuji.c
index 37db252e276..2790bee6ca2 100644
--- a/hw/arm/aspeed_ast2600_fuji.c
+++ b/hw/arm/aspeed_ast2600_fuji.c
@@ -111,6 +111,7 @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2600_gb200nvl.c b/hw/arm/aspeed_ast2600_gb200nvl.c
index ad9a10110b8..5286d03428c 100644
--- a/hw/arm/aspeed_ast2600_gb200nvl.c
+++ b/hw/arm/aspeed_ast2600_gb200nvl.c
@@ -79,6 +79,7 @@ static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast2600_rainier.c b/hw/arm/aspeed_ast2600_rainier.c
index 8f0a412ddcf..189cc4d2560 100644
--- a/hw/arm/aspeed_ast2600_rainier.c
+++ b/hw/arm/aspeed_ast2600_rainier.c
@@ -169,6 +169,7 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 7d9fade68da..8915bfbc6fa 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -207,6 +207,7 @@ static void ast2700fc_init(MachineState *machine)
static void ast2700fc_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "ast2700 full core support";
diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c
index 0ff1bebeb0e..8a1b2b22fae 100644
--- a/hw/arm/aspeed_ast27x0_evb.c
+++ b/hw/arm/aspeed_ast27x0_evb.c
@@ -31,6 +31,7 @@ static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
@@ -52,6 +53,7 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
static void aspeed_machine_ast2700a2_evb_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index ee789c8df94..d31ad5d9e04 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -113,6 +113,7 @@ static void bl475e_init(MachineState *machine)
static void bl475e_machine_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
static const char *machine_valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"),
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index 9b468cd8ac8..4fb19a83657 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -128,6 +128,7 @@ static void bpim2u_init(MachineState *machine)
static void bpim2u_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a7"),
NULL
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 91f0a94b6ff..99482fb425f 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -72,6 +72,7 @@ static void collie_init(MachineState *machine)
static void collie_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)";
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index a643ae4e27d..234c1ea37fc 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -109,6 +109,7 @@ static void cubieboard_init(MachineState *machine)
static void cubieboard_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a8"),
NULL
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index ed12f542001..fbcabaa3362 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -139,6 +139,7 @@ static void canon_a1100_init(MachineState *machine)
static void canon_a1100_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
mc->desc = "Canon PowerShot A1100 IS (ARM946)";
mc->init = &canon_a1100_init;
mc->ignore_memory_transaction_failures = true;
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index 1b8c9b618f8..2caeb420246 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -157,6 +157,7 @@ static const char * const valid_cpu_types[] = {
static void nuri_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Samsung NURI board (Exynos4210)";
@@ -178,6 +179,7 @@ static const TypeInfo nuri_type = {
static void smdkc210_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Samsung SMDKC210 board (Exynos4210)";
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index 7ebd6c8eb9c..e60a7e672a4 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -144,6 +144,7 @@ static void imx25_pdk_init(MachineState *machine)
static void imx25_pdk_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
mc->desc = "ARM i.MX25 PDK board (ARM926)";
mc->init = imx25_pdk_init;
mc->ignore_memory_transaction_failures = true;
diff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c
index 6b7774d3e25..031f9348626 100644
--- a/hw/arm/imx8mm-evk.c
+++ b/hw/arm/imx8mm-evk.c
@@ -118,6 +118,7 @@ static const char *imx8mm_evk_get_default_cpu_type(const MachineState *ms)
static void imx8mm_evk_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_aarch64;
mc->desc = "NXP i.MX 8MM EVK Board";
mc->init = imx8mm_evk_init;
mc->max_cpus = FSL_IMX8MM_NUM_CPUS;
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c
index 16e9722d146..897f1b91d0a 100644
--- a/hw/arm/imx8mp-evk.c
+++ b/hw/arm/imx8mp-evk.c
@@ -144,6 +144,7 @@ static void imx8mp_evk_machine_init(Object *obj)
static void imx8mp_evk_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "NXP i.MX 8M Plus EVK Board";
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index c25bbf3c82a..cf95c3f57d4 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -686,6 +686,7 @@ static void integratorcp_init(MachineState *machine)
static void integratorcp_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
mc->init = integratorcp_init;
mc->ignore_memory_transaction_failures = true;
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index 168ecf35d09..b49841ca87a 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -134,6 +134,7 @@ static void kzm_init(MachineState *machine)
static void kzm_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
mc->desc = "ARM KZM Emulation Baseboard (ARM1136)";
mc->init = kzm_init;
mc->ignore_memory_transaction_failures = true;
diff --git a/hw/arm/max78000fthr.c b/hw/arm/max78000fthr.c
index 530ca9dd964..4453868e562 100644
--- a/hw/arm/max78000fthr.c
+++ b/hw/arm/max78000fthr.c
@@ -38,6 +38,7 @@ static void max78000_init(MachineState *machine)
static void max78000_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"),
NULL
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index 6e9d92b1f1d..299e797fd48 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -71,6 +71,7 @@ static void mcimx6ul_evk_init(MachineState *machine)
static void mcimx6ul_evk_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
mc->desc = "Freescale i.MX6UL Evaluation Kit (Cortex-A7)";
mc->init = mcimx6ul_evk_init;
mc->max_cpus = FSL_IMX6UL_NUM_CPUS;
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index a0ac647c3df..a94218ac1b1 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -71,6 +71,7 @@ static void mcimx7d_sabre_init(MachineState *machine)
static void mcimx7d_sabre_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
mc->desc = "Freescale i.MX7 DUAL SABRE (Cortex-A7)";
mc->init = mcimx7d_sabre_init;
mc->max_cpus = FSL_IMX7_NUM_CPUS;
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 9d5c4898469..50d561aa246 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -63,6 +63,7 @@ static void microbit_init(MachineState *machine)
static void microbit_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "BBC micro:bit (Cortex-M0)";
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index f101c1b7c3b..91e66f82b69 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -1307,6 +1307,7 @@ static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
static void mps2tz_an505_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
@@ -1341,6 +1342,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, const void *data)
static void mps2tz_an521_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
@@ -1375,6 +1377,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, const void *data)
static void mps3tz_an524_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
@@ -1414,6 +1417,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, const void *data)
static void mps3tz_an547_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index ac9366d8447..55fd22a85d2 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -481,6 +481,7 @@ static void mps2_class_init(ObjectClass *oc, const void *data)
static void mps2_an385_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
@@ -500,6 +501,7 @@ static void mps2_an385_class_init(ObjectClass *oc, const void *data)
static void mps2_an386_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
@@ -519,6 +521,7 @@ static void mps2_an386_class_init(ObjectClass *oc, const void *data)
static void mps2_an500_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
@@ -538,6 +541,7 @@ static void mps2_an500_class_init(ObjectClass *oc, const void *data)
static void mps2_an511_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index caad820d3bc..687f74f9ec0 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -593,6 +593,7 @@ static void mps3r_class_init(ObjectClass *oc, const void *data)
static void mps3r_an536_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 1ada1a13613..44c68bffac6 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -99,6 +99,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
static void emcraft_sf2_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m3"),
NULL
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index 75d82eebcac..e6736efa8dd 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -612,6 +612,7 @@ static void musca_class_init(ObjectClass *oc, const void *data)
static void musca_a_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc);
@@ -626,6 +627,7 @@ static void musca_a_class_init(ObjectClass *oc, const void *data)
static void musca_b1_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc);
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 69e83bdd973..d9aeb98b6f0 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -1347,6 +1347,7 @@ static void musicpal_init(MachineState *machine)
static void musicpal_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)";
mc->init = musicpal_init;
mc->ignore_memory_transaction_failures = true;
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index c32deaf43ba..a721da02ce0 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -55,6 +55,7 @@ static void netduino2_init(MachineState *machine)
static void netduino2_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m3"),
NULL
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index a90dcbe8c26..ee5f1679426 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -56,6 +56,7 @@ static void netduinoplus2_init(MachineState *machine)
static void netduinoplus2_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"),
NULL
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 57a8d3186e6..573180f873a 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -475,6 +475,7 @@ static void npcm7xx_machine_class_init(ObjectClass *oc, const void *data)
*/
static void npcm750_evb_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
MachineClass *mc = MACHINE_CLASS(oc);
@@ -488,6 +489,7 @@ static void npcm750_evb_machine_class_init(ObjectClass *oc, const void *data)
static void gsj_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
MachineClass *mc = MACHINE_CLASS(oc);
@@ -501,6 +503,7 @@ static void gsj_machine_class_init(ObjectClass *oc, const void *data)
static void gbs_bmc_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
MachineClass *mc = MACHINE_CLASS(oc);
@@ -514,6 +517,7 @@ static void gbs_bmc_machine_class_init(ObjectClass *oc, const void *data)
static void kudo_bmc_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
MachineClass *mc = MACHINE_CLASS(oc);
@@ -527,6 +531,7 @@ static void kudo_bmc_machine_class_init(ObjectClass *oc, const void *data)
static void mori_bmc_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
MachineClass *mc = MACHINE_CLASS(oc);
diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
index 042a928857c..c8335091a7e 100644
--- a/hw/arm/npcm8xx_boards.c
+++ b/hw/arm/npcm8xx_boards.c
@@ -227,6 +227,7 @@ static void npcm8xx_machine_class_init(ObjectClass *oc, const void *data)
static void npcm845_evb_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_CLASS(oc);
MachineClass *mc = MACHINE_CLASS(oc);
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index e801e4308ed..58a124d3c06 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -59,6 +59,7 @@ static void olimex_stm32_h405_init(MachineState *machine)
static void olimex_stm32_h405_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"),
NULL
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index bcb7105323f..59670d31af8 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -205,6 +205,7 @@ static void sx1_init_v2(MachineState *machine)
static void sx1_machine_v2_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Siemens SX1 (OMAP310) V2";
@@ -225,6 +226,7 @@ static const TypeInfo sx1_machine_v2_type = {
static void sx1_machine_v1_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Siemens SX1 (OMAP310) V1";
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index d84443bb7b3..53366a76334 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -106,6 +106,7 @@ static void orangepi_init(MachineState *machine)
static void orangepi_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a7"),
NULL
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 3f99e87428c..e0e597d55ef 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -339,6 +339,7 @@ static void raspi_machine_class_init(MachineClass *mc,
static void raspi0_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
@@ -349,6 +350,7 @@ static void raspi0_machine_class_init(ObjectClass *oc, const void *data)
static void raspi1ap_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
@@ -359,6 +361,7 @@ static void raspi1ap_machine_class_init(ObjectClass *oc, const void *data)
static void raspi2b_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
@@ -369,6 +372,7 @@ static void raspi2b_machine_class_init(ObjectClass *oc, const void *data)
static void raspi3ap_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
@@ -379,6 +383,7 @@ static void raspi3ap_machine_class_init(ObjectClass *oc, const void *data)
static void raspi3b_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index 06aeb8db014..c8a2463ec8d 100644
--- a/hw/arm/raspi4b.c
+++ b/hw/arm/raspi4b.c
@@ -108,6 +108,7 @@ static void raspi4b_machine_init(MachineState *machine)
static void raspi4b_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 2b9f3271d62..005f737b68c 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -415,6 +415,7 @@ static void realview_pbx_a9_init(MachineState *machine)
static void realview_eb_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)";
@@ -436,6 +437,7 @@ static const TypeInfo realview_eb_type = {
static void realview_eb_mpcore_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)";
@@ -458,6 +460,7 @@ static const TypeInfo realview_eb_mpcore_type = {
static void realview_pb_a8_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
@@ -478,6 +481,7 @@ static const TypeInfo realview_pb_a8_type = {
static void realview_pbx_a9_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9";
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index 84bbc2f9798..4ea4cda36ee 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -137,6 +137,7 @@ static void sabrelite_machine_instance_init(Object *obj)
static void sabrelite_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex-A9)";
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 484b90053e8..5608263a810 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -905,6 +905,7 @@ static void sbsa_ref_instance_finalize(Object *obj)
static void sbsa_ref_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a57"),
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 56ecc828f4f..4b7dc5c45a3 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1416,6 +1416,7 @@ static void lm3s6965evb_init(MachineState *machine)
*/
static void lm3s811evb_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
@@ -1437,6 +1438,7 @@ static const TypeInfo lm3s811evb_type = {
*/
static void lm3s6965evb_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 8f93c0036a3..53b4632c013 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -59,6 +59,7 @@ static void stm32vldiscovery_init(MachineState *machine)
static void stm32vldiscovery_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m3"),
NULL
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index c6991a52e65..3437e014cd4 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -414,6 +414,7 @@ static void vab_init(MachineState *machine)
static void versatilepb_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "ARM Versatile/PB (ARM926EJ-S)";
@@ -436,6 +437,7 @@ static const TypeInfo versatilepb_type = {
static void versatileab_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "ARM Versatile/AB (ARM926EJ-S)";
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index f26d8c6f8d1..13d76597893 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -797,6 +797,7 @@ static void vexpress_class_init(ObjectClass *oc, const void *data)
static void vexpress_a9_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a9"),
NULL
@@ -813,6 +814,7 @@ static void vexpress_a9_class_init(ObjectClass *oc, const void *data)
static void vexpress_a15_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a15"),
NULL
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 219597cabd0..f55366b4d07 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -119,6 +119,7 @@ static void arm_virt_compat_default_set(MachineClass *mc)
ObjectClass *oc, \
const void *data) \
{ \
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm; \
MachineClass *mc = MACHINE_CLASS(oc); \
arm_virt_compat_default_set(mc); \
MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 6c834390174..6861fe91774 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -455,6 +455,7 @@ static void zynq_init(MachineState *machine)
static void zynq_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_arm;
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a9"),
NULL
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 2b04513ba2e..c40b8376947 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -367,6 +367,7 @@ static void versal_virt_machine_class_init_common(ObjectClass *oc)
static void versal_virt_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
VersalVirtClass *vvc = XLNX_VERSAL_VIRT_BASE_MACHINE_CLASS(oc);
@@ -379,6 +380,7 @@ static void versal_virt_machine_class_init(ObjectClass *oc, const void *data)
static void versal2_virt_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
VersalVirtClass *vvc = XLNX_VERSAL_VIRT_BASE_MACHINE_CLASS(oc);
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 4e489702743..ff98827f83a 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -269,6 +269,7 @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
static void xlnx_zcu102_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_aarch64;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
index 3ed39384e59..37fb64bf479 100644
--- a/include/hw/arm/machines-qom.h
+++ b/include/hw/arm/machines-qom.h
@@ -10,6 +10,8 @@
#define HW_ARM_MACHINES_QOM_H
#include "hw/core/boards.h"
+#include "qemu/target-info.h"
+#include "qemu/target-info-qom.h"
#define TYPE_TARGET_ARM_MACHINE \
"target-info-arm-machine"
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 89127e5d83c..60501d17911 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -10,6 +10,7 @@
#include "cpu-features.h"
#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
+#include "qemu/target-info-qom.h"
#include "target/arm/gtimer.h"
#include "hw/arm/machines-qom.h"
@@ -1348,18 +1349,21 @@ const VMStateDescription vmstate_arm_cpu = {
};
const InterfaceInfo arm_machine_interfaces[] = {
+ { TYPE_TARGET_SPECIFIC },
{ TYPE_TARGET_ARM_MACHINE },
{ TYPE_TARGET_AARCH64_MACHINE },
{ }
};
const InterfaceInfo arm_aarch64_machine_interfaces[] = {
+ { TYPE_TARGET_SPECIFIC },
{ TYPE_TARGET_ARM_MACHINE },
{ TYPE_TARGET_AARCH64_MACHINE },
{ }
};
const InterfaceInfo aarch64_machine_interfaces[] = {
+ { TYPE_TARGET_SPECIFIC },
{ TYPE_TARGET_AARCH64_MACHINE },
{ }
};
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 03/27] target-info: add target_riscv32 and target_base_riscv
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 01/27] include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 02/27] hw/arm: implement TYPE_TARGET_SPECIFIC Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 6:09 ` Philippe Mathieu-Daudé
2026-07-24 0:09 ` [PATCH 04/27] hw/riscv: implement TYPE_TARGET_SPECIFIC Pierrick Bouvier
` (25 subsequent siblings)
28 siblings, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
include/qemu/target-info.h | 16 +++++++++++++++-
target-info.c | 16 ++++++++++++++++
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 6c5b714288e..88ccef2a988 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -99,10 +99,24 @@ bool target_ppc64(void);
*/
bool target_s390x(void);
+/**
+ * target_base_riscv:
+ *
+ * Returns whether the target architecture is RISC-V 32-bit or 64-bit.
+ */
+bool target_base_riscv(void);
+
+/**
+ * target_riscv32:
+ *
+ * Returns whether the target architecture is RISC-V 32-bit.
+ */
+bool target_riscv32(void);
+
/**
* target_riscv64:
*
- * Returns whether the target architecture is riscv64
+ * Returns whether the target architecture is RISC-V 64-bit.
*/
bool target_riscv64(void);
diff --git a/target-info.c b/target-info.c
index 04c69c41f8a..7ac2260b182 100644
--- a/target-info.c
+++ b/target-info.c
@@ -94,6 +94,22 @@ bool target_s390x(void)
return target_arch() == SYS_EMU_TARGET_S390X;
}
+bool target_base_riscv(void)
+{
+ switch (target_arch()) {
+ case SYS_EMU_TARGET_RISCV32:
+ case SYS_EMU_TARGET_RISCV64:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool target_riscv32(void)
+{
+ return target_arch() == SYS_EMU_TARGET_RISCV32;
+}
+
bool target_riscv64(void)
{
return target_arch() == SYS_EMU_TARGET_RISCV64;
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH 03/27] target-info: add target_riscv32 and target_base_riscv
2026-07-24 0:09 ` [PATCH 03/27] target-info: add target_riscv32 and target_base_riscv Pierrick Bouvier
@ 2026-07-24 6:09 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-24 6:09 UTC (permalink / raw)
To: Pierrick Bouvier, qemu-devel
Cc: Nicholas Piggin, Daniel Henrique Barboza, Bernhard Beschow,
Anton Johansson, Alistair Francis, Peter Maydell,
Alistair Francis
On 24/7/26 02:09, Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
> include/qemu/target-info.h | 16 +++++++++++++++-
> target-info.c | 16 ++++++++++++++++
> 2 files changed, 31 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 04/27] hw/riscv: implement TYPE_TARGET_SPECIFIC
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (2 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 03/27] target-info: add target_riscv32 and target_base_riscv Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 05/27] target-info: add target_config_multiprocess Pierrick Bouvier
` (24 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
For now, we still keep existing TYPE_TARGET_.*_MACHINE mechanic to not
break existing binaries. As a result, we add TYPE_TARGET_SPECIFIC to
list of interfaces *_machine_interfaces.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/riscv/boston-aia.c | 1 +
hw/riscv/k230.c | 1 +
hw/riscv/microblaze-v-generic.c | 1 +
hw/riscv/microchip_pfsoc.c | 1 +
hw/riscv/opentitan.c | 1 +
hw/riscv/shakti_c.c | 1 +
hw/riscv/sifive_e.c | 1 +
hw/riscv/sifive_u.c | 1 +
hw/riscv/spike.c | 1 +
hw/riscv/tt_atlantis.c | 1 +
hw/riscv/xiangshan_kmh.c | 1 +
include/hw/riscv/machines-qom.h | 2 ++
target/riscv/machine.c | 3 +++
13 files changed, 16 insertions(+)
diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c
index 965d0f5699e..42b16945c12 100644
--- a/hw/riscv/boston-aia.c
+++ b/hw/riscv/boston-aia.c
@@ -465,6 +465,7 @@ static void boston_mach_init(MachineState *machine)
static void boston_mach_class_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_riscv64;
mc->desc = "MIPS Boston-aia";
mc->init = boston_mach_init;
mc->block_default_type = IF_IDE;
diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
index 656f28190cd..0eb1bede222 100644
--- a/hw/riscv/k230.c
+++ b/hw/riscv/k230.c
@@ -504,6 +504,7 @@ static void k230_machine_instance_init(Object *obj)
static void k230_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_riscv64;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Board compatible with Kendryte K230 SDK";
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index d33ac39a68c..7cc24ed189f 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -179,6 +179,7 @@ static void mb_v_generic_init(MachineState *machine)
static void mb_v_generic_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_base_riscv;
mc->desc = "AMD Microblaze-V generic platform";
mc->init = mb_v_generic_init;
mc->min_cpus = 1;
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4017129c830..520d1fd4d11 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -722,6 +722,7 @@ static void microchip_icicle_kit_machine_instance_init(Object *obj)
static void microchip_icicle_kit_machine_class_init(ObjectClass *oc,
const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_riscv64;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Microchip PolarFire SoC Icicle Kit";
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 5b2f33d5aca..5c50b1c423d 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -117,6 +117,7 @@ static void opentitan_machine_init(MachineState *machine)
static void opentitan_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_riscv32;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Board compatible with OpenTitan";
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 835b1f879b7..7556fd8c854 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -78,6 +78,7 @@ static void shakti_c_machine_instance_init(Object *obj)
static void shakti_c_machine_class_init(ObjectClass *klass, const void *data)
{
+ TARGET_SPECIFIC_CLASS(klass)->is_available = target_riscv64;
MachineClass *mc = MACHINE_CLASS(klass);
static const char * const valid_cpu_types[] = {
RISCV_CPU_TYPE_NAME("shakti-c"),
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 71925583bd9..657f6ecad25 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -146,6 +146,7 @@ static void sifive_e_machine_instance_init(Object *obj)
static void sifive_e_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_riscv;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Board compatible with SiFive E SDK";
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 99423ef472d..33f1af2cdf1 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -653,6 +653,7 @@ static void sifive_u_machine_instance_init(Object *obj)
static void sifive_u_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_riscv;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Board compatible with SiFive U SDK";
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 9fde0faf39d..1f706f4dcc1 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -262,6 +262,7 @@ static void spike_machine_instance_init(Object *obj)
static void spike_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_base_riscv;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Spike board";
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index d808bcc11c3..ceaa88d5238 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -590,6 +590,7 @@ static void tt_atlantis_machine_init(MachineState *machine)
static void tt_atlantis_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_riscv64;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Tenstorrent Atlantis RISC-V SoC (Experimental)";
diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
index 384624d69ad..d8ee1dfa15e 100644
--- a/hw/riscv/xiangshan_kmh.c
+++ b/hw/riscv/xiangshan_kmh.c
@@ -196,6 +196,7 @@ static void xiangshan_kmh_machine_init(MachineState *machine)
static void xiangshan_kmh_machine_class_init(ObjectClass *klass, const void *data)
{
+ TARGET_SPECIFIC_CLASS(klass)->is_available = target_riscv64;
MachineClass *mc = MACHINE_CLASS(klass);
static const char *const valid_cpu_types[] = {
TYPE_RISCV_CPU_XIANGSHAN_KMH,
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index ee346227bb2..5a5b5e05f58 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -10,6 +10,8 @@
#define HW_RISCV_MACHINES_QOM_H
#include "hw/core/boards.h"
+#include "qemu/target-info.h"
+#include "qemu/target-info-qom.h"
#define TYPE_TARGET_RISCV32_MACHINE \
"target-info-riscv32-machine"
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 0ab613a2980..507e862f061 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "qemu/error-report.h"
+#include "qemu/target-info-qom.h"
#include "system/kvm.h"
#include "system/tcg.h"
#include "migration/cpu.h"
@@ -537,11 +538,13 @@ const VMStateDescription vmstate_riscv_cpu = {
};
const InterfaceInfo riscv32_machine_interfaces[] = {
+ { TYPE_TARGET_SPECIFIC },
{ TYPE_TARGET_RISCV32_MACHINE },
{ }
};
const InterfaceInfo riscv64_machine_interfaces[] = {
+ { TYPE_TARGET_SPECIFIC },
{ TYPE_TARGET_RISCV64_MACHINE },
{ }
};
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 05/27] target-info: add target_config_multiprocess
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (3 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 04/27] hw/riscv: implement TYPE_TARGET_SPECIFIC Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 06/27] hw/remote/machine: remove unsupported arm target Pierrick Bouvier
` (23 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
For some devices/machines, we'll need to access target configuration,
but without relying to target headers. Thus, we'll add the needed
information in target-info.
At this moment, we duplicate code between all configs/targets/*.c and
target-info-stub.c but we will clean up this before the end of this
series.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
configs/targets/aarch64-softmmu.c | 11 +++++++++++
configs/targets/arm-softmmu.c | 11 +++++++++++
configs/targets/riscv32-softmmu.c | 11 +++++++++++
configs/targets/riscv64-softmmu.c | 11 +++++++++++
include/qemu/target-info-impl.h | 3 +++
include/qemu/target-info.h | 7 +++++++
meson.build | 2 +-
target-info-stub.c | 12 ++++++++++++
target-info.c | 5 +++++
9 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
index 75d95b0e743..af65da80d04 100644
--- a/configs/targets/aarch64-softmmu.c
+++ b/configs/targets/aarch64-softmmu.c
@@ -12,6 +12,9 @@
#include "hw/arm/machines-qom.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/cpu-param.h"
+#ifndef CONFIG_USER_ONLY
+#include CONFIG_DEVICES
+#endif
static const TargetInfo target_info_aarch64_system = {
.target_name = "aarch64",
@@ -22,6 +25,14 @@ static const TargetInfo target_info_aarch64_system = {
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_vary = true,
.page_bits_init = TARGET_PAGE_BITS_LEGACY,
+
+#ifndef CONFIG_USER_ONLY
+# ifdef CONFIG_MULTIPROCESS
+ .config_multiprocess = true,
+# else
+ .config_multiprocess = false,
+# endif
+#endif
};
target_info_init(target_info_aarch64_system)
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
index 73546fa5737..501956403cc 100644
--- a/configs/targets/arm-softmmu.c
+++ b/configs/targets/arm-softmmu.c
@@ -12,6 +12,9 @@
#include "hw/arm/machines-qom.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/cpu-param.h"
+#ifndef CONFIG_USER_ONLY
+#include CONFIG_DEVICES
+#endif
static const TargetInfo target_info_arm_system = {
.target_name = "arm",
@@ -22,6 +25,14 @@ static const TargetInfo target_info_arm_system = {
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_vary = true,
.page_bits_init = TARGET_PAGE_BITS_LEGACY,
+
+#ifndef CONFIG_USER_ONLY
+# ifdef CONFIG_MULTIPROCESS
+ .config_multiprocess = true,
+# else
+ .config_multiprocess = false,
+# endif
+#endif
};
target_info_init(target_info_arm_system)
diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c
index 752c813077e..69053f3945e 100644
--- a/configs/targets/riscv32-softmmu.c
+++ b/configs/targets/riscv32-softmmu.c
@@ -12,6 +12,9 @@
#include "hw/riscv/machines-qom.h"
#include "target/riscv/cpu-qom.h"
#include "target/riscv/cpu-param.h"
+#ifndef CONFIG_USER_ONLY
+#include CONFIG_DEVICES
+#endif
static const TargetInfo target_info_riscv32_system = {
.target_name = "riscv32",
@@ -21,6 +24,14 @@ static const TargetInfo target_info_riscv32_system = {
.machine_typename = TYPE_TARGET_RISCV32_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_init = TARGET_PAGE_BITS,
+
+#ifndef CONFIG_USER_ONLY
+# ifdef CONFIG_MULTIPROCESS
+ .config_multiprocess = true,
+# else
+ .config_multiprocess = false,
+# endif
+#endif
};
target_info_init(target_info_riscv32_system)
diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c
index 5150f0fe9d9..cd0fb555986 100644
--- a/configs/targets/riscv64-softmmu.c
+++ b/configs/targets/riscv64-softmmu.c
@@ -12,6 +12,9 @@
#include "hw/riscv/machines-qom.h"
#include "target/riscv/cpu-qom.h"
#include "target/riscv/cpu-param.h"
+#ifndef CONFIG_USER_ONLY
+#include CONFIG_DEVICES
+#endif
static const TargetInfo target_info_riscv64_system = {
.target_name = "riscv64",
@@ -21,6 +24,14 @@ static const TargetInfo target_info_riscv64_system = {
.machine_typename = TYPE_TARGET_RISCV64_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_init = TARGET_PAGE_BITS,
+
+#ifndef CONFIG_USER_ONLY
+# ifdef CONFIG_MULTIPROCESS
+ .config_multiprocess = true,
+# else
+ .config_multiprocess = false,
+# endif
+#endif
};
target_info_init(target_info_riscv64_system)
diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
index c917d546eab..0496eeac046 100644
--- a/include/qemu/target-info-impl.h
+++ b/include/qemu/target-info-impl.h
@@ -32,6 +32,9 @@ typedef struct TargetInfo {
unsigned page_bits_init;
/* runtime equivalent of TARGET_PAGE_BITS_VARY definition */
bool page_bits_vary;
+
+ /* CONFIG_MULTIPROCESS */
+ bool config_multiprocess;
} TargetInfo;
/**
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 88ccef2a988..996780150a0 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -120,4 +120,11 @@ bool target_riscv32(void);
*/
bool target_riscv64(void);
+/**
+ * target_config_multiprocess:
+ *
+ * Returns true if target defines CONFIG_MULTIPROCESS.
+ */
+bool target_config_multiprocess(void);
+
#endif
diff --git a/meson.build b/meson.build
index 49a5baf5b52..2b5db0d096a 100644
--- a/meson.build
+++ b/meson.build
@@ -4259,7 +4259,7 @@ foreach target : target_dirs
arch_deps = []
c_args = ['-DCOMPILING_PER_TARGET',
'-DCONFIG_TARGET="@0@-config-target.h"'.format(target),
- ]
+ '-DCONFIG_DEVICES="@0@-config-devices.h"'.format(target)]
link_args = emulator_link_args
target_inc = [include_directories('target' / config_target['TARGET_BASE_ARCH'])]
diff --git a/target-info-stub.c b/target-info-stub.c
index 22b7911201c..99c1b1cd7ef 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -14,6 +14,10 @@
#include "cpu.h"
#include "exec/cpu-defs.h"
#include "exec/page-vary.h"
+#ifndef CONFIG_USER_ONLY
+#include CONFIG_DEVICES
+#endif
+#include CONFIG_TARGET
/* Validate correct placement of CPUArchState. */
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
@@ -40,6 +44,14 @@ static const TargetInfo target_info_stub = {
.page_bits_vary = false,
.page_bits_init = TARGET_PAGE_BITS,
#endif
+
+#ifndef CONFIG_USER_ONLY
+# ifdef CONFIG_MULTIPROCESS
+ .config_multiprocess = true,
+# else
+ .config_multiprocess = false,
+# endif
+#endif
};
target_info_init(target_info_stub)
diff --git a/target-info.c b/target-info.c
index 7ac2260b182..07fde91b1ec 100644
--- a/target-info.c
+++ b/target-info.c
@@ -114,3 +114,8 @@ bool target_riscv64(void)
{
return target_arch() == SYS_EMU_TARGET_RISCV64;
}
+
+bool target_config_multiprocess(void)
+{
+ return target_info()->config_multiprocess;
+}
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 06/27] hw/remote/machine: remove unsupported arm target
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (4 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 05/27] target-info: add target_config_multiprocess Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 07/27] hw/remote/machine: implement TYPE_TARGET_SPECIFIC Pierrick Bouvier
` (22 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
With recent target machine changes, this machine was made available for
AArch32. However, it depends on CONFIG_KVM (see Kconfig), and since we
don't support 32 bit anymore, we don't support it. See main
meson.build and 'kvm_targets' for more details.
Fixes: 4e8ac6857faab2 "hw/remote/machine.c: Mark x-remote machine as OK for AArch64 and AArch32"
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/remote/machine.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/remote/machine.c b/hw/remote/machine.c
index df08f640199..88d38b75d52 100644
--- a/hw/remote/machine.c
+++ b/hw/remote/machine.c
@@ -150,7 +150,6 @@ static const TypeInfo remote_machine = {
.interfaces = (const InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
{ TYPE_TARGET_AARCH64_MACHINE },
- { TYPE_TARGET_ARM_MACHINE },
{ }
}
};
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 07/27] hw/remote/machine: implement TYPE_TARGET_SPECIFIC
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (5 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 06/27] hw/remote/machine: remove unsupported arm target Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 08/27] target-info: add target_config_xen Pierrick Bouvier
` (21 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
This board is a bit special since it's not "statically" available for a
given target, but a combination of host + target.
From meson.build, we can see it's present only when CONFIG_MULTIPROCESS
is set. From Kconfig, we can see it's set when PCI && PCI_EXPRESS &&
KVM. CONFIG_KVM is defined for specific host/targets combination.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/remote/machine.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/remote/machine.c b/hw/remote/machine.c
index 88d38b75d52..fa750368df2 100644
--- a/hw/remote/machine.c
+++ b/hw/remote/machine.c
@@ -124,6 +124,7 @@ static void remote_machine_dev_unplug_cb(HotplugHandler *hotplug_dev,
static void remote_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_config_multiprocess;
MachineClass *mc = MACHINE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
@@ -149,6 +150,7 @@ static const TypeInfo remote_machine = {
.class_init = remote_machine_class_init,
.interfaces = (const InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
+ { TYPE_TARGET_SPECIFIC },
{ TYPE_TARGET_AARCH64_MACHINE },
{ }
}
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 08/27] target-info: add target_config_xen
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (6 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 07/27] hw/remote/machine: implement TYPE_TARGET_SPECIFIC Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 09/27] hw/arm/xen-pvh: implement TYPE_TARGET_SPECIFIC Pierrick Bouvier
` (20 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
At this moment, we duplicate code between all configs/targets/*.c and
target-info-stub.c but we will clean up this before the end of this
series.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
configs/targets/aarch64-softmmu.c | 5 +++++
configs/targets/arm-softmmu.c | 5 +++++
configs/targets/riscv32-softmmu.c | 5 +++++
configs/targets/riscv64-softmmu.c | 5 +++++
include/qemu/target-info-impl.h | 2 ++
include/qemu/target-info.h | 7 +++++++
target-info-stub.c | 5 +++++
target-info.c | 5 +++++
8 files changed, 39 insertions(+)
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
index af65da80d04..4cf13a187d9 100644
--- a/configs/targets/aarch64-softmmu.c
+++ b/configs/targets/aarch64-softmmu.c
@@ -32,6 +32,11 @@ static const TargetInfo target_info_aarch64_system = {
# else
.config_multiprocess = false,
# endif
+# ifdef CONFIG_XEN
+ .config_xen = true,
+# else
+ .config_xen = false,
+# endif
#endif
};
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
index 501956403cc..f9b8212fc3c 100644
--- a/configs/targets/arm-softmmu.c
+++ b/configs/targets/arm-softmmu.c
@@ -32,6 +32,11 @@ static const TargetInfo target_info_arm_system = {
# else
.config_multiprocess = false,
# endif
+# ifdef CONFIG_XEN
+ .config_xen = true,
+# else
+ .config_xen = false,
+# endif
#endif
};
diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c
index 69053f3945e..4fe8b096ce0 100644
--- a/configs/targets/riscv32-softmmu.c
+++ b/configs/targets/riscv32-softmmu.c
@@ -31,6 +31,11 @@ static const TargetInfo target_info_riscv32_system = {
# else
.config_multiprocess = false,
# endif
+# ifdef CONFIG_XEN
+ .config_xen = true,
+# else
+ .config_xen = false,
+# endif
#endif
};
diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c
index cd0fb555986..cfcdac89697 100644
--- a/configs/targets/riscv64-softmmu.c
+++ b/configs/targets/riscv64-softmmu.c
@@ -31,6 +31,11 @@ static const TargetInfo target_info_riscv64_system = {
# else
.config_multiprocess = false,
# endif
+# ifdef CONFIG_XEN
+ .config_xen = true,
+# else
+ .config_xen = false,
+# endif
#endif
};
diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
index 0496eeac046..98542bdaeeb 100644
--- a/include/qemu/target-info-impl.h
+++ b/include/qemu/target-info-impl.h
@@ -35,6 +35,8 @@ typedef struct TargetInfo {
/* CONFIG_MULTIPROCESS */
bool config_multiprocess;
+ /* CONFIG_XEN */
+ bool config_xen;
} TargetInfo;
/**
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 996780150a0..0ecae9411c3 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -127,4 +127,11 @@ bool target_riscv64(void);
*/
bool target_config_multiprocess(void);
+/**
+ * target_config_xen:
+ *
+ * Returns true if target defines CONFIG_XEN.
+ */
+bool target_config_xen(void);
+
#endif
diff --git a/target-info-stub.c b/target-info-stub.c
index 99c1b1cd7ef..bafbeaa039f 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -51,6 +51,11 @@ static const TargetInfo target_info_stub = {
# else
.config_multiprocess = false,
# endif
+# ifdef CONFIG_XEN
+ .config_xen = true,
+# else
+ .config_xen = false,
+# endif
#endif
};
diff --git a/target-info.c b/target-info.c
index 07fde91b1ec..a264c51ce83 100644
--- a/target-info.c
+++ b/target-info.c
@@ -119,3 +119,8 @@ bool target_config_multiprocess(void)
{
return target_info()->config_multiprocess;
}
+
+bool target_config_xen(void)
+{
+ return target_info()->config_xen;
+}
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 09/27] hw/arm/xen-pvh: implement TYPE_TARGET_SPECIFIC
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (7 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 08/27] target-info: add target_config_xen Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 10/27] hw/xenpv/xen_machine_pv: " Pierrick Bouvier
` (19 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/arm/xen-pvh.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index 10cac28a910..fd83fa5f541 100644
--- a/hw/arm/xen-pvh.c
+++ b/hw/arm/xen-pvh.c
@@ -51,6 +51,7 @@ static void xen_pvh_set_pci_intx_irq(void *opaque, int intx_irq, int level)
static void xen_arm_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_config_xen;
XenPVHMachineClass *xpc = XEN_PVH_MACHINE_CLASS(oc);
MachineClass *mc = MACHINE_CLASS(oc);
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 10/27] hw/xenpv/xen_machine_pv: implement TYPE_TARGET_SPECIFIC
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (8 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 09/27] hw/arm/xen-pvh: implement TYPE_TARGET_SPECIFIC Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 11/27] target-info: add target_config_nitro Pierrick Bouvier
` (18 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/xenpv/xen_machine_pv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/xenpv/xen_machine_pv.c b/hw/xenpv/xen_machine_pv.c
index c406821c34c..40b975d0e16 100644
--- a/hw/xenpv/xen_machine_pv.c
+++ b/hw/xenpv/xen_machine_pv.c
@@ -63,10 +63,11 @@ static void xen_init_pv(MachineState *machine)
static void xenpv_machine_init(MachineClass *mc)
{
+ TARGET_SPECIFIC_CLASS(mc)->is_available = target_config_xen;
mc->desc = "Xen Para-virtualized PC";
mc->init = xen_init_pv;
mc->max_cpus = 1;
mc->default_machine_opts = "accel=xen";
}
-DEFINE_MACHINE("xenpv", xenpv_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("xenpv", xenpv_machine_init)
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 11/27] target-info: add target_config_nitro
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (9 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 10/27] hw/xenpv/xen_machine_pv: " Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 12/27] hw/nitro/machine: implement TYPE_TARGET_SPECIFIC Pierrick Bouvier
` (17 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
At this moment, we duplicate code between all configs/targets/*.c and
target-info-stub.c but we will clean up this before the end of this
series.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
configs/targets/aarch64-softmmu.c | 5 +++++
configs/targets/arm-softmmu.c | 5 +++++
configs/targets/riscv32-softmmu.c | 5 +++++
configs/targets/riscv64-softmmu.c | 5 +++++
include/qemu/target-info-impl.h | 2 ++
include/qemu/target-info.h | 7 +++++++
target-info-stub.c | 5 +++++
target-info.c | 5 +++++
8 files changed, 39 insertions(+)
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
index 4cf13a187d9..0d8519c3267 100644
--- a/configs/targets/aarch64-softmmu.c
+++ b/configs/targets/aarch64-softmmu.c
@@ -32,6 +32,11 @@ static const TargetInfo target_info_aarch64_system = {
# else
.config_multiprocess = false,
# endif
+# ifdef CONFIG_NITRO
+ .config_nitro = true,
+# else
+ .config_nitro = false,
+# endif
# ifdef CONFIG_XEN
.config_xen = true,
# else
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
index f9b8212fc3c..9ea63d8662e 100644
--- a/configs/targets/arm-softmmu.c
+++ b/configs/targets/arm-softmmu.c
@@ -32,6 +32,11 @@ static const TargetInfo target_info_arm_system = {
# else
.config_multiprocess = false,
# endif
+# ifdef CONFIG_NITRO
+ .config_nitro = true,
+# else
+ .config_nitro = false,
+# endif
# ifdef CONFIG_XEN
.config_xen = true,
# else
diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c
index 4fe8b096ce0..208d5792fb4 100644
--- a/configs/targets/riscv32-softmmu.c
+++ b/configs/targets/riscv32-softmmu.c
@@ -31,6 +31,11 @@ static const TargetInfo target_info_riscv32_system = {
# else
.config_multiprocess = false,
# endif
+# ifdef CONFIG_NITRO
+ .config_nitro = true,
+# else
+ .config_nitro = false,
+# endif
# ifdef CONFIG_XEN
.config_xen = true,
# else
diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c
index cfcdac89697..1e0896d8db7 100644
--- a/configs/targets/riscv64-softmmu.c
+++ b/configs/targets/riscv64-softmmu.c
@@ -31,6 +31,11 @@ static const TargetInfo target_info_riscv64_system = {
# else
.config_multiprocess = false,
# endif
+# ifdef CONFIG_NITRO
+ .config_nitro = true,
+# else
+ .config_nitro = false,
+# endif
# ifdef CONFIG_XEN
.config_xen = true,
# else
diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
index 98542bdaeeb..d9c4f0a5da0 100644
--- a/include/qemu/target-info-impl.h
+++ b/include/qemu/target-info-impl.h
@@ -35,6 +35,8 @@ typedef struct TargetInfo {
/* CONFIG_MULTIPROCESS */
bool config_multiprocess;
+ /* CONFIG_NITRO */
+ bool config_nitro;
/* CONFIG_XEN */
bool config_xen;
} TargetInfo;
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 0ecae9411c3..96d85aecdeb 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -127,6 +127,13 @@ bool target_riscv64(void);
*/
bool target_config_multiprocess(void);
+/**
+ * target_config_nitro:
+ *
+ * Returns true if target defines CONFIG_NITRO.
+ */
+bool target_config_nitro(void);
+
/**
* target_config_xen:
*
diff --git a/target-info-stub.c b/target-info-stub.c
index bafbeaa039f..ca5bdfc5a91 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -51,6 +51,11 @@ static const TargetInfo target_info_stub = {
# else
.config_multiprocess = false,
# endif
+# ifdef CONFIG_NITRO
+ .config_nitro = true,
+# else
+ .config_nitro = false,
+# endif
# ifdef CONFIG_XEN
.config_xen = true,
# else
diff --git a/target-info.c b/target-info.c
index a264c51ce83..067feff98cb 100644
--- a/target-info.c
+++ b/target-info.c
@@ -120,6 +120,11 @@ bool target_config_multiprocess(void)
return target_info()->config_multiprocess;
}
+bool target_config_nitro(void)
+{
+ return target_info()->config_nitro;
+}
+
bool target_config_xen(void)
{
return target_info()->config_xen;
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 12/27] hw/nitro/machine: implement TYPE_TARGET_SPECIFIC
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (10 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 11/27] target-info: add target_config_nitro Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 13/27] target-info-qom: implement new machine filtering per target Pierrick Bouvier
` (16 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
This machine is available only for aarch64 host/guest and x86_64
host/guest combinations. Some nitro devices follow the same rule also.
To avoid duplicated information, we use CONFIG_NITRO instead.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/nitro/machine.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/nitro/machine.c b/hw/nitro/machine.c
index 8849959359c..79d57664886 100644
--- a/hw/nitro/machine.c
+++ b/hw/nitro/machine.c
@@ -248,6 +248,7 @@ out:
static void nitro_machine_class_init(ObjectClass *oc, const void *data)
{
+ TARGET_SPECIFIC_CLASS(oc)->is_available = target_config_nitro;
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Nitro Enclave";
@@ -264,6 +265,7 @@ static const TypeInfo nitro_machine_info = {
.class_init = nitro_machine_class_init,
.interfaces = (const InterfaceInfo[]) {
/* x86_64 and aarch64 only */
+ { TYPE_TARGET_SPECIFIC },
{ TYPE_TARGET_AARCH64_MACHINE },
{ }
},
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 13/27] target-info-qom: implement new machine filtering per target
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (11 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 12/27] hw/nitro/machine: implement TYPE_TARGET_SPECIFIC Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 6:12 ` Philippe Mathieu-Daudé
2026-07-24 0:09 ` [PATCH 14/27] target-info-qom: use TYPE_MACHINE instead of target_machine_typename Pierrick Bouvier
` (15 subsequent siblings)
28 siblings, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Now we tagged and implemented TYPE_TARGET_SPECIFIC for all boards, we
can implement the new filtering mechanic. We update all locations
querying list of machines accordingly.
We make sure that all machines implementing TYPE_TARGET_SPECIFIC have
is_available overriden.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/core/machine-qmp-cmds.c | 3 ++-
include/qemu/target-info-qom.h | 7 +++++++
monitor/qemu-config-qmp.c | 4 ++--
system/vl.c | 5 ++---
target-info-qom.c | 31 +++++++++++++++++++++++++++++++
5 files changed, 44 insertions(+), 6 deletions(-)
diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c
index e62cb4ec888..e6e6ecc31e3 100644
--- a/hw/core/machine-qmp-cmds.c
+++ b/hw/core/machine-qmp-cmds.c
@@ -21,6 +21,7 @@
#include "qapi/type-helpers.h"
#include "qemu/uuid.h"
#include "qemu/target-info.h"
+#include "qemu/target-info-qom.h"
#include "qemu/target-info-qapi.h"
#include "qom/qom-qobject.h"
#include "system/hostmem.h"
@@ -98,7 +99,7 @@ MachineInfoList *qmp_query_machines(bool has_compat_props, bool compat_props,
GSList *el, *machines;
MachineInfoList *mach_list = NULL;
- machines = object_class_get_list(target_machine_typename(), false);
+ machines = get_machine_types_available();
for (el = machines; el; el = el->next) {
MachineClass *mc = el->data;
const char *default_cpu_type = machine_class_default_cpu_type(mc);
diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
index 83eb537333b..9f175bed057 100644
--- a/include/qemu/target-info-qom.h
+++ b/include/qemu/target-info-qom.h
@@ -42,4 +42,11 @@ OBJECT_DECLARE_TYPE(TargetInfoQom, TargetInfoQomClass, TARGET_INFO)
void target_info_qom_set_target(void);
+/**
+ * get_machine_types_available:
+ *
+ * Returns: Machine classes available for the selected target.
+ */
+GSList *get_machine_types_available(void);
+
#endif /* QEMU_TARGET_INFO_QOM_H */
diff --git a/monitor/qemu-config-qmp.c b/monitor/qemu-config-qmp.c
index 29801023564..3b06aea734f 100644
--- a/monitor/qemu-config-qmp.c
+++ b/monitor/qemu-config-qmp.c
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include "qemu/osdep.h"
-#include "qemu/target-info.h"
+#include "qemu/target-info-qom.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-misc.h"
#include "qobject/qlist.h"
@@ -129,7 +129,7 @@ static CommandLineParameterInfoList *query_all_machine_properties(void)
ObjectProperty *prop;
bool is_new;
- machines = object_class_get_list(target_machine_typename(), false);
+ machines = get_machine_types_available();
assert(machines);
/* Loop over all machine classes */
diff --git a/system/vl.c b/system/vl.c
index 061cbdf860b..83b9425de9b 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -1570,7 +1570,7 @@ static void machine_help_func(const QDict *qdict)
GSList *el;
const char *type = qdict_get_try_str(qdict, "type");
- machines = object_class_get_list(target_machine_typename(), false);
+ machines = get_machine_types_available();
if (type) {
ObjectClass *machine_class = OBJECT_CLASS(find_machine(type, machines));
if (machine_class) {
@@ -1682,8 +1682,7 @@ static MachineClass *select_machine(QDict *qdict, Error **errp)
{
ERRP_GUARD();
const char *machine_type = qdict_get_try_str(qdict, "type");
- g_autoptr(GSList) machines = object_class_get_list(target_machine_typename(),
- false);
+ g_autoptr(GSList) machines = get_machine_types_available();
MachineClass *machine_class = NULL;
if (machine_type) {
diff --git a/target-info-qom.c b/target-info-qom.c
index 1388691657c..67102c31a80 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -41,6 +41,37 @@ static const TypeInfo target_info_types[] = {
DEFINE_TYPES(target_info_types)
+static GSList *filter_types_available(GSList *types)
+{
+ GSList **link = &types;
+
+ while (*link) {
+ ObjectClass *oc = (*link)->data;
+ TargetSpecificClass *tsc = (TargetSpecificClass *)
+ object_class_dynamic_cast(oc, TYPE_TARGET_SPECIFIC);
+
+ if (tsc && !tsc->is_available) {
+ error_setg(&error_fatal,
+ "%s is target specific, but does not "
+ "implement interface", object_class_get_name(oc));
+ }
+ if (tsc && !tsc->is_available()) {
+ *link = g_slist_delete_link(*link, *link);
+ } else {
+ link = &(*link)->next;
+ }
+ }
+
+ return types;
+}
+
+GSList *get_machine_types_available(void)
+{
+ GSList *machines = object_class_get_list_sorted(target_machine_typename(), false);
+
+ return filter_types_available(machines);
+}
+
static void target_info_qom_class_init(ObjectClass *oc, const void * data)
{
TargetInfoQomClass *klass = TARGET_INFO_CLASS(oc);
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH 13/27] target-info-qom: implement new machine filtering per target
2026-07-24 0:09 ` [PATCH 13/27] target-info-qom: implement new machine filtering per target Pierrick Bouvier
@ 2026-07-24 6:12 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-24 6:12 UTC (permalink / raw)
To: Pierrick Bouvier, qemu-devel
Cc: Nicholas Piggin, Daniel Henrique Barboza, Bernhard Beschow,
Anton Johansson, Alistair Francis, Peter Maydell,
Alistair Francis
On 24/7/26 02:09, Pierrick Bouvier wrote:
> Now we tagged and implemented TYPE_TARGET_SPECIFIC for all boards, we
> can implement the new filtering mechanic. We update all locations
> querying list of machines accordingly.
>
> We make sure that all machines implementing TYPE_TARGET_SPECIFIC have
> is_available overriden.
>
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
> hw/core/machine-qmp-cmds.c | 3 ++-
> include/qemu/target-info-qom.h | 7 +++++++
> monitor/qemu-config-qmp.c | 4 ++--
> system/vl.c | 5 ++---
> target-info-qom.c | 31 +++++++++++++++++++++++++++++++
> 5 files changed, 44 insertions(+), 6 deletions(-)
> diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
> index 83eb537333b..9f175bed057 100644
> --- a/include/qemu/target-info-qom.h
> +++ b/include/qemu/target-info-qom.h
> @@ -42,4 +42,11 @@ OBJECT_DECLARE_TYPE(TargetInfoQom, TargetInfoQomClass, TARGET_INFO)
>
> void target_info_qom_set_target(void);
>
> +/**
> + * get_machine_types_available:
> + *
> + * Returns: Machine classes available for the selected target.
> + */
> +GSList *get_machine_types_available(void);
machine_get_available_types(), otherwise:
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 14/27] target-info-qom: use TYPE_MACHINE instead of target_machine_typename
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (12 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 13/27] target-info-qom: implement new machine filtering per target Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 6:12 ` Philippe Mathieu-Daudé
2026-07-24 0:09 ` [PATCH 15/27] target-info: remove target_machine_typename Pierrick Bouvier
` (14 subsequent siblings)
28 siblings, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Now that we implemented the new filtering logic based on
TYPE_TARGET_SPECIFIC, we don't need target_machine_typename anymore.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
target-info-qom.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-info-qom.c b/target-info-qom.c
index 67102c31a80..7ee2614b324 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -13,6 +13,7 @@
#include "qemu/target-info-init.h"
#include "qemu/target-info-qom.h"
#include "hw/arm/machines-qom.h"
+#include "hw/core/boards.h"
#include "hw/riscv/machines-qom.h"
static const TypeInfo target_info_types[] = {
@@ -67,7 +68,7 @@ static GSList *filter_types_available(GSList *types)
GSList *get_machine_types_available(void)
{
- GSList *machines = object_class_get_list_sorted(target_machine_typename(), false);
+ GSList *machines = object_class_get_list_sorted(TYPE_MACHINE, false);
return filter_types_available(machines);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH 14/27] target-info-qom: use TYPE_MACHINE instead of target_machine_typename
2026-07-24 0:09 ` [PATCH 14/27] target-info-qom: use TYPE_MACHINE instead of target_machine_typename Pierrick Bouvier
@ 2026-07-24 6:12 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-24 6:12 UTC (permalink / raw)
To: Pierrick Bouvier, qemu-devel
Cc: Nicholas Piggin, Daniel Henrique Barboza, Bernhard Beschow,
Anton Johansson, Alistair Francis, Peter Maydell,
Alistair Francis
On 24/7/26 02:09, Pierrick Bouvier wrote:
> Now that we implemented the new filtering logic based on
> TYPE_TARGET_SPECIFIC, we don't need target_machine_typename anymore.
>
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
> target-info-qom.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH 15/27] target-info: remove target_machine_typename
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (13 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 14/27] target-info-qom: use TYPE_MACHINE instead of target_machine_typename Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 16/27] target-info-qom: add type_target_specific Pierrick Bouvier
` (13 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
configs/targets/aarch64-softmmu.c | 1 -
configs/targets/arm-softmmu.c | 1 -
configs/targets/riscv32-softmmu.c | 1 -
configs/targets/riscv64-softmmu.c | 1 -
include/qemu/target-info-impl.h | 2 --
include/qemu/target-info.h | 8 --------
target-info-stub.c | 1 -
target-info.c | 5 -----
8 files changed, 20 deletions(-)
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
index 0d8519c3267..381a9f686a5 100644
--- a/configs/targets/aarch64-softmmu.c
+++ b/configs/targets/aarch64-softmmu.c
@@ -21,7 +21,6 @@ static const TargetInfo target_info_aarch64_system = {
.target_arch = SYS_EMU_TARGET_AARCH64,
.long_bits = 64,
.cpu_type = TYPE_ARM_CPU,
- .machine_typename = TYPE_TARGET_AARCH64_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_vary = true,
.page_bits_init = TARGET_PAGE_BITS_LEGACY,
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
index 9ea63d8662e..4f946708864 100644
--- a/configs/targets/arm-softmmu.c
+++ b/configs/targets/arm-softmmu.c
@@ -21,7 +21,6 @@ static const TargetInfo target_info_arm_system = {
.target_arch = SYS_EMU_TARGET_ARM,
.long_bits = 32,
.cpu_type = TYPE_ARM_CPU,
- .machine_typename = TYPE_TARGET_ARM_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_vary = true,
.page_bits_init = TARGET_PAGE_BITS_LEGACY,
diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c
index 208d5792fb4..48d55bfc354 100644
--- a/configs/targets/riscv32-softmmu.c
+++ b/configs/targets/riscv32-softmmu.c
@@ -21,7 +21,6 @@ static const TargetInfo target_info_riscv32_system = {
.target_arch = SYS_EMU_TARGET_RISCV32,
.long_bits = 32,
.cpu_type = TYPE_RISCV_CPU,
- .machine_typename = TYPE_TARGET_RISCV32_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_init = TARGET_PAGE_BITS,
diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c
index 1e0896d8db7..01013bb5b7c 100644
--- a/configs/targets/riscv64-softmmu.c
+++ b/configs/targets/riscv64-softmmu.c
@@ -21,7 +21,6 @@ static const TargetInfo target_info_riscv64_system = {
.target_arch = SYS_EMU_TARGET_RISCV64,
.long_bits = 64,
.cpu_type = TYPE_RISCV_CPU,
- .machine_typename = TYPE_TARGET_RISCV64_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_init = TARGET_PAGE_BITS,
diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
index d9c4f0a5da0..de329ec2b86 100644
--- a/include/qemu/target-info-impl.h
+++ b/include/qemu/target-info-impl.h
@@ -21,8 +21,6 @@ typedef struct TargetInfo {
unsigned long_bits;
/* runtime equivalent of CPU_RESOLVING_TYPE definition */
const char *cpu_type;
- /* QOM typename machines for this binary must implement */
- const char *machine_typename;
/* related to TARGET_BIG_ENDIAN definition */
EndianMode endianness;
/*
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 96d85aecdeb..46d0efd6498 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -23,14 +23,6 @@ const char *target_name(void);
*/
unsigned target_long_bits(void);
-/**
- * target_machine_typename:
- *
- * Returns: Name of the QOM interface implemented by machines
- * usable on this target binary.
- */
-const char *target_machine_typename(void);
-
/**
* target_cpu_type:
*
diff --git a/target-info-stub.c b/target-info-stub.c
index ca5bdfc5a91..71a6064548f 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -33,7 +33,6 @@ static const TargetInfo target_info_stub = {
.target_arch = glue(SYS_EMU_TARGET_, TARGET_ARCH),
.long_bits = TARGET_LONG_BITS,
.cpu_type = CPU_RESOLVING_TYPE,
- .machine_typename = TYPE_MACHINE,
.endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG : ENDIAN_MODE_LITTLE,
#ifdef TARGET_PAGE_BITS_VARY
.page_bits_vary = true,
diff --git a/target-info.c b/target-info.c
index 067feff98cb..ce7f9797dce 100644
--- a/target-info.c
+++ b/target-info.c
@@ -32,11 +32,6 @@ const char *target_cpu_type(void)
return target_info()->cpu_type;
}
-const char *target_machine_typename(void)
-{
- return target_info()->machine_typename;
-}
-
EndianMode target_endian_mode(void)
{
return target_info()->endianness;
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 16/27] target-info-qom: add type_target_specific
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (14 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 15/27] target-info: remove target_machine_typename Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 17/27] hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE Pierrick Bouvier
` (12 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
We'll now clean all target specific interfaces. For this, we need to be
able to replace them with our new TYPE_TARGET_SPECIFIC interface.
Define a global array to be referenced by all concerned types.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
include/qemu/target-info-qom.h | 2 ++
target-info-qom.c | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/include/qemu/target-info-qom.h b/include/qemu/target-info-qom.h
index 9f175bed057..842cf241e0a 100644
--- a/include/qemu/target-info-qom.h
+++ b/include/qemu/target-info-qom.h
@@ -49,4 +49,6 @@ void target_info_qom_set_target(void);
*/
GSList *get_machine_types_available(void);
+extern const InterfaceInfo type_target_specific[];
+
#endif /* QEMU_TARGET_INFO_QOM_H */
diff --git a/target-info-qom.c b/target-info-qom.c
index 7ee2614b324..9089ef336a7 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -16,6 +16,11 @@
#include "hw/core/boards.h"
#include "hw/riscv/machines-qom.h"
+const InterfaceInfo type_target_specific[] = {
+ { TYPE_TARGET_SPECIFIC },
+ { }
+};
+
static const TypeInfo target_info_types[] = {
{
.name = TYPE_TARGET_SPECIFIC,
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 17/27] hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (15 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 16/27] target-info-qom: add type_target_specific Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 18/27] hw/arm: remove {arm, arm_aarch64, aarch64}_machine_interfaces Pierrick Bouvier via qemu development
` (11 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/core/null-machine.c | 2 --
hw/nitro/machine.c | 1 -
hw/remote/machine.c | 1 -
include/hw/arm/machines-qom.h | 6 ------
target-info-qom.c | 8 --------
target/arm/machine.c | 5 -----
6 files changed, 23 deletions(-)
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index f132a7b89b4..c1ecf3214fd 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -58,8 +58,6 @@ static void machine_none_machine_init(MachineClass *mc)
}
DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init,
- { TYPE_TARGET_AARCH64_MACHINE },
- { TYPE_TARGET_ARM_MACHINE },
{ TYPE_TARGET_RISCV32_MACHINE },
{ TYPE_TARGET_RISCV64_MACHINE },
{ })
diff --git a/hw/nitro/machine.c b/hw/nitro/machine.c
index 79d57664886..2d001a32fe2 100644
--- a/hw/nitro/machine.c
+++ b/hw/nitro/machine.c
@@ -266,7 +266,6 @@ static const TypeInfo nitro_machine_info = {
.interfaces = (const InterfaceInfo[]) {
/* x86_64 and aarch64 only */
{ TYPE_TARGET_SPECIFIC },
- { TYPE_TARGET_AARCH64_MACHINE },
{ }
},
};
diff --git a/hw/remote/machine.c b/hw/remote/machine.c
index fa750368df2..932d14e53e9 100644
--- a/hw/remote/machine.c
+++ b/hw/remote/machine.c
@@ -151,7 +151,6 @@ static const TypeInfo remote_machine = {
.interfaces = (const InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
{ TYPE_TARGET_SPECIFIC },
- { TYPE_TARGET_AARCH64_MACHINE },
{ }
}
};
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
index 37fb64bf479..91b2c57c6d2 100644
--- a/include/hw/arm/machines-qom.h
+++ b/include/hw/arm/machines-qom.h
@@ -13,12 +13,6 @@
#include "qemu/target-info.h"
#include "qemu/target-info-qom.h"
-#define TYPE_TARGET_ARM_MACHINE \
- "target-info-arm-machine"
-
-#define TYPE_TARGET_AARCH64_MACHINE \
- "target-info-aarch64-machine"
-
/*
* A machine filtered with arm_machine_interfaces[] or
* arm_aarch64_machine_interfaces[] will be available
diff --git a/target-info-qom.c b/target-info-qom.c
index 9089ef336a7..d7b8fbd4fcd 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -27,14 +27,6 @@ static const TypeInfo target_info_types[] = {
.parent = TYPE_INTERFACE,
.class_size = sizeof(TargetSpecificClass),
},
- {
- .name = TYPE_TARGET_ARM_MACHINE,
- .parent = TYPE_INTERFACE,
- },
- {
- .name = TYPE_TARGET_AARCH64_MACHINE,
- .parent = TYPE_INTERFACE,
- },
{
.name = TYPE_TARGET_RISCV32_MACHINE,
.parent = TYPE_INTERFACE,
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 60501d17911..8f0d927ab63 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -1350,20 +1350,15 @@ const VMStateDescription vmstate_arm_cpu = {
const InterfaceInfo arm_machine_interfaces[] = {
{ TYPE_TARGET_SPECIFIC },
- { TYPE_TARGET_ARM_MACHINE },
- { TYPE_TARGET_AARCH64_MACHINE },
{ }
};
const InterfaceInfo arm_aarch64_machine_interfaces[] = {
{ TYPE_TARGET_SPECIFIC },
- { TYPE_TARGET_ARM_MACHINE },
- { TYPE_TARGET_AARCH64_MACHINE },
{ }
};
const InterfaceInfo aarch64_machine_interfaces[] = {
{ TYPE_TARGET_SPECIFIC },
- { TYPE_TARGET_AARCH64_MACHINE },
{ }
};
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 18/27] hw/arm: remove {arm, arm_aarch64, aarch64}_machine_interfaces
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (16 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 17/27] hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier via qemu development
2026-07-24 0:09 ` [PATCH 19/27] include/hw/core/boards.h: add DEFINE_MACHINE_TARGET_SPECIFIC Pierrick Bouvier
` (10 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier via qemu development @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
We can now remove those arrays, and use type_target_specific instead.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/arm/aspeed_ast1040_evb.c | 2 +-
hw/arm/aspeed_ast10x0_evb.c | 4 ++--
hw/arm/aspeed_ast2400_palmetto.c | 2 +-
hw/arm/aspeed_ast2400_quanta-q71l.c | 2 +-
hw/arm/aspeed_ast2400_supermicrox11.c | 2 +-
hw/arm/aspeed_ast2500_evb.c | 2 +-
hw/arm/aspeed_ast2500_g220a.c | 2 +-
hw/arm/aspeed_ast2500_romulus.c | 2 +-
hw/arm/aspeed_ast2500_supermicro-x11spi.c | 2 +-
hw/arm/aspeed_ast2500_tiogapass.c | 2 +-
hw/arm/aspeed_ast2500_witherspoon.c | 2 +-
hw/arm/aspeed_ast2500_yosemitev2.c | 2 +-
hw/arm/aspeed_ast2600_anacapa.c | 2 +-
hw/arm/aspeed_ast2600_bletchley.c | 2 +-
hw/arm/aspeed_ast2600_catalina.c | 2 +-
hw/arm/aspeed_ast2600_evb.c | 2 +-
hw/arm/aspeed_ast2600_fby35.c | 2 +-
hw/arm/aspeed_ast2600_fuji.c | 2 +-
hw/arm/aspeed_ast2600_gb200nvl.c | 2 +-
hw/arm/aspeed_ast2600_rainier.c | 2 +-
hw/arm/aspeed_ast27x0-fc.c | 2 +-
hw/arm/aspeed_ast27x0_evb.c | 4 ++--
hw/arm/b-l475e-iot01a.c | 2 +-
hw/arm/collie.c | 2 +-
hw/arm/exynos4_boards.c | 4 ++--
hw/arm/imx8mp-evk.c | 2 +-
hw/arm/microbit.c | 2 +-
hw/arm/mps2-tz.c | 8 ++++----
hw/arm/mps2.c | 8 ++++----
hw/arm/mps3r.c | 2 +-
hw/arm/musca.c | 4 ++--
hw/arm/npcm7xx_boards.c | 10 +++++-----
hw/arm/npcm8xx_boards.c | 2 +-
hw/arm/omap_sx1.c | 4 ++--
hw/arm/raspi.c | 10 +++++-----
hw/arm/raspi4b.c | 2 +-
hw/arm/realview.c | 8 ++++----
hw/arm/sabrelite.c | 2 +-
hw/arm/sbsa-ref.c | 2 +-
hw/arm/stellaris.c | 4 ++--
hw/arm/versatilepb.c | 4 ++--
hw/arm/vexpress.c | 4 ++--
hw/arm/virt.c | 2 +-
hw/arm/xen-pvh.c | 2 +-
hw/arm/xilinx_zynq.c | 2 +-
hw/arm/xlnx-versal-virt.c | 4 ++--
hw/arm/xlnx-zcu102.c | 2 +-
include/hw/arm/machines-qom.h | 16 ++--------------
target/arm/machine.c | 15 ---------------
49 files changed, 75 insertions(+), 102 deletions(-)
diff --git a/hw/arm/aspeed_ast1040_evb.c b/hw/arm/aspeed_ast1040_evb.c
index 0b52612432e..a15c8a15335 100644
--- a/hw/arm/aspeed_ast1040_evb.c
+++ b/hw/arm/aspeed_ast1040_evb.c
@@ -82,7 +82,7 @@ static const TypeInfo aspeed_ast1040_evb_types[] = {
.name = MACHINE_TYPE_NAME("ast1040-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast1040_evb_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast10x0_evb.c b/hw/arm/aspeed_ast10x0_evb.c
index ed858a35b52..8dff7d54f31 100644
--- a/hw/arm/aspeed_ast10x0_evb.c
+++ b/hw/arm/aspeed_ast10x0_evb.c
@@ -121,12 +121,12 @@ static const TypeInfo aspeed_ast10x0_evb_types[] = {
.name = MACHINE_TYPE_NAME("ast1030-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}, {
.name = MACHINE_TYPE_NAME("ast1060-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1060_evb_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2400_palmetto.c b/hw/arm/aspeed_ast2400_palmetto.c
index b3dcb559b4e..36bed532328 100644
--- a/hw/arm/aspeed_ast2400_palmetto.c
+++ b/hw/arm/aspeed_ast2400_palmetto.c
@@ -74,7 +74,7 @@ static const TypeInfo aspeed_ast2400_palmetto_types[] = {
.name = MACHINE_TYPE_NAME("palmetto-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_palmetto_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2400_quanta-q71l.c b/hw/arm/aspeed_ast2400_quanta-q71l.c
index 04d5445bae6..b8d0510a7bb 100644
--- a/hw/arm/aspeed_ast2400_quanta-q71l.c
+++ b/hw/arm/aspeed_ast2400_quanta-q71l.c
@@ -80,7 +80,7 @@ static const TypeInfo aspeed_ast2400_quanta_q71l_types[] = {
.name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_quanta_q71l_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2400_supermicrox11.c b/hw/arm/aspeed_ast2400_supermicrox11.c
index ab16ffa4e3a..485d747f27f 100644
--- a/hw/arm/aspeed_ast2400_supermicrox11.c
+++ b/hw/arm/aspeed_ast2400_supermicrox11.c
@@ -75,7 +75,7 @@ static const TypeInfo aspeed_ast2400_supermicrox11_types[] = {
.name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_supermicrox11_bmc_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2500_evb.c b/hw/arm/aspeed_ast2500_evb.c
index 76b1d8dc5cf..10f52279425 100644
--- a/hw/arm/aspeed_ast2500_evb.c
+++ b/hw/arm/aspeed_ast2500_evb.c
@@ -61,7 +61,7 @@ static const TypeInfo aspeed_ast2500_evb_types[] = {
.name = MACHINE_TYPE_NAME("ast2500-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2500_evb_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2500_g220a.c b/hw/arm/aspeed_ast2500_g220a.c
index e0ba88c47a5..b0f9649a7cf 100644
--- a/hw/arm/aspeed_ast2500_g220a.c
+++ b/hw/arm/aspeed_ast2500_g220a.c
@@ -86,7 +86,7 @@ static const TypeInfo aspeed_ast2500_g220a_types[] = {
.name = MACHINE_TYPE_NAME("g220a-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_g220a_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2500_romulus.c b/hw/arm/aspeed_ast2500_romulus.c
index 5031539f288..7f926b3a496 100644
--- a/hw/arm/aspeed_ast2500_romulus.c
+++ b/hw/arm/aspeed_ast2500_romulus.c
@@ -56,7 +56,7 @@ static const TypeInfo aspeed_ast2500_romulus_types[] = {
.name = MACHINE_TYPE_NAME("romulus-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_romulus_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2500_supermicro-x11spi.c b/hw/arm/aspeed_ast2500_supermicro-x11spi.c
index b2362d45d8f..2dacb65362f 100644
--- a/hw/arm/aspeed_ast2500_supermicro-x11spi.c
+++ b/hw/arm/aspeed_ast2500_supermicro-x11spi.c
@@ -71,7 +71,7 @@ static const TypeInfo aspeed_ast2500_supermicro_x11spi_types[] = {
.name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2500_tiogapass.c b/hw/arm/aspeed_ast2500_tiogapass.c
index de0129a4991..7fb25532cdc 100644
--- a/hw/arm/aspeed_ast2500_tiogapass.c
+++ b/hw/arm/aspeed_ast2500_tiogapass.c
@@ -84,7 +84,7 @@ static const TypeInfo aspeed_ast2500_tiogapass_types[] = {
.name = MACHINE_TYPE_NAME("tiogapass-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_tiogapass_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2500_witherspoon.c b/hw/arm/aspeed_ast2500_witherspoon.c
index e77bbc6a697..8545f1f97ba 100644
--- a/hw/arm/aspeed_ast2500_witherspoon.c
+++ b/hw/arm/aspeed_ast2500_witherspoon.c
@@ -106,7 +106,7 @@ static const TypeInfo aspeed_ast2500_witherspoon_types[] = {
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_witherspoon_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2500_yosemitev2.c b/hw/arm/aspeed_ast2500_yosemitev2.c
index 3ceda60c0f2..d7a1090ad65 100644
--- a/hw/arm/aspeed_ast2500_yosemitev2.c
+++ b/hw/arm/aspeed_ast2500_yosemitev2.c
@@ -85,7 +85,7 @@ static const TypeInfo aspeed_ast2500_yosemitev2_types[] = {
.name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_yosemitev2_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2600_anacapa.c b/hw/arm/aspeed_ast2600_anacapa.c
index 5ef86e175f7..70d42297287 100644
--- a/hw/arm/aspeed_ast2600_anacapa.c
+++ b/hw/arm/aspeed_ast2600_anacapa.c
@@ -356,7 +356,7 @@ static const TypeInfo aspeed_ast2600_anacapa_types[] = {
.name = MACHINE_TYPE_NAME("anacapa-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_anacapa_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2600_bletchley.c b/hw/arm/aspeed_ast2600_bletchley.c
index e3f3a383113..ba7dd554d7d 100644
--- a/hw/arm/aspeed_ast2600_bletchley.c
+++ b/hw/arm/aspeed_ast2600_bletchley.c
@@ -91,7 +91,7 @@ static const TypeInfo aspeed_ast2600_bletchley_types[] = {
.name = MACHINE_TYPE_NAME("bletchley-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_bletchley_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catalina.c
index 269a2ac8332..e3e540ec0d9 100644
--- a/hw/arm/aspeed_ast2600_catalina.c
+++ b/hw/arm/aspeed_ast2600_catalina.c
@@ -660,7 +660,7 @@ static const TypeInfo aspeed_ast2600_catalina_types[] = {
.name = MACHINE_TYPE_NAME("catalina-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_catalina_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2600_evb.c b/hw/arm/aspeed_ast2600_evb.c
index 4c0dc6b625f..f32a9930e5d 100644
--- a/hw/arm/aspeed_ast2600_evb.c
+++ b/hw/arm/aspeed_ast2600_evb.c
@@ -59,7 +59,7 @@ static const TypeInfo aspeed_ast2600_evb_types[] = {
.name = MACHINE_TYPE_NAME("ast2600-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2600_evb_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2600_fby35.c b/hw/arm/aspeed_ast2600_fby35.c
index bca31e5a0bf..12b52795b6e 100644
--- a/hw/arm/aspeed_ast2600_fby35.c
+++ b/hw/arm/aspeed_ast2600_fby35.c
@@ -172,7 +172,7 @@ static const TypeInfo aspeed_ast2600_fby35_types[] = {
.name = MACHINE_TYPE_NAME("fby35-bmc"),
.parent = MACHINE_TYPE_NAME("ast2600-evb"),
.class_init = aspeed_machine_fby35_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2600_fuji.c b/hw/arm/aspeed_ast2600_fuji.c
index 2790bee6ca2..eb901686b74 100644
--- a/hw/arm/aspeed_ast2600_fuji.c
+++ b/hw/arm/aspeed_ast2600_fuji.c
@@ -134,7 +134,7 @@ static const TypeInfo aspeed_ast2600_fuji_types[] = {
.name = MACHINE_TYPE_NAME("fuji-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_fuji_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2600_gb200nvl.c b/hw/arm/aspeed_ast2600_gb200nvl.c
index 5286d03428c..27cd80509b0 100644
--- a/hw/arm/aspeed_ast2600_gb200nvl.c
+++ b/hw/arm/aspeed_ast2600_gb200nvl.c
@@ -105,7 +105,7 @@ static const TypeInfo aspeed_ast2600_gb200nvl_types[] = {
.name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_gb200nvl_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast2600_rainier.c b/hw/arm/aspeed_ast2600_rainier.c
index 189cc4d2560..8e18d710e75 100644
--- a/hw/arm/aspeed_ast2600_rainier.c
+++ b/hw/arm/aspeed_ast2600_rainier.c
@@ -192,7 +192,7 @@ static const TypeInfo aspeed_ast2600_rainier_types[] = {
.name = MACHINE_TYPE_NAME("rainier-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_rainier_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 8915bfbc6fa..4c11c0fbf3e 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -223,7 +223,7 @@ static const TypeInfo ast2700fc_types[] = {
.parent = TYPE_MACHINE,
.class_init = ast2700fc_class_init,
.instance_size = sizeof(Ast2700FCState),
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
},
};
diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c
index 8a1b2b22fae..eb2b52a9b0b 100644
--- a/hw/arm/aspeed_ast27x0_evb.c
+++ b/hw/arm/aspeed_ast27x0_evb.c
@@ -78,13 +78,13 @@ static const TypeInfo aspeed_ast27x0_evb_types[] = {
.name = MACHINE_TYPE_NAME("ast2700a1-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a1_evb_class_init,
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
},
{
.name = MACHINE_TYPE_NAME("ast2700a2-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a2_evb_class_init,
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index d31ad5d9e04..aa626aa1e58 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -133,7 +133,7 @@ static const TypeInfo bl475e_machine_type[] = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(Bl475eMachineState),
.class_init = bl475e_machine_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 99482fb425f..ace8f908703 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -88,7 +88,7 @@ static const TypeInfo collie_machine_typeinfo = {
.parent = TYPE_MACHINE,
.class_init = collie_machine_class_init,
.instance_size = sizeof(CollieMachineState),
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void collie_machine_register_types(void)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index 2caeb420246..8007ac8e76e 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -174,7 +174,7 @@ static const TypeInfo nuri_type = {
.name = MACHINE_TYPE_NAME("nuri"),
.parent = TYPE_MACHINE,
.class_init = nuri_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void smdkc210_class_init(ObjectClass *oc, const void *data)
@@ -196,7 +196,7 @@ static const TypeInfo smdkc210_type = {
.name = MACHINE_TYPE_NAME("smdkc210"),
.parent = TYPE_MACHINE,
.class_init = smdkc210_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void exynos4_machines_init(void)
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c
index 897f1b91d0a..b37a76e1529 100644
--- a/hw/arm/imx8mp-evk.c
+++ b/hw/arm/imx8mp-evk.c
@@ -163,7 +163,7 @@ static const TypeInfo imx8mp_evk_machine_types[] = {
.class_init = imx8mp_evk_machine_class_init,
.instance_init = imx8mp_evk_machine_init,
.instance_size = sizeof(FslImx8mpEvkState),
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
},
};
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 50d561aa246..bd93c3f7798 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -76,7 +76,7 @@ static const TypeInfo microbit_info = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(MicrobitMachineState),
.class_init = microbit_machine_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void microbit_machine_init(void)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 91e66f82b69..fb857209659 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -1468,28 +1468,28 @@ static const TypeInfo mps2tz_an505_info = {
.name = TYPE_MPS2TZ_AN505_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps2tz_an505_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static const TypeInfo mps2tz_an521_info = {
.name = TYPE_MPS2TZ_AN521_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps2tz_an521_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static const TypeInfo mps3tz_an524_info = {
.name = TYPE_MPS3TZ_AN524_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps3tz_an524_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static const TypeInfo mps3tz_an547_info = {
.name = TYPE_MPS3TZ_AN547_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps3tz_an547_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void mps2tz_machine_init(void)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 55fd22a85d2..5249248eb52 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -572,28 +572,28 @@ static const TypeInfo mps2_an385_info = {
.name = TYPE_MPS2_AN385_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an385_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static const TypeInfo mps2_an386_info = {
.name = TYPE_MPS2_AN386_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an386_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static const TypeInfo mps2_an500_info = {
.name = TYPE_MPS2_AN500_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an500_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static const TypeInfo mps2_an511_info = {
.name = TYPE_MPS2_AN511_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an511_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void mps2_machine_init(void)
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index 687f74f9ec0..6b7392769b0 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -636,7 +636,7 @@ static const TypeInfo mps3r_machine_types[] = {
.name = TYPE_MPS3R_AN536_MACHINE,
.parent = TYPE_MPS3R_MACHINE,
.class_init = mps3r_an536_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
},
};
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index e6736efa8dd..20acc80b378 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -660,14 +660,14 @@ static const TypeInfo musca_a_info = {
.name = TYPE_MUSCA_A_MACHINE,
.parent = TYPE_MUSCA_MACHINE,
.class_init = musca_a_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static const TypeInfo musca_b1_info = {
.name = TYPE_MUSCA_B1_MACHINE,
.parent = TYPE_MUSCA_MACHINE,
.class_init = musca_b1_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void musca_machine_init(void)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 573180f873a..6237cd050d9 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -555,27 +555,27 @@ static const TypeInfo npcm7xx_machine_types[] = {
.name = MACHINE_TYPE_NAME("npcm750-evb"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = npcm750_evb_machine_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}, {
.name = MACHINE_TYPE_NAME("quanta-gsj"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = gsj_machine_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}, {
.name = MACHINE_TYPE_NAME("quanta-gbs-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = gbs_bmc_machine_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}, {
.name = MACHINE_TYPE_NAME("kudo-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = kudo_bmc_machine_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}, {
.name = MACHINE_TYPE_NAME("mori-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = mori_bmc_machine_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
},
};
diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
index c8335091a7e..132b10961ee 100644
--- a/hw/arm/npcm8xx_boards.c
+++ b/hw/arm/npcm8xx_boards.c
@@ -250,7 +250,7 @@ static const TypeInfo npcm8xx_machine_types[] = {
.name = MACHINE_TYPE_NAME("npcm845-evb"),
.parent = TYPE_NPCM8XX_MACHINE,
.class_init = npcm845_evb_machine_class_init,
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
},
};
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index 59670d31af8..475ec4007a0 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -221,7 +221,7 @@ static const TypeInfo sx1_machine_v2_type = {
.name = MACHINE_TYPE_NAME("sx1"),
.parent = TYPE_MACHINE,
.class_init = sx1_machine_v2_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void sx1_machine_v1_class_init(ObjectClass *oc, const void *data)
@@ -242,7 +242,7 @@ static const TypeInfo sx1_machine_v1_type = {
.name = MACHINE_TYPE_NAME("sx1-v1"),
.parent = TYPE_MACHINE,
.class_init = sx1_machine_v1_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void sx1_machine_init(void)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index e0e597d55ef..71f2493bcb9 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -397,27 +397,27 @@ static const TypeInfo raspi_machine_types[] = {
.name = MACHINE_TYPE_NAME("raspi0"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi0_machine_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}, {
.name = MACHINE_TYPE_NAME("raspi1ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi1ap_machine_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}, {
.name = MACHINE_TYPE_NAME("raspi2b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
}, {
.name = MACHINE_TYPE_NAME("raspi3ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3ap_machine_class_init,
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
}, {
.name = MACHINE_TYPE_NAME("raspi3b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3b_machine_class_init,
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
}, {
.name = TYPE_RASPI_MACHINE,
.parent = TYPE_RASPI_BASE_MACHINE,
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index c8a2463ec8d..515f6296ca3 100644
--- a/hw/arm/raspi4b.c
+++ b/hw/arm/raspi4b.c
@@ -127,7 +127,7 @@ static const TypeInfo raspi4b_machine_type = {
.parent = TYPE_RASPI_BASE_MACHINE,
.instance_size = sizeof(Raspi4bMachineState),
.class_init = raspi4b_machine_class_init,
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void raspi4b_machine_register_type(void)
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 005f737b68c..1319316a56f 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -432,7 +432,7 @@ static const TypeInfo realview_eb_type = {
.name = MACHINE_TYPE_NAME("realview-eb"),
.parent = TYPE_MACHINE,
.class_init = realview_eb_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void realview_eb_mpcore_class_init(ObjectClass *oc, const void *data)
@@ -455,7 +455,7 @@ static const TypeInfo realview_eb_mpcore_type = {
.name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
.parent = TYPE_MACHINE,
.class_init = realview_eb_mpcore_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void realview_pb_a8_class_init(ObjectClass *oc, const void *data)
@@ -476,7 +476,7 @@ static const TypeInfo realview_pb_a8_type = {
.name = MACHINE_TYPE_NAME("realview-pb-a8"),
.parent = TYPE_MACHINE,
.class_init = realview_pb_a8_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void realview_pbx_a9_class_init(ObjectClass *oc, const void *data)
@@ -498,7 +498,7 @@ static const TypeInfo realview_pbx_a9_type = {
.name = MACHINE_TYPE_NAME("realview-pbx-a9"),
.parent = TYPE_MACHINE,
.class_init = realview_pbx_a9_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void realview_machine_init(void)
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index 4ea4cda36ee..e48eb10b2d2 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -155,7 +155,7 @@ static const TypeInfo sabrelite_machine_init_typeinfo = {
.instance_init = sabrelite_machine_instance_init,
.instance_size = sizeof(SabreliteMachineState),
.abstract = false,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void sabrelite_machine_init_register_types(void)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 5608263a810..2879aca8818 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -945,7 +945,7 @@ static const TypeInfo sbsa_ref_info = {
.instance_finalize = sbsa_ref_instance_finalize,
.class_init = sbsa_ref_class_init,
.instance_size = sizeof(SBSAMachineState),
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void sbsa_ref_machine_init(void)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 4b7dc5c45a3..9bae6325501 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1429,7 +1429,7 @@ static const TypeInfo lm3s811evb_type = {
.name = MACHINE_TYPE_NAME("lm3s811evb"),
.parent = TYPE_MACHINE,
.class_init = lm3s811evb_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
/*
@@ -1452,7 +1452,7 @@ static const TypeInfo lm3s6965evb_type = {
.name = MACHINE_TYPE_NAME("lm3s6965evb"),
.parent = TYPE_MACHINE,
.class_init = lm3s6965evb_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void stellaris_machine_init(void)
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 3437e014cd4..0c84669236a 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -432,7 +432,7 @@ static const TypeInfo versatilepb_type = {
.name = MACHINE_TYPE_NAME("versatilepb"),
.parent = TYPE_MACHINE,
.class_init = versatilepb_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void versatileab_class_init(ObjectClass *oc, const void *data)
@@ -455,7 +455,7 @@ static const TypeInfo versatileab_type = {
.name = MACHINE_TYPE_NAME("versatileab"),
.parent = TYPE_MACHINE,
.class_init = versatileab_class_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void versatile_machine_init(void)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 13d76597893..25b7bbb9b6c 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -852,7 +852,7 @@ static const TypeInfo vexpress_a9_info = {
.parent = TYPE_VEXPRESS_MACHINE,
.class_init = vexpress_a9_class_init,
.instance_init = vexpress_a9_instance_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static const TypeInfo vexpress_a15_info = {
@@ -860,7 +860,7 @@ static const TypeInfo vexpress_a15_info = {
.parent = TYPE_VEXPRESS_MACHINE,
.class_init = vexpress_a15_class_init,
.instance_init = vexpress_a15_instance_init,
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void vexpress_machine_init(void)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index f55366b4d07..e6d44cf25fd 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -134,7 +134,7 @@ static void arm_virt_compat_default_set(MachineClass *mc)
.name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
.parent = TYPE_VIRT_MACHINE, \
.class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
- .interfaces = arm_aarch64_machine_interfaces, \
+ .interfaces = type_target_specific, \
}; \
static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
{ \
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index fd83fa5f541..6ac4fc16602 100644
--- a/hw/arm/xen-pvh.c
+++ b/hw/arm/xen-pvh.c
@@ -97,7 +97,7 @@ static const TypeInfo xen_arm_machine_type = {
.class_init = xen_arm_machine_class_init,
.instance_size = sizeof(XenPVHMachineState),
.instance_init = xen_arm_instance_init,
- .interfaces = arm_aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void xen_arm_machine_register_types(void)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 6861fe91774..6b6bf37fdec 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -481,7 +481,7 @@ static const TypeInfo zynq_machine_type = {
.parent = TYPE_MACHINE,
.class_init = zynq_machine_class_init,
.instance_size = sizeof(ZynqMachineState),
- .interfaces = arm_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void zynq_machine_register_types(void)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index c40b8376947..b08682f1e9e 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -404,14 +404,14 @@ static const TypeInfo versal_virt_machine_init_typeinfo = {
.name = TYPE_XLNX_VERSAL_VIRT_MACHINE,
.parent = TYPE_XLNX_VERSAL_VIRT_BASE_MACHINE,
.class_init = versal_virt_machine_class_init,
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static const TypeInfo versal2_virt_machine_init_typeinfo = {
.name = TYPE_XLNX_VERSAL2_VIRT_MACHINE,
.parent = TYPE_XLNX_VERSAL_VIRT_BASE_MACHINE,
.class_init = versal2_virt_machine_class_init,
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void versal_virt_machine_init_register_types(void)
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index ff98827f83a..b3383a2bb83 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -304,7 +304,7 @@ static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
.class_init = xlnx_zcu102_machine_class_init,
.instance_init = xlnx_zcu102_machine_instance_init,
.instance_size = sizeof(XlnxZCU102),
- .interfaces = aarch64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void xlnx_zcu102_machine_init_register_types(void)
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
index 91b2c57c6d2..f4d9a163220 100644
--- a/include/hw/arm/machines-qom.h
+++ b/include/hw/arm/machines-qom.h
@@ -13,18 +13,6 @@
#include "qemu/target-info.h"
#include "qemu/target-info-qom.h"
-/*
- * A machine filtered with arm_machine_interfaces[] or
- * arm_aarch64_machine_interfaces[] will be available
- * in both qemu-system-arm and qemu-system-aarch64 binaries.
- *
- * One filtered with aarch64_machine_interfaces[] will only
- * be available in the qemu-system-aarch64 binary.
- */
-extern const InterfaceInfo arm_machine_interfaces[];
-extern const InterfaceInfo arm_aarch64_machine_interfaces[];
-extern const InterfaceInfo aarch64_machine_interfaces[];
-
/*
* A machine defined with the DEFINE_MACHINE_ARM() macro will be
* available in both qemu-system-arm and qemu-system-aarch64 binaries.
@@ -34,9 +22,9 @@ extern const InterfaceInfo aarch64_machine_interfaces[];
*/
#define DEFINE_MACHINE_ARM(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- arm_machine_interfaces)
+ type_target_specific)
#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- aarch64_machine_interfaces)
+ type_target_specific)
#endif
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 8f0d927ab63..b5eeb586007 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -1347,18 +1347,3 @@ const VMStateDescription vmstate_arm_cpu = {
NULL
}
};
-
-const InterfaceInfo arm_machine_interfaces[] = {
- { TYPE_TARGET_SPECIFIC },
- { }
-};
-
-const InterfaceInfo arm_aarch64_machine_interfaces[] = {
- { TYPE_TARGET_SPECIFIC },
- { }
-};
-
-const InterfaceInfo aarch64_machine_interfaces[] = {
- { TYPE_TARGET_SPECIFIC },
- { }
-};
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 19/27] include/hw/core/boards.h: add DEFINE_MACHINE_TARGET_SPECIFIC
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (17 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 18/27] hw/arm: remove {arm, arm_aarch64, aarch64}_machine_interfaces Pierrick Bouvier via qemu development
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 20/27] hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM} Pierrick Bouvier
` (9 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
include/hw/core/boards.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/hw/core/boards.h b/include/hw/core/boards.h
index 29c68931d8a..c963e956157 100644
--- a/include/hw/core/boards.h
+++ b/include/hw/core/boards.h
@@ -8,6 +8,7 @@
#include "system/blockdev.h"
#include "qapi/qapi-types-machine.h"
#include "qemu/module.h"
+#include "qemu/target-info-qom.h"
#include "qom/compat-properties.h"
#include "qom/object.h"
#include "hw/core/cpu.h"
@@ -546,6 +547,9 @@ struct MachineState {
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
(const InterfaceInfo[]) { __VA_ARGS__ })
+#define DEFINE_MACHINE_TARGET_SPECIFIC(namestr, machine_initfn) \
+ DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
+ type_target_specific)
/*
* Helper for dispatching different macros based on how
* many __VA_ARGS__ are passed. Supports 1 to 5 variadic
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 20/27] hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM}
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (18 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 19/27] include/hw/core/boards.h: add DEFINE_MACHINE_TARGET_SPECIFIC Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 21/27] hw/arm: remove machines-qom.h Pierrick Bouvier
` (8 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/arm/bananapi_m2u.c | 2 +-
hw/arm/cubieboard.c | 2 +-
hw/arm/digic_boards.c | 2 +-
hw/arm/imx25_pdk.c | 2 +-
hw/arm/imx8mm-evk.c | 2 +-
hw/arm/integratorcp.c | 2 +-
hw/arm/kzm.c | 2 +-
hw/arm/max78000fthr.c | 2 +-
hw/arm/mcimx6ul-evk.c | 2 +-
hw/arm/mcimx7d-sabre.c | 2 +-
hw/arm/msf2-som.c | 2 +-
hw/arm/musicpal.c | 2 +-
hw/arm/netduino2.c | 2 +-
hw/arm/netduinoplus2.c | 2 +-
hw/arm/olimex-stm32-h405.c | 2 +-
hw/arm/orangepi.c | 2 +-
hw/arm/stm32vldiscovery.c | 2 +-
include/hw/arm/machines-qom.h | 14 --------------
18 files changed, 17 insertions(+), 31 deletions(-)
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index 4fb19a83657..b96268ef0f3 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -146,4 +146,4 @@ static void bpim2u_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE_ARM("bpim2u", bpim2u_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("bpim2u", bpim2u_machine_init)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 234c1ea37fc..b80cd4ade7a 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -127,4 +127,4 @@ static void cubieboard_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE_ARM("cubieboard", cubieboard_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("cubieboard", cubieboard_machine_init)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index fbcabaa3362..1210a6a888e 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -147,4 +147,4 @@ static void canon_a1100_machine_init(MachineClass *mc)
mc->default_ram_id = "ram";
}
-DEFINE_MACHINE_ARM("canon-a1100", canon_a1100_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("canon-a1100", canon_a1100_machine_init)
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index e60a7e672a4..b9113ee983a 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -152,4 +152,4 @@ static void imx25_pdk_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE_ARM("imx25-pdk", imx25_pdk_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("imx25-pdk", imx25_pdk_machine_init)
diff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c
index 031f9348626..f660015e207 100644
--- a/hw/arm/imx8mm-evk.c
+++ b/hw/arm/imx8mm-evk.c
@@ -128,4 +128,4 @@ static void imx8mm_evk_machine_init(MachineClass *mc)
mc->get_default_cpu_type = imx8mm_evk_get_default_cpu_type;
}
-DEFINE_MACHINE_AARCH64("imx8mm-evk", imx8mm_evk_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("imx8mm-evk", imx8mm_evk_machine_init)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index cf95c3f57d4..489afdaf163 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -697,7 +697,7 @@ static void integratorcp_machine_init(MachineClass *mc)
machine_add_audiodev_property(mc);
}
-DEFINE_MACHINE_ARM("integratorcp", integratorcp_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("integratorcp", integratorcp_machine_init)
static const Property core_properties[] = {
DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index b49841ca87a..b97ef4c932c 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -141,4 +141,4 @@ static void kzm_machine_init(MachineClass *mc)
mc->default_ram_id = "kzm.ram";
}
-DEFINE_MACHINE_ARM("kzm", kzm_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("kzm", kzm_machine_init)
diff --git a/hw/arm/max78000fthr.c b/hw/arm/max78000fthr.c
index 4453868e562..a39cb001ce2 100644
--- a/hw/arm/max78000fthr.c
+++ b/hw/arm/max78000fthr.c
@@ -49,4 +49,4 @@ static void max78000_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE_ARM("max78000fthr", max78000_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("max78000fthr", max78000_machine_init)
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index 299e797fd48..cbd41056522 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -79,4 +79,4 @@ static void mcimx6ul_evk_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE_ARM("mcimx6ul-evk", mcimx6ul_evk_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("mcimx6ul-evk", mcimx6ul_evk_machine_init)
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index a94218ac1b1..f4e31407fe5 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -79,4 +79,4 @@ static void mcimx7d_sabre_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE_ARM("mcimx7d-sabre", mcimx7d_sabre_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("mcimx7d-sabre", mcimx7d_sabre_machine_init)
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 44c68bffac6..67d7a8d00de 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -110,4 +110,4 @@ static void emcraft_sf2_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE_ARM("emcraft-sf2", emcraft_sf2_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("emcraft-sf2", emcraft_sf2_machine_init)
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index d9aeb98b6f0..a3f98ca95a2 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -1358,7 +1358,7 @@ static void musicpal_machine_init(MachineClass *mc)
machine_add_audiodev_property(mc);
}
-DEFINE_MACHINE_ARM("musicpal", musicpal_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("musicpal", musicpal_machine_init)
static void mv88w8618_wlan_class_init(ObjectClass *klass, const void *data)
{
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index a721da02ce0..d9b74b9065a 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -67,4 +67,4 @@ static void netduino2_machine_init(MachineClass *mc)
mc->ignore_memory_transaction_failures = true;
}
-DEFINE_MACHINE_ARM("netduino2", netduino2_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("netduino2", netduino2_machine_init)
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index ee5f1679426..c0ef997184c 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -67,4 +67,4 @@ static void netduinoplus2_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE_ARM("netduinoplus2", netduinoplus2_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("netduinoplus2", netduinoplus2_machine_init)
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index 58a124d3c06..9dbae8238b3 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -73,4 +73,4 @@ static void olimex_stm32_h405_machine_init(MachineClass *mc)
mc->default_ram_size = 0;
}
-DEFINE_MACHINE_ARM("olimex-stm32-h405", olimex_stm32_h405_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("olimex-stm32-h405", olimex_stm32_h405_machine_init)
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 53366a76334..9cfc1e077e9 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -126,4 +126,4 @@ static void orangepi_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE_ARM("orangepi-pc", orangepi_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("orangepi-pc", orangepi_machine_init)
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 53b4632c013..b87b57da61c 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -70,4 +70,4 @@ static void stm32vldiscovery_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE_ARM("stm32vldiscovery", stm32vldiscovery_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("stm32vldiscovery", stm32vldiscovery_machine_init)
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
index f4d9a163220..f64de7bfc8d 100644
--- a/include/hw/arm/machines-qom.h
+++ b/include/hw/arm/machines-qom.h
@@ -13,18 +13,4 @@
#include "qemu/target-info.h"
#include "qemu/target-info-qom.h"
-/*
- * A machine defined with the DEFINE_MACHINE_ARM() macro will be
- * available in both qemu-system-arm and qemu-system-aarch64 binaries.
- *
- * One defined with DEFINE_MACHINE_AARCH64() will only be available in
- * the qemu-system-aarch64 binary.
- */
-#define DEFINE_MACHINE_ARM(namestr, machine_initfn) \
- DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- type_target_specific)
-#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
- DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- type_target_specific)
-
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 21/27] hw/arm: remove machines-qom.h
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (19 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 20/27] hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM} Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 22/27] hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE Pierrick Bouvier
` (7 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
configs/targets/aarch64-softmmu.c | 1 -
configs/targets/arm-softmmu.c | 1 -
hw/arm/aspeed.c | 1 -
hw/arm/aspeed_ast1040_evb.c | 1 -
hw/arm/aspeed_ast10x0_evb.c | 1 -
hw/arm/aspeed_ast2400_palmetto.c | 1 -
hw/arm/aspeed_ast2400_quanta-q71l.c | 1 -
hw/arm/aspeed_ast2400_supermicrox11.c | 1 -
hw/arm/aspeed_ast2500_evb.c | 1 -
hw/arm/aspeed_ast2500_g220a.c | 1 -
hw/arm/aspeed_ast2500_romulus.c | 1 -
hw/arm/aspeed_ast2500_supermicro-x11spi.c | 1 -
hw/arm/aspeed_ast2500_tiogapass.c | 1 -
hw/arm/aspeed_ast2500_witherspoon.c | 1 -
hw/arm/aspeed_ast2500_yosemitev2.c | 1 -
hw/arm/aspeed_ast2600_anacapa.c | 1 -
hw/arm/aspeed_ast2600_bletchley.c | 1 -
hw/arm/aspeed_ast2600_catalina.c | 1 -
hw/arm/aspeed_ast2600_evb.c | 1 -
hw/arm/aspeed_ast2600_fby35.c | 1 -
hw/arm/aspeed_ast2600_fuji.c | 1 -
hw/arm/aspeed_ast2600_gb200nvl.c | 1 -
hw/arm/aspeed_ast2600_rainier.c | 1 -
hw/arm/aspeed_ast27x0-fc.c | 1 -
hw/arm/aspeed_ast27x0_evb.c | 1 -
hw/arm/b-l475e-iot01a.c | 1 -
hw/arm/bananapi_m2u.c | 1 -
hw/arm/collie.c | 1 -
hw/arm/cubieboard.c | 1 -
hw/arm/digic_boards.c | 1 -
hw/arm/exynos4_boards.c | 1 -
hw/arm/imx25_pdk.c | 1 -
hw/arm/imx8mm-evk.c | 1 -
hw/arm/imx8mp-evk.c | 1 -
hw/arm/integratorcp.c | 1 -
hw/arm/kzm.c | 1 -
hw/arm/max78000fthr.c | 1 -
hw/arm/mcimx6ul-evk.c | 1 -
hw/arm/mcimx7d-sabre.c | 1 -
hw/arm/microbit.c | 1 -
hw/arm/mps2-tz.c | 1 -
hw/arm/mps2.c | 1 -
hw/arm/mps3r.c | 1 -
hw/arm/msf2-som.c | 1 -
hw/arm/musca.c | 1 -
hw/arm/musicpal.c | 1 -
hw/arm/netduino2.c | 1 -
hw/arm/netduinoplus2.c | 1 -
hw/arm/npcm7xx_boards.c | 1 -
hw/arm/npcm8xx_boards.c | 1 -
hw/arm/olimex-stm32-h405.c | 1 -
hw/arm/omap_sx1.c | 1 -
hw/arm/orangepi.c | 1 -
hw/arm/raspi.c | 1 -
hw/arm/raspi4b.c | 1 -
hw/arm/realview.c | 1 -
hw/arm/sabrelite.c | 1 -
hw/arm/sbsa-ref.c | 1 -
hw/arm/stellaris.c | 1 -
hw/arm/stm32vldiscovery.c | 1 -
hw/arm/versatilepb.c | 1 -
hw/arm/vexpress.c | 1 -
hw/arm/virt.c | 1 -
hw/arm/xen-pvh.c | 1 -
hw/arm/xilinx_zynq.c | 1 -
hw/arm/xlnx-versal-virt.c | 1 -
hw/arm/xlnx-zcu102.c | 1 -
hw/core/null-machine.c | 1 -
hw/nitro/machine.c | 1 -
hw/remote/machine.c | 1 -
include/hw/arm/machines-qom.h | 16 ----------------
target-info-qom.c | 1 -
target/arm/machine.c | 1 -
73 files changed, 88 deletions(-)
delete mode 100644 include/hw/arm/machines-qom.h
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
index 381a9f686a5..9efeb366e3b 100644
--- a/configs/targets/aarch64-softmmu.c
+++ b/configs/targets/aarch64-softmmu.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
-#include "hw/arm/machines-qom.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/cpu-param.h"
#ifndef CONFIG_USER_ONLY
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
index 4f946708864..8785ea01824 100644
--- a/configs/targets/arm-softmmu.c
+++ b/configs/targets/arm-softmmu.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
-#include "hw/arm/machines-qom.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/cpu-param.h"
#ifndef CONFIG_USER_ONLY
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index a48c4420583..fc57ad168a9 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -14,7 +14,6 @@
#include "hw/arm/boot.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/gpio/pca9552.h"
#include "hw/gpio/pca9554.h"
diff --git a/hw/arm/aspeed_ast1040_evb.c b/hw/arm/aspeed_ast1040_evb.c
index a15c8a15335..4a31c1a3261 100644
--- a/hw/arm/aspeed_ast1040_evb.c
+++ b/hw/arm/aspeed_ast1040_evb.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/core/qdev-clock.h"
diff --git a/hw/arm/aspeed_ast10x0_evb.c b/hw/arm/aspeed_ast10x0_evb.c
index 8dff7d54f31..f7048a260b6 100644
--- a/hw/arm/aspeed_ast10x0_evb.c
+++ b/hw/arm/aspeed_ast10x0_evb.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/core/qdev-clock.h"
diff --git a/hw/arm/aspeed_ast2400_palmetto.c b/hw/arm/aspeed_ast2400_palmetto.c
index 36bed532328..6521cac69c9 100644
--- a/hw/arm/aspeed_ast2400_palmetto.c
+++ b/hw/arm/aspeed_ast2400_palmetto.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2400_quanta-q71l.c b/hw/arm/aspeed_ast2400_quanta-q71l.c
index b8d0510a7bb..0f7a7e8d29e 100644
--- a/hw/arm/aspeed_ast2400_quanta-q71l.c
+++ b/hw/arm/aspeed_ast2400_quanta-q71l.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
diff --git a/hw/arm/aspeed_ast2400_supermicrox11.c b/hw/arm/aspeed_ast2400_supermicrox11.c
index 485d747f27f..ba603977a3b 100644
--- a/hw/arm/aspeed_ast2400_supermicrox11.c
+++ b/hw/arm/aspeed_ast2400_supermicrox11.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2500_evb.c b/hw/arm/aspeed_ast2500_evb.c
index 10f52279425..d278bc996ec 100644
--- a/hw/arm/aspeed_ast2500_evb.c
+++ b/hw/arm/aspeed_ast2500_evb.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2500_g220a.c b/hw/arm/aspeed_ast2500_g220a.c
index b0f9649a7cf..4c33de3838f 100644
--- a/hw/arm/aspeed_ast2500_g220a.c
+++ b/hw/arm/aspeed_ast2500_g220a.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2500_romulus.c b/hw/arm/aspeed_ast2500_romulus.c
index 7f926b3a496..a6385ea0ccf 100644
--- a/hw/arm/aspeed_ast2500_romulus.c
+++ b/hw/arm/aspeed_ast2500_romulus.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
diff --git a/hw/arm/aspeed_ast2500_supermicro-x11spi.c b/hw/arm/aspeed_ast2500_supermicro-x11spi.c
index 2dacb65362f..c44b55da1e8 100644
--- a/hw/arm/aspeed_ast2500_supermicro-x11spi.c
+++ b/hw/arm/aspeed_ast2500_supermicro-x11spi.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2500_tiogapass.c b/hw/arm/aspeed_ast2500_tiogapass.c
index 7fb25532cdc..09cba4896b6 100644
--- a/hw/arm/aspeed_ast2500_tiogapass.c
+++ b/hw/arm/aspeed_ast2500_tiogapass.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/nvram/eeprom_at24c.h"
diff --git a/hw/arm/aspeed_ast2500_witherspoon.c b/hw/arm/aspeed_ast2500_witherspoon.c
index 8545f1f97ba..d263d0e5b6c 100644
--- a/hw/arm/aspeed_ast2500_witherspoon.c
+++ b/hw/arm/aspeed_ast2500_witherspoon.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/misc/led.h"
diff --git a/hw/arm/aspeed_ast2500_yosemitev2.c b/hw/arm/aspeed_ast2500_yosemitev2.c
index d7a1090ad65..34b249b5933 100644
--- a/hw/arm/aspeed_ast2500_yosemitev2.c
+++ b/hw/arm/aspeed_ast2500_yosemitev2.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/nvram/eeprom_at24c.h"
diff --git a/hw/arm/aspeed_ast2600_anacapa.c b/hw/arm/aspeed_ast2600_anacapa.c
index 70d42297287..9ecc12b40b5 100644
--- a/hw/arm/aspeed_ast2600_anacapa.c
+++ b/hw/arm/aspeed_ast2600_anacapa.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/i2c_mux_pca954x.h"
diff --git a/hw/arm/aspeed_ast2600_bletchley.c b/hw/arm/aspeed_ast2600_bletchley.c
index ba7dd554d7d..42b4f048dde 100644
--- a/hw/arm/aspeed_ast2600_bletchley.c
+++ b/hw/arm/aspeed_ast2600_bletchley.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/gpio/pca9552.h"
diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catalina.c
index e3e540ec0d9..fe43b39a51a 100644
--- a/hw/arm/aspeed_ast2600_catalina.c
+++ b/hw/arm/aspeed_ast2600_catalina.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/i2c_mux_pca954x.h"
diff --git a/hw/arm/aspeed_ast2600_evb.c b/hw/arm/aspeed_ast2600_evb.c
index f32a9930e5d..e11c4cc6a2c 100644
--- a/hw/arm/aspeed_ast2600_evb.c
+++ b/hw/arm/aspeed_ast2600_evb.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2600_fby35.c b/hw/arm/aspeed_ast2600_fby35.c
index 12b52795b6e..2907dd94076 100644
--- a/hw/arm/aspeed_ast2600_fby35.c
+++ b/hw/arm/aspeed_ast2600_fby35.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/nvram/eeprom_at24c.h"
diff --git a/hw/arm/aspeed_ast2600_fuji.c b/hw/arm/aspeed_ast2600_fuji.c
index eb901686b74..fe11aef9a51 100644
--- a/hw/arm/aspeed_ast2600_fuji.c
+++ b/hw/arm/aspeed_ast2600_fuji.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/i2c_mux_pca954x.h"
diff --git a/hw/arm/aspeed_ast2600_gb200nvl.c b/hw/arm/aspeed_ast2600_gb200nvl.c
index 27cd80509b0..57040715695 100644
--- a/hw/arm/aspeed_ast2600_gb200nvl.c
+++ b/hw/arm/aspeed_ast2600_gb200nvl.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/nvram/eeprom_at24c.h"
diff --git a/hw/arm/aspeed_ast2600_rainier.c b/hw/arm/aspeed_ast2600_rainier.c
index 8e18d710e75..0553a6cb600 100644
--- a/hw/arm/aspeed_ast2600_rainier.c
+++ b/hw/arm/aspeed_ast2600_rainier.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/nvram/eeprom_at24c.h"
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 4c11c0fbf3e..f0fd94f33bc 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -22,7 +22,6 @@
#include "hw/arm/boot.h"
#include "hw/block/flash.h"
#include "hw/arm/aspeed_coprocessor.h"
-#include "hw/arm/machines-qom.h"
#define TYPE_AST2700FC MACHINE_TYPE_NAME("ast2700fc")
OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700FC);
diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c
index eb2b52a9b0b..ca255a4787e 100644
--- a/hw/arm/aspeed_ast27x0_evb.c
+++ b/hw/arm/aspeed_ast27x0_evb.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/sensor/tmp105.h"
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index aa626aa1e58..d847f41b9d1 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -29,7 +29,6 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/core/split-irq.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/stm32l4x5_soc.h"
#include "hw/gpio/stm32l4x5_gpio.h"
#include "hw/display/dm163.h"
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index b96268ef0f3..be44c5b955b 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -27,7 +27,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/arm/allwinner-r40.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
static struct arm_boot_info bpim2u_binfo;
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index ace8f908703..332912e9d37 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -15,7 +15,6 @@
#include "hw/core/boards.h"
#include "strongarm.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "system/address-spaces.h"
#include "qom/object.h"
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index b80cd4ade7a..2340a691dd0 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -22,7 +22,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/arm/allwinner-a10.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/i2c/i2c.h"
static struct arm_boot_info cubieboard_binfo = {
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 1210a6a888e..6b6085fc5f2 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -29,7 +29,6 @@
#include "hw/core/boards.h"
#include "qemu/error-report.h"
#include "hw/arm/digic.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/core/loader.h"
#include "system/qtest.h"
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index 8007ac8e76e..0c6dca31efc 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -28,7 +28,6 @@
#include "hw/core/sysbus.h"
#include "net/net.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "system/address-spaces.h"
#include "hw/arm/exynos4210.h"
#include "hw/net/lan9118.h"
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index b9113ee983a..05cc7bc7517 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -28,7 +28,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/arm/fsl-imx25.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "qemu/error-report.h"
#include "system/qtest.h"
diff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c
index f660015e207..9b510e67fff 100644
--- a/hw/arm/imx8mm-evk.c
+++ b/hw/arm/imx8mm-evk.c
@@ -11,7 +11,6 @@
#include "system/address-spaces.h"
#include "hw/arm/boot.h"
#include "hw/arm/fsl-imx8mm.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "system/kvm.h"
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c
index b37a76e1529..bf54f3e40c5 100644
--- a/hw/arm/imx8mp-evk.c
+++ b/hw/arm/imx8mp-evk.c
@@ -10,7 +10,6 @@
#include "system/address-spaces.h"
#include "hw/arm/boot.h"
#include "hw/arm/fsl-imx8mp.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "system/kvm.h"
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 489afdaf163..c10deee12e9 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -13,7 +13,6 @@
#include "migration/vmstate.h"
#include "hw/core/boards.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/misc/arm_integrator_debug.h"
#include "hw/net/smc91c111.h"
#include "net/net.h"
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index b97ef4c932c..6cc72c04632 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -17,7 +17,6 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx31.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "qemu/error-report.h"
#include "system/address-spaces.h"
diff --git a/hw/arm/max78000fthr.c b/hw/arm/max78000fthr.c
index a39cb001ce2..ff5463127f1 100644
--- a/hw/arm/max78000fthr.c
+++ b/hw/arm/max78000fthr.c
@@ -12,7 +12,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/core/qdev-clock.h"
#include "qemu/error-report.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/max78000_soc.h"
#include "hw/arm/boot.h"
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index cbd41056522..c8518d0c5f0 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -14,7 +14,6 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx6ul.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index f4e31407fe5..87a63840627 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -16,7 +16,6 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx7.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index bd93c3f7798..98366a277cf 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -12,7 +12,6 @@
#include "qapi/error.h"
#include "hw/core/boards.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "system/system.h"
#include "system/address-spaces.h"
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index fb857209659..2cf4054c431 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -52,7 +52,6 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/arm/armv7m.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/or-irq.h"
#include "hw/core/boards.h"
#include "system/address-spaces.h"
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 5249248eb52..6cb04645318 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -31,7 +31,6 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/arm/armv7m.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/or-irq.h"
#include "hw/core/boards.h"
#include "system/address-spaces.h"
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index 6b7392769b0..23db8b3f089 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -37,7 +37,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/arm/boot.h"
#include "hw/arm/bsa.h"
-#include "hw/arm/machines-qom.h"
#include "hw/char/cmsdk-apb-uart.h"
#include "hw/i2c/arm_sbcon_i2c.h"
#include "hw/intc/arm_gicv3.h"
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 67d7a8d00de..5d2228b71e7 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -32,7 +32,6 @@
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/qdev-clock.h"
#include "system/address-spaces.h"
#include "hw/arm/msf2-soc.h"
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index 20acc80b378..aa6a05c6008 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -26,7 +26,6 @@
#include "system/system.h"
#include "hw/arm/boot.h"
#include "hw/arm/armsse.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/char/pl011.h"
#include "hw/core/split-irq.h"
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index a3f98ca95a2..ef4357edf64 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -15,7 +15,6 @@
#include "hw/core/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "net/net.h"
#include "system/system.h"
#include "hw/core/boards.h"
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index d9b74b9065a..d5651b5fb8b 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -30,7 +30,6 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f205_soc.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
/* Main SYSCLK frequency in Hz (120MHz) */
#define SYSCLK_FRQ 120000000ULL
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index c0ef997184c..1bc324dbc85 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -30,7 +30,6 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f405_soc.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
/* Main SYSCLK frequency in Hz (168MHz) */
#define SYSCLK_FRQ 168000000ULL
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 6237cd050d9..8242b995fd0 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -17,7 +17,6 @@
#include "qemu/osdep.h"
#include "hw/arm/npcm7xx.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/cpu.h"
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
index 132b10961ee..b88e5cee3fb 100644
--- a/hw/arm/npcm8xx_boards.c
+++ b/hw/arm/npcm8xx_boards.c
@@ -19,7 +19,6 @@
#include "chardev/char.h"
#include "hw/core/boards.h"
#include "hw/arm/npcm8xx.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/cpu.h"
#include "hw/core/loader.h"
#include "hw/core/qdev.h"
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index 9dbae8238b3..0e3d4182b5d 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -31,7 +31,6 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f405_soc.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index 475ec4007a0..7071eb341df 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -32,7 +32,6 @@
#include "hw/arm/omap.h"
#include "hw/core/boards.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "system/qtest.h"
#include "system/address-spaces.h"
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 9cfc1e077e9..c5900eb2a29 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -26,7 +26,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/arm/allwinner-h3.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
static struct arm_boot_info orangepi_binfo;
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 71f2493bcb9..18a2155a025 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -24,7 +24,6 @@
#include "qemu/error-report.h"
#include "hw/core/boards.h"
#include "hw/core/loader.h"
-#include "hw/arm/machines-qom.h"
#include "qom/object.h"
#define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common")
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index 515f6296ca3..16c471846ba 100644
--- a/hw/arm/raspi4b.c
+++ b/hw/arm/raspi4b.c
@@ -11,7 +11,6 @@
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/raspi_platform.h"
#include "hw/display/bcm2835_fb.h"
#include "hw/core/registerfields.h"
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 1319316a56f..a83eb28abeb 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -12,7 +12,6 @@
#include "target/arm/cpu.h"
#include "hw/core/sysbus.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/split-irq.h"
#include "hw/misc/arm_sysctl.h"
#include "hw/net/lan9118.h"
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index e48eb10b2d2..0975f83eaa7 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -14,7 +14,6 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx6.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 2879aca8818..28bf1e30fec 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -35,7 +35,6 @@
#include "hw/arm/bsa.h"
#include "hw/arm/fdt.h"
#include "hw/arm/smmuv3.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/core/boards.h"
#include "hw/ide/ide-bus.h"
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 9bae6325501..a8e914e457a 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -15,7 +15,6 @@
#include "hw/sd/sd.h"
#include "hw/ssi/ssi.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "qemu/timer.h"
#include "hw/i2c/i2c.h"
#include "net/net.h"
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index b87b57da61c..39746a31fa5 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -31,7 +31,6 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f100_soc.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
/* stm32vldiscovery implementation is derived from netduinoplus2 */
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 0c84669236a..922f76bb113 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -12,7 +12,6 @@
#include "hw/core/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/net/smc91c111.h"
#include "net/net.h"
#include "system/system.h"
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 25b7bbb9b6c..a768e6e13a7 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -26,7 +26,6 @@
#include "qemu/datadir.h"
#include "hw/core/sysbus.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/misc/arm_sysctl.h"
#include "hw/net/lan9118.h"
#include "hw/i2c/i2c.h"
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e6d44cf25fd..daba9af79f1 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -37,7 +37,6 @@
#include "hw/core/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/virt.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/display/ramfb.h"
#include "net/net.h"
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index 6ac4fc16602..cc60a2d49d6 100644
--- a/hw/arm/xen-pvh.c
+++ b/hw/arm/xen-pvh.c
@@ -10,7 +10,6 @@
#include "hw/core/boards.h"
#include "system/system.h"
#include "hw/xen/xen-pvh-common.h"
-#include "hw/arm/machines-qom.h"
#define TYPE_XEN_ARM MACHINE_TYPE_NAME("xenpvh")
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 6b6bf37fdec..ca9f074ace6 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -20,7 +20,6 @@
#include "qapi/error.h"
#include "hw/core/sysbus.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "net/net.h"
#include "system/system.h"
#include "hw/core/boards.h"
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index b08682f1e9e..e33a2233313 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -21,7 +21,6 @@
#include "hw/arm/fdt.h"
#include "hw/arm/xlnx-versal.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "qom/object.h"
#include "target/arm/cpu.h"
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index b3383a2bb83..1a418424555 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -19,7 +19,6 @@
#include "qapi/error.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index c1ecf3214fd..2aa748233b3 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -16,7 +16,6 @@
#include "hw/core/boards.h"
#include "system/address-spaces.h"
#include "hw/core/cpu.h"
-#include "hw/arm/machines-qom.h"
#include "hw/riscv/machines-qom.h"
static void machine_none_init(MachineState *mch)
diff --git a/hw/nitro/machine.c b/hw/nitro/machine.c
index 2d001a32fe2..be2b5bc5401 100644
--- a/hw/nitro/machine.c
+++ b/hw/nitro/machine.c
@@ -31,7 +31,6 @@
#include "system/system.h"
#include "system/nitro-accel.h"
#include "qemu/accel.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/eif.h"
#include <zlib.h> /* for crc32 */
diff --git a/hw/remote/machine.c b/hw/remote/machine.c
index 932d14e53e9..188647fd4ed 100644
--- a/hw/remote/machine.c
+++ b/hw/remote/machine.c
@@ -24,7 +24,6 @@
#include "hw/core/qdev.h"
#include "hw/remote/vfio-user-obj.h"
#include "hw/pci/msi.h"
-#include "hw/arm/machines-qom.h"
static void remote_machine_init(MachineState *machine)
{
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
deleted file mode 100644
index f64de7bfc8d..00000000000
--- a/include/hw/arm/machines-qom.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * QOM type definitions for ARM / Aarch64 machines
- *
- * Copyright (c) Linaro
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_ARM_MACHINES_QOM_H
-#define HW_ARM_MACHINES_QOM_H
-
-#include "hw/core/boards.h"
-#include "qemu/target-info.h"
-#include "qemu/target-info-qom.h"
-
-#endif
diff --git a/target-info-qom.c b/target-info-qom.c
index d7b8fbd4fcd..30982d9d18b 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -12,7 +12,6 @@
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
#include "qemu/target-info-qom.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/riscv/machines-qom.h"
diff --git a/target/arm/machine.c b/target/arm/machine.c
index b5eeb586007..f8636d2606e 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -12,7 +12,6 @@
#include "migration/vmstate.h"
#include "qemu/target-info-qom.h"
#include "target/arm/gtimer.h"
-#include "hw/arm/machines-qom.h"
static bool vfp_needed(void *opaque)
{
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 22/27] hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (20 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 21/27] hw/arm: remove machines-qom.h Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 23/27] hw/riscv: remove {riscv32, riscv32_64, riscv64}_machine_interfaces Pierrick Bouvier via qemu development
` (6 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/core/null-machine.c | 5 +----
hw/riscv/virt.c | 2 --
include/hw/riscv/machines-qom.h | 6 ------
target-info-qom.c | 8 --------
target/riscv/machine.c | 4 ----
5 files changed, 1 insertion(+), 24 deletions(-)
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index 2aa748233b3..2f008c4a702 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -56,7 +56,4 @@ static void machine_none_machine_init(MachineClass *mc)
mc->no_cdrom = 1;
}
-DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init,
- { TYPE_TARGET_RISCV32_MACHINE },
- { TYPE_TARGET_RISCV64_MACHINE },
- { })
+DEFINE_MACHINE("none", machine_none_machine_init)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 51bac47a91d..f9de8827624 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1791,8 +1791,6 @@ static const TypeInfo virt_machine_typeinfo = {
.instance_size = sizeof(RISCVVirtState),
.interfaces = (const InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
- { TYPE_TARGET_RISCV32_MACHINE },
- { TYPE_TARGET_RISCV64_MACHINE },
{ }
},
};
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index 5a5b5e05f58..0f9f3b94eac 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -13,12 +13,6 @@
#include "qemu/target-info.h"
#include "qemu/target-info-qom.h"
-#define TYPE_TARGET_RISCV32_MACHINE \
- "target-info-riscv32-machine"
-
-#define TYPE_TARGET_RISCV64_MACHINE \
- "target-info-riscv64-machine"
-
/*
* Interfaces specifying whether a given QOM object is available in
* qemu-system-riscv32, qemu-system-riscv64, or both.
diff --git a/target-info-qom.c b/target-info-qom.c
index 30982d9d18b..5e0f21a319c 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -26,14 +26,6 @@ static const TypeInfo target_info_types[] = {
.parent = TYPE_INTERFACE,
.class_size = sizeof(TargetSpecificClass),
},
- {
- .name = TYPE_TARGET_RISCV32_MACHINE,
- .parent = TYPE_INTERFACE,
- },
- {
- .name = TYPE_TARGET_RISCV64_MACHINE,
- .parent = TYPE_INTERFACE,
- },
};
DEFINE_TYPES(target_info_types)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 507e862f061..484a3730ef4 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -539,18 +539,14 @@ const VMStateDescription vmstate_riscv_cpu = {
const InterfaceInfo riscv32_machine_interfaces[] = {
{ TYPE_TARGET_SPECIFIC },
- { TYPE_TARGET_RISCV32_MACHINE },
{ }
};
const InterfaceInfo riscv64_machine_interfaces[] = {
{ TYPE_TARGET_SPECIFIC },
- { TYPE_TARGET_RISCV64_MACHINE },
{ }
};
const InterfaceInfo riscv32_64_machine_interfaces[] = {
- { TYPE_TARGET_RISCV32_MACHINE },
- { TYPE_TARGET_RISCV64_MACHINE },
{ }
};
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 23/27] hw/riscv: remove {riscv32, riscv32_64, riscv64}_machine_interfaces
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (21 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 22/27] hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier via qemu development
2026-07-24 0:09 ` [PATCH 24/27] hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64} Pierrick Bouvier
` (5 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier via qemu development @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
We can now remove those arrays, and use type_target_specific instead.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/riscv/k230.c | 2 +-
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/opentitan.c | 2 +-
hw/riscv/shakti_c.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 2 +-
hw/riscv/tt_atlantis.c | 2 +-
hw/riscv/xiangshan_kmh.c | 2 +-
include/hw/riscv/machines-qom.h | 15 +++------------
target/riscv/machine.c | 14 --------------
11 files changed, 12 insertions(+), 35 deletions(-)
diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
index 0eb1bede222..631ea71c441 100644
--- a/hw/riscv/k230.c
+++ b/hw/riscv/k230.c
@@ -520,7 +520,7 @@ static const TypeInfo k230_machine_typeinfo = {
.class_init = k230_machine_class_init,
.instance_init = k230_machine_instance_init,
.instance_size = sizeof(K230MachineState),
- .interfaces = riscv64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void k230_machine_init_register_types(void)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 520d1fd4d11..cd0c8ca5f36 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -757,7 +757,7 @@ static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
.class_init = microchip_icicle_kit_machine_class_init,
.instance_init = microchip_icicle_kit_machine_instance_init,
.instance_size = sizeof(MicrochipIcicleKitState),
- .interfaces = riscv64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void microchip_icicle_kit_machine_init_register_types(void)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 5c50b1c423d..0b3e02415ad 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -339,7 +339,7 @@ static const TypeInfo open_titan_types[] = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(OpenTitanState),
.class_init = opentitan_machine_class_init,
- .interfaces = riscv32_machine_interfaces,
+ .interfaces = type_target_specific,
}
};
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 7556fd8c854..b59c4035929 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -99,7 +99,7 @@ static const TypeInfo shakti_c_machine_type_info = {
.class_init = shakti_c_machine_class_init,
.instance_init = shakti_c_machine_instance_init,
.instance_size = sizeof(ShaktiCMachineState),
- .interfaces = riscv64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void shakti_c_machine_type_info_register(void)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 657f6ecad25..5b5dc812b27 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -169,7 +169,7 @@ static const TypeInfo sifive_e_machine_typeinfo = {
.class_init = sifive_e_machine_class_init,
.instance_init = sifive_e_machine_instance_init,
.instance_size = sizeof(SiFiveEState),
- .interfaces = riscv32_64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void sifive_e_machine_init_register_types(void)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 33f1af2cdf1..1fd752dfa2a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -680,7 +680,7 @@ static const TypeInfo sifive_u_machine_typeinfo = {
.class_init = sifive_u_machine_class_init,
.instance_init = sifive_u_machine_instance_init,
.instance_size = sizeof(SiFiveUState),
- .interfaces = riscv32_64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void sifive_u_machine_init_register_types(void)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 1f706f4dcc1..450f5679110 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -292,7 +292,7 @@ static const TypeInfo spike_machine_typeinfo = {
.class_init = spike_machine_class_init,
.instance_init = spike_machine_instance_init,
.instance_size = sizeof(SpikeState),
- .interfaces = riscv32_64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void spike_machine_init_register_types(void)
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index ceaa88d5238..896dfb1afde 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -610,7 +610,7 @@ static const TypeInfo tt_atlantis_types[] = {
.parent = TYPE_MACHINE,
.class_init = tt_atlantis_machine_class_init,
.instance_size = sizeof(TTAtlantisState),
- .interfaces = riscv64_machine_interfaces,
+ .interfaces = type_target_specific,
},
};
diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
index d8ee1dfa15e..101b441a441 100644
--- a/hw/riscv/xiangshan_kmh.c
+++ b/hw/riscv/xiangshan_kmh.c
@@ -217,7 +217,7 @@ static const TypeInfo xiangshan_kmh_machine_info = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(XiangshanKmhState),
.class_init = xiangshan_kmh_machine_class_init,
- .interfaces = riscv64_machine_interfaces,
+ .interfaces = type_target_specific,
};
static void xiangshan_kmh_machine_register_types(void)
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index 0f9f3b94eac..57da218d959 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -13,15 +13,6 @@
#include "qemu/target-info.h"
#include "qemu/target-info-qom.h"
-/*
- * Interfaces specifying whether a given QOM object is available in
- * qemu-system-riscv32, qemu-system-riscv64, or both.
- */
-
-extern const InterfaceInfo riscv32_machine_interfaces[];
-extern const InterfaceInfo riscv64_machine_interfaces[];
-extern const InterfaceInfo riscv32_64_machine_interfaces[];
-
/*
* Helper macros for defining machines available in qemu-system-riscv32,
* qemu-system-riscv64, or both.
@@ -29,14 +20,14 @@ extern const InterfaceInfo riscv32_64_machine_interfaces[];
#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- riscv32_machine_interfaces)
+ type_target_specific)
#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- riscv64_machine_interfaces)
+ type_target_specific)
#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- riscv32_64_machine_interfaces)
+ type_target_specific)
#endif
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 484a3730ef4..555a1f3c881 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -536,17 +536,3 @@ const VMStateDescription vmstate_riscv_cpu = {
NULL
}
};
-
-const InterfaceInfo riscv32_machine_interfaces[] = {
- { TYPE_TARGET_SPECIFIC },
- { }
-};
-
-const InterfaceInfo riscv64_machine_interfaces[] = {
- { TYPE_TARGET_SPECIFIC },
- { }
-};
-
-const InterfaceInfo riscv32_64_machine_interfaces[] = {
- { }
-};
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 24/27] hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64}
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (22 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 23/27] hw/riscv: remove {riscv32, riscv32_64, riscv64}_machine_interfaces Pierrick Bouvier via qemu development
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 25/27] hw/riscv: remove machines-qom.h Pierrick Bouvier
` (4 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
hw/riscv/boston-aia.c | 2 +-
hw/riscv/microblaze-v-generic.c | 2 +-
include/hw/riscv/machines-qom.h | 17 -----------------
3 files changed, 2 insertions(+), 19 deletions(-)
diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c
index 42b16945c12..8c9d50ae762 100644
--- a/hw/riscv/boston-aia.c
+++ b/hw/riscv/boston-aia.c
@@ -475,4 +475,4 @@ static void boston_mach_class_init(MachineClass *mc)
mc->default_cpu_type = TYPE_RISCV_CPU_MIPS_P8700;
}
-DEFINE_MACHINE_RISCV64("boston-aia", boston_mach_class_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("boston-aia", boston_mach_class_init)
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index 7cc24ed189f..e742e67c232 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -188,4 +188,4 @@ static void mb_v_generic_machine_init(MachineClass *mc)
mc->default_cpus = 1;
}
-DEFINE_MACHINE_RISCV32_64("amd-microblaze-v-generic", mb_v_generic_machine_init)
+DEFINE_MACHINE_TARGET_SPECIFIC("amd-microblaze-v-generic", mb_v_generic_machine_init)
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index 57da218d959..0d30759bdd4 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -13,21 +13,4 @@
#include "qemu/target-info.h"
#include "qemu/target-info-qom.h"
-/*
- * Helper macros for defining machines available in qemu-system-riscv32,
- * qemu-system-riscv64, or both.
- */
-
-#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \
- DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- type_target_specific)
-
-#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \
- DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- type_target_specific)
-
-#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \
- DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- type_target_specific)
-
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 25/27] hw/riscv: remove machines-qom.h
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (23 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 24/27] hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64} Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 26/27] configs/targets: remove target info definitions Pierrick Bouvier
` (3 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
configs/targets/riscv32-softmmu.c | 1 -
configs/targets/riscv64-softmmu.c | 1 -
hw/core/null-machine.c | 1 -
hw/riscv/boston-aia.c | 1 -
hw/riscv/k230.c | 1 -
hw/riscv/microblaze-v-generic.c | 1 -
hw/riscv/microchip_pfsoc.c | 1 -
hw/riscv/opentitan.c | 1 -
hw/riscv/shakti_c.c | 1 -
hw/riscv/sifive_e.c | 1 -
hw/riscv/sifive_u.c | 1 -
hw/riscv/spike.c | 1 -
hw/riscv/tt_atlantis.c | 1 -
hw/riscv/virt.c | 1 -
hw/riscv/xiangshan_kmh.c | 1 -
include/hw/riscv/machines-qom.h | 16 ----------------
target-info-qom.c | 1 -
target/riscv/machine.c | 1 -
18 files changed, 33 deletions(-)
delete mode 100644 include/hw/riscv/machines-qom.h
diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c
index 48d55bfc354..671772aa40c 100644
--- a/configs/targets/riscv32-softmmu.c
+++ b/configs/targets/riscv32-softmmu.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
-#include "hw/riscv/machines-qom.h"
#include "target/riscv/cpu-qom.h"
#include "target/riscv/cpu-param.h"
#ifndef CONFIG_USER_ONLY
diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c
index 01013bb5b7c..a28b99fd64e 100644
--- a/configs/targets/riscv64-softmmu.c
+++ b/configs/targets/riscv64-softmmu.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
-#include "hw/riscv/machines-qom.h"
#include "target/riscv/cpu-qom.h"
#include "target/riscv/cpu-param.h"
#ifndef CONFIG_USER_ONLY
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index 2f008c4a702..60254913019 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -16,7 +16,6 @@
#include "hw/core/boards.h"
#include "system/address-spaces.h"
#include "hw/core/cpu.h"
-#include "hw/riscv/machines-qom.h"
static void machine_none_init(MachineState *mch)
{
diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c
index 8c9d50ae762..d63075100a2 100644
--- a/hw/riscv/boston-aia.c
+++ b/hw/riscv/boston-aia.c
@@ -18,7 +18,6 @@
#include "hw/ide/ahci-pci.h"
#include "hw/core/loader.h"
#include "hw/riscv/cps.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/pci-host/xilinx-pcie.h"
#include "hw/core/qdev-properties.h"
#include "qapi/error.h"
diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
index 631ea71c441..ffc0e224e8d 100644
--- a/hw/riscv/k230.c
+++ b/hw/riscv/k230.c
@@ -26,7 +26,6 @@
#include "hw/core/sysbus.h"
#include "hw/riscv/k230.h"
#include "hw/riscv/boot.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/sifive_plic.h"
#include "hw/char/serial-mm.h"
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index e742e67c232..97961b84ac4 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -25,7 +25,6 @@
#include "system/address-spaces.h"
#include "hw/char/xilinx_uartlite.h"
#include "hw/misc/unimp.h"
-#include "hw/riscv/machines-qom.h"
#define LMB_BRAM_SIZE (128 * KiB)
#define MEMORY_BASEADDR 0x80000000
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index cd0c8ca5f36..5f356dc099d 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -49,7 +49,6 @@
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/riscv/microchip_pfsoc.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/sifive_plic.h"
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 0b3e02415ad..5f5a4e01575 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -26,7 +26,6 @@
#include "hw/core/boards.h"
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
-#include "hw/riscv/machines-qom.h"
#include "qemu/units.h"
#include "system/system.h"
#include "system/address-spaces.h"
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index b59c4035929..05c55e9aae3 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -19,7 +19,6 @@
#include "qemu/osdep.h"
#include "hw/core/boards.h"
#include "hw/riscv/shakti_c.h"
-#include "hw/riscv/machines-qom.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/intc/sifive_plic.h"
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 5b5dc812b27..2941f14aff3 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -40,7 +40,6 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_e.h"
#include "hw/riscv/boot.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/char/sifive_uart.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/sifive_plic.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 1fd752dfa2a..cd0b9c2da41 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -51,7 +51,6 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/riscv/fdt-common.h"
#include "hw/char/sifive_uart.h"
#include "hw/intc/riscv_aclint.h"
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 450f5679110..1ca7106efd4 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -34,7 +34,6 @@
#include "hw/riscv/boot.h"
#include "hw/riscv/fdt-common.h"
#include "hw/riscv/numa.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/char/riscv_htif.h"
#include "hw/intc/riscv_aclint.h"
#include "chardev/char.h"
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index 896dfb1afde..cd66548c851 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -20,7 +20,6 @@
#include "hw/riscv/boot.h"
#include "hw/riscv/fdt-common.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/char/serial-mm.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f9de8827624..2d242ef71a5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -36,7 +36,6 @@
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/fdt-common.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/riscv/numa.h"
#include "kvm/kvm_riscv.h"
#include "hw/firmware/smbios.h"
diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
index 101b441a441..a58bbd0e0bc 100644
--- a/hw/riscv/xiangshan_kmh.c
+++ b/hw/riscv/xiangshan_kmh.c
@@ -41,7 +41,6 @@
#include "hw/riscv/boot.h"
#include "hw/riscv/xiangshan_kmh.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/machines-qom.h"
#include "system/system.h"
static const MemMapEntry xiangshan_kmh_memmap[] = {
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
deleted file mode 100644
index 0d30759bdd4..00000000000
--- a/include/hw/riscv/machines-qom.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * QOM type definitions for riscv32 / riscv64 machines
- *
- * Copyright (c) rev.ng Labs Srl.
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_RISCV_MACHINES_QOM_H
-#define HW_RISCV_MACHINES_QOM_H
-
-#include "hw/core/boards.h"
-#include "qemu/target-info.h"
-#include "qemu/target-info-qom.h"
-
-#endif
diff --git a/target-info-qom.c b/target-info-qom.c
index 5e0f21a319c..68ad734049c 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -13,7 +13,6 @@
#include "qemu/target-info-init.h"
#include "qemu/target-info-qom.h"
#include "hw/core/boards.h"
-#include "hw/riscv/machines-qom.h"
const InterfaceInfo type_target_specific[] = {
{ TYPE_TARGET_SPECIFIC },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 555a1f3c881..82e5206fc7d 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -25,7 +25,6 @@
#include "migration/cpu.h"
#include "exec/icount.h"
#include "target/riscv/tcg/debug.h"
-#include "hw/riscv/machines-qom.h"
static bool pmp_needed(void *opaque)
{
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 26/27] configs/targets: remove target info definitions
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (24 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 25/27] hw/riscv: remove machines-qom.h Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-24 0:09 ` [PATCH 27/27] target-info: rename target-info-stub.c in target-info-def.c Pierrick Bouvier
` (2 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Now that we remove machine_typename, we don't need to keep duplicated
file per target anymore. So we can just rely on target-info-stub.c.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
configs/targets/aarch64-softmmu.c | 46 -------------------------------
configs/targets/arm-softmmu.c | 46 -------------------------------
configs/targets/meson.build | 6 ----
configs/targets/riscv32-softmmu.c | 45 ------------------------------
configs/targets/riscv64-softmmu.c | 45 ------------------------------
meson.build | 7 +----
6 files changed, 1 insertion(+), 194 deletions(-)
delete mode 100644 configs/targets/aarch64-softmmu.c
delete mode 100644 configs/targets/arm-softmmu.c
delete mode 100644 configs/targets/meson.build
delete mode 100644 configs/targets/riscv32-softmmu.c
delete mode 100644 configs/targets/riscv64-softmmu.c
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
deleted file mode 100644
index 9efeb366e3b..00000000000
--- a/configs/targets/aarch64-softmmu.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * QEMU binary/target API (qemu-system-aarch64)
- *
- * Copyright (c) Linaro
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#include "qemu/osdep.h"
-#include "qemu/target-info-impl.h"
-#include "qemu/target-info-init.h"
-#include "target/arm/cpu-qom.h"
-#include "target/arm/cpu-param.h"
-#ifndef CONFIG_USER_ONLY
-#include CONFIG_DEVICES
-#endif
-
-static const TargetInfo target_info_aarch64_system = {
- .target_name = "aarch64",
- .target_arch = SYS_EMU_TARGET_AARCH64,
- .long_bits = 64,
- .cpu_type = TYPE_ARM_CPU,
- .endianness = ENDIAN_MODE_LITTLE,
- .page_bits_vary = true,
- .page_bits_init = TARGET_PAGE_BITS_LEGACY,
-
-#ifndef CONFIG_USER_ONLY
-# ifdef CONFIG_MULTIPROCESS
- .config_multiprocess = true,
-# else
- .config_multiprocess = false,
-# endif
-# ifdef CONFIG_NITRO
- .config_nitro = true,
-# else
- .config_nitro = false,
-# endif
-# ifdef CONFIG_XEN
- .config_xen = true,
-# else
- .config_xen = false,
-# endif
-#endif
-};
-
-target_info_init(target_info_aarch64_system)
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
deleted file mode 100644
index 8785ea01824..00000000000
--- a/configs/targets/arm-softmmu.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * QEMU binary/target API (qemu-system-arm)
- *
- * Copyright (c) Linaro
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#include "qemu/osdep.h"
-#include "qemu/target-info-impl.h"
-#include "qemu/target-info-init.h"
-#include "target/arm/cpu-qom.h"
-#include "target/arm/cpu-param.h"
-#ifndef CONFIG_USER_ONLY
-#include CONFIG_DEVICES
-#endif
-
-static const TargetInfo target_info_arm_system = {
- .target_name = "arm",
- .target_arch = SYS_EMU_TARGET_ARM,
- .long_bits = 32,
- .cpu_type = TYPE_ARM_CPU,
- .endianness = ENDIAN_MODE_LITTLE,
- .page_bits_vary = true,
- .page_bits_init = TARGET_PAGE_BITS_LEGACY,
-
-#ifndef CONFIG_USER_ONLY
-# ifdef CONFIG_MULTIPROCESS
- .config_multiprocess = true,
-# else
- .config_multiprocess = false,
-# endif
-# ifdef CONFIG_NITRO
- .config_nitro = true,
-# else
- .config_nitro = false,
-# endif
-# ifdef CONFIG_XEN
- .config_xen = true,
-# else
- .config_xen = false,
-# endif
-#endif
-};
-
-target_info_init(target_info_arm_system)
diff --git a/configs/targets/meson.build b/configs/targets/meson.build
deleted file mode 100644
index 2ab4d27eaf5..00000000000
--- a/configs/targets/meson.build
+++ /dev/null
@@ -1,6 +0,0 @@
-foreach target : [
- 'arm-softmmu', 'aarch64-softmmu',
- 'riscv32-softmmu', 'riscv64-softmmu'
- ]
- config_target_info += {target : files(target + '.c')}
-endforeach
diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c
deleted file mode 100644
index 671772aa40c..00000000000
--- a/configs/targets/riscv32-softmmu.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * QEMU binary/target API (qemu-system-riscv32)
- *
- * Copyright (c) rev.ng Labs Srl.
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#include "qemu/osdep.h"
-#include "qemu/target-info-impl.h"
-#include "qemu/target-info-init.h"
-#include "target/riscv/cpu-qom.h"
-#include "target/riscv/cpu-param.h"
-#ifndef CONFIG_USER_ONLY
-#include CONFIG_DEVICES
-#endif
-
-static const TargetInfo target_info_riscv32_system = {
- .target_name = "riscv32",
- .target_arch = SYS_EMU_TARGET_RISCV32,
- .long_bits = 32,
- .cpu_type = TYPE_RISCV_CPU,
- .endianness = ENDIAN_MODE_LITTLE,
- .page_bits_init = TARGET_PAGE_BITS,
-
-#ifndef CONFIG_USER_ONLY
-# ifdef CONFIG_MULTIPROCESS
- .config_multiprocess = true,
-# else
- .config_multiprocess = false,
-# endif
-# ifdef CONFIG_NITRO
- .config_nitro = true,
-# else
- .config_nitro = false,
-# endif
-# ifdef CONFIG_XEN
- .config_xen = true,
-# else
- .config_xen = false,
-# endif
-#endif
-};
-
-target_info_init(target_info_riscv32_system)
diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c
deleted file mode 100644
index a28b99fd64e..00000000000
--- a/configs/targets/riscv64-softmmu.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * QEMU binary/target API (qemu-system-riscv64)
- *
- * Copyright (c) rev.ng Labs Srl.
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#include "qemu/osdep.h"
-#include "qemu/target-info-impl.h"
-#include "qemu/target-info-init.h"
-#include "target/riscv/cpu-qom.h"
-#include "target/riscv/cpu-param.h"
-#ifndef CONFIG_USER_ONLY
-#include CONFIG_DEVICES
-#endif
-
-static const TargetInfo target_info_riscv64_system = {
- .target_name = "riscv64",
- .target_arch = SYS_EMU_TARGET_RISCV64,
- .long_bits = 64,
- .cpu_type = TYPE_RISCV_CPU,
- .endianness = ENDIAN_MODE_LITTLE,
- .page_bits_init = TARGET_PAGE_BITS,
-
-#ifndef CONFIG_USER_ONLY
-# ifdef CONFIG_MULTIPROCESS
- .config_multiprocess = true,
-# else
- .config_multiprocess = false,
-# endif
-# ifdef CONFIG_NITRO
- .config_nitro = true,
-# else
- .config_nitro = false,
-# endif
-# ifdef CONFIG_XEN
- .config_xen = true,
-# else
- .config_xen = false,
-# endif
-#endif
-};
-
-target_info_init(target_info_riscv64_system)
diff --git a/meson.build b/meson.build
index 2b5db0d096a..6cfa0e6e754 100644
--- a/meson.build
+++ b/meson.build
@@ -3745,7 +3745,6 @@ subdir('dump')
subdir('accel')
subdir('backends')
-subdir('configs/targets')
subdir('disas')
subdir('migration')
subdir('monitor')
@@ -4322,11 +4321,7 @@ foreach target : target_dirs
endif
endif
- if target in config_target_info
- arch_srcs += config_target_info[target]
- else
- arch_srcs += files('target-info-stub.c')
- endif
+ arch_srcs += files('target-info-stub.c')
if target_base_arch in target_arch
t = target_arch[target_base_arch].apply(config_target, strict: false)
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH 27/27] target-info: rename target-info-stub.c in target-info-def.c
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (25 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 26/27] configs/targets: remove target info definitions Pierrick Bouvier
@ 2026-07-24 0:09 ` Pierrick Bouvier
2026-07-30 17:33 ` [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
2026-08-10 15:46 ` Peter Maydell
28 siblings, 0 replies; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-24 0:09 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
Now it's the only file left to define target info, we call it def to
make the intent more clear.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
meson.build | 2 +-
target-info-stub.c => target-info-def.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
rename target-info-stub.c => target-info-def.c (92%)
diff --git a/meson.build b/meson.build
index 6cfa0e6e754..449d50f2983 100644
--- a/meson.build
+++ b/meson.build
@@ -4321,7 +4321,7 @@ foreach target : target_dirs
endif
endif
- arch_srcs += files('target-info-stub.c')
+ arch_srcs += files('target-info-def.c')
if target_base_arch in target_arch
t = target_arch[target_base_arch].apply(config_target, strict: false)
diff --git a/target-info-stub.c b/target-info-def.c
similarity index 92%
rename from target-info-stub.c
rename to target-info-def.c
index 71a6064548f..5d38e405735 100644
--- a/target-info-stub.c
+++ b/target-info-def.c
@@ -1,5 +1,5 @@
/*
- * QEMU target info stubs (target specific)
+ * QEMU target info definition (target specific)
*
* Copyright (c) Linaro
*
@@ -28,7 +28,7 @@ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
QEMU_BUILD_BUG_ON(TARGET_PAGE_BITS < TARGET_PAGE_BITS_MIN);
#endif
-static const TargetInfo target_info_stub = {
+static const TargetInfo target_info_def = {
.target_name = TARGET_NAME,
.target_arch = glue(SYS_EMU_TARGET_, TARGET_ARCH),
.long_bits = TARGET_LONG_BITS,
@@ -63,4 +63,4 @@ static const TargetInfo target_info_stub = {
#endif
};
-target_info_init(target_info_stub)
+target_info_init(target_info_def)
--
2.43.0
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH 00/27] single-binary: implement dynamic filtering for machine types
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (26 preceding siblings ...)
2026-07-24 0:09 ` [PATCH 27/27] target-info: rename target-info-stub.c in target-info-def.c Pierrick Bouvier
@ 2026-07-30 17:33 ` Pierrick Bouvier
2026-08-05 13:30 ` Yonggang Luo
2026-08-10 15:46 ` Peter Maydell
28 siblings, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-07-30 17:33 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On 7/23/2026 5:09 PM, Pierrick Bouvier wrote:
> Now that we can link a single-binary with at least two targets (arm, aarch64),
> we want to make sure that we expose the same set of machines (later devices and
> cpus) than target binaries. For that, we implemented a static filtering based on
> target interfaces that each machine will implement to declare which targets have
> this machine.
>
> However, we discovered that this static filtering is not enough. Indeed, some
> machines and devices do not depend only on target, and their presence can depend
> on Kconfig or host/target combination. Thus, our static approach can't work, and
> we need something more flexible.
>
> This series adds a new TYPE_TARGET_SPECIFIC, that declare a single function
> bool is_available(void). From there, any machine type (and later devices and
> cpus) can implement it to override their presence for each target.
> We first replace the existing static mechanism with this, and once done, we
> cleanup all the old interface. One nice benefit is that we can get rid of
> config/targets/*.c files, which saves duplication.
>
> This series was tested by comparing list of machines for all qemu system
> binaries, before and after this change, to make sure we don't introduce a
> regression.
>
> Pierrick Bouvier (27):
> include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
> hw/arm: implement TYPE_TARGET_SPECIFIC
> target-info: add target_riscv32 and target_base_riscv
> hw/riscv: implement TYPE_TARGET_SPECIFIC
> target-info: add target_config_multiprocess
> hw/remote/machine: remove unsupported arm target
> hw/remote/machine: implement TYPE_TARGET_SPECIFIC
> target-info: add target_config_xen
> hw/arm/xen-pvh: implement TYPE_TARGET_SPECIFIC
> hw/xenpv/xen_machine_pv: implement TYPE_TARGET_SPECIFIC
> target-info: add target_config_nitro
> hw/nitro/machine: implement TYPE_TARGET_SPECIFIC
> target-info-qom: implement new machine filtering per target
> target-info-qom: use TYPE_MACHINE instead of target_machine_typename
> target-info: remove target_machine_typename
> target-info-qom: add type_target_specific
> hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE
> hw/arm: remove {arm,arm_aarch64,aarch64}_machine_interfaces
> include/hw/core/boards.h: add DEFINE_MACHINE_TARGET_SPECIFIC
> hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM}
> hw/arm: remove machines-qom.h
> hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE
> hw/riscv: remove {riscv32,riscv32_64,riscv64}_machine_interfaces
> hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64}
> hw/riscv: remove machines-qom.h
> configs/targets: remove target info definitions
> target-info: rename target-info-stub.c in target-info-def.c
>
Gentle ping after a week.
You're welcome to review only your architecture if time is limited, and
validate the global approach.
Regards,
Pierrick
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 00/27] single-binary: implement dynamic filtering for machine types
2026-07-30 17:33 ` [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
@ 2026-08-05 13:30 ` Yonggang Luo
2026-08-05 16:20 ` Pierrick Bouvier
0 siblings, 1 reply; 56+ messages in thread
From: Yonggang Luo @ 2026-08-05 13:30 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
[-- Attachment #1: Type: text/plain, Size: 3817 bytes --]
On Fri, Jul 31, 2026 at 1:34 AM Pierrick Bouvier <
pierrick.bouvier@oss.qualcomm.com> wrote:
>
> On 7/23/2026 5:09 PM, Pierrick Bouvier wrote:
> > Now that we can link a single-binary with at least two targets (arm,
aarch64),
> > we want to make sure that we expose the same set of machines (later
devices and
> > cpus) than target binaries. For that, we implemented a static filtering
based on
> > target interfaces that each machine will implement to declare which
targets have
> > this machine.
> >
> > However, we discovered that this static filtering is not enough.
Indeed, some
> > machines and devices do not depend only on target, and their presence
can depend
> > on Kconfig or host/target combination. Thus, our static approach can't
work, and
> > we need something more flexible.
> >
> > This series adds a new TYPE_TARGET_SPECIFIC, that declare a single
function
> > bool is_available(void). From there, any machine type (and later
devices and
> > cpus) can implement it to override their presence for each target.
> > We first replace the existing static mechanism with this, and once
done, we
> > cleanup all the old interface. One nice benefit is that we can get rid
of
> > config/targets/*.c files, which saves duplication.
> >
> > This series was tested by comparing list of machines for all qemu system
> > binaries, before and after this change, to make sure we don't introduce
a
> > regression.
> >
I am also tracing for this. So what's the shape of the final command line?
Maybe we can at least get arm/arm64/riscv32/risv64/riscv32-be/risv64-be to
be in a single binary.
The -be is needed because gdbstub would need this to get gdb working fine.
so the endian mode is important. arm/arm64 have nothing about be support
yet, even though in spec also have
> > Pierrick Bouvier (27):
> > include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
> > hw/arm: implement TYPE_TARGET_SPECIFIC
> > target-info: add target_riscv32 and target_base_riscv
> > hw/riscv: implement TYPE_TARGET_SPECIFIC
> > target-info: add target_config_multiprocess
> > hw/remote/machine: remove unsupported arm target
> > hw/remote/machine: implement TYPE_TARGET_SPECIFIC
> > target-info: add target_config_xen
> > hw/arm/xen-pvh: implement TYPE_TARGET_SPECIFIC
> > hw/xenpv/xen_machine_pv: implement TYPE_TARGET_SPECIFIC
> > target-info: add target_config_nitro
> > hw/nitro/machine: implement TYPE_TARGET_SPECIFIC
> > target-info-qom: implement new machine filtering per target
> > target-info-qom: use TYPE_MACHINE instead of target_machine_typename
> > target-info: remove target_machine_typename
> > target-info-qom: add type_target_specific
> > hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE
> > hw/arm: remove {arm,arm_aarch64,aarch64}_machine_interfaces
> > include/hw/core/boards.h: add DEFINE_MACHINE_TARGET_SPECIFIC
> > hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM}
> > hw/arm: remove machines-qom.h
> > hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE
> > hw/riscv: remove {riscv32,riscv32_64,riscv64}_machine_interfaces
> > hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64}
> > hw/riscv: remove machines-qom.h
> > configs/targets: remove target info definitions
> > target-info: rename target-info-stub.c in target-info-def.c
Does that mean target-info-def.c would be compiled N-times. N is the
target list count and finally linkage into a single binary?
How to choose this target-info?
> >
>
> Gentle ping after a week.
> You're welcome to review only your architecture if time is limited, and
> validate the global approach.
>
> Regards,
> Pierrick
>
--
此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo
[-- Attachment #2: Type: text/html, Size: 4730 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 00/27] single-binary: implement dynamic filtering for machine types
2026-08-05 13:30 ` Yonggang Luo
@ 2026-08-05 16:20 ` Pierrick Bouvier
2026-08-06 20:29 ` Daniel Henrique Barboza
0 siblings, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-08-05 16:20 UTC (permalink / raw)
To: luoyonggang
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Peter Maydell, Alistair Francis
On 8/5/2026 6:30 AM, Yonggang Luo wrote:
>
>
> On Fri, Jul 31, 2026 at 1:34 AM Pierrick Bouvier
> <pierrick.bouvier@oss.qualcomm.com
> <mailto:pierrick.bouvier@oss.qualcomm.com>> wrote:
>>
>> On 7/23/2026 5:09 PM, Pierrick Bouvier wrote:
>> > Now that we can link a single-binary with at least two targets (arm,
> aarch64),
>> > we want to make sure that we expose the same set of machines (later
> devices and
>> > cpus) than target binaries. For that, we implemented a static
> filtering based on
>> > target interfaces that each machine will implement to declare which
> targets have
>> > this machine.
>> >
>> > However, we discovered that this static filtering is not enough.
> Indeed, some
>> > machines and devices do not depend only on target, and their
> presence can depend
>> > on Kconfig or host/target combination. Thus, our static approach
> can't work, and
>> > we need something more flexible.
>> >
>> > This series adds a new TYPE_TARGET_SPECIFIC, that declare a single
> function
>> > bool is_available(void). From there, any machine type (and later
> devices and
>> > cpus) can implement it to override their presence for each target.
>> > We first replace the existing static mechanism with this, and once
> done, we
>> > cleanup all the old interface. One nice benefit is that we can get
> rid of
>> > config/targets/*.c files, which saves duplication.
>> >
>> > This series was tested by comparing list of machines for all qemu system
>> > binaries, before and after this change, to make sure we don't
> introduce a
>> > regression.
>> >
>
> I am also tracing for this. So what's the shape of the final command line?
>
I have those commits ready, but I would like to get filtering done
before so we can focus on command line independently.
Currently, what we have implemented is:
./build/qemu-system -target {arm,aarch64,microblaze}
Or
cp ./build/qemu-system ./build/qemu-system-{arm,aarch64,microblaze} and
there is no need to use -target in this case.
> Maybe we can at least get arm/arm64/riscv32/risv64/riscv32-be/risv64-be
> to be in a single binary.
>
v0 will be arm/arm64/microblaze.
risvc64 is a wip, it's not yet ready for integration.
> The -be is needed because gdbstub would need this to get gdb working
> fine. so the endian mode is important. arm/arm64 have nothing about be
> support yet, even though in spec also have
>
>
>
>> > Pierrick Bouvier (27):
>> > include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
>> > hw/arm: implement TYPE_TARGET_SPECIFIC
>> > target-info: add target_riscv32 and target_base_riscv
>> > hw/riscv: implement TYPE_TARGET_SPECIFIC
>> > target-info: add target_config_multiprocess
>> > hw/remote/machine: remove unsupported arm target
>> > hw/remote/machine: implement TYPE_TARGET_SPECIFIC
>> > target-info: add target_config_xen
>> > hw/arm/xen-pvh: implement TYPE_TARGET_SPECIFIC
>> > hw/xenpv/xen_machine_pv: implement TYPE_TARGET_SPECIFIC
>> > target-info: add target_config_nitro
>> > hw/nitro/machine: implement TYPE_TARGET_SPECIFIC
>> > target-info-qom: implement new machine filtering per target
>> > target-info-qom: use TYPE_MACHINE instead of target_machine_typename
>> > target-info: remove target_machine_typename
>> > target-info-qom: add type_target_specific
>> > hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE
>> > hw/arm: remove {arm,arm_aarch64,aarch64}_machine_interfaces
>> > include/hw/core/boards.h: add DEFINE_MACHINE_TARGET_SPECIFIC
>> > hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM}
>> > hw/arm: remove machines-qom.h
>> > hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE
>> > hw/riscv: remove {riscv32,riscv32_64,riscv64}_machine_interfaces
>> > hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64}
>> > hw/riscv: remove machines-qom.h
>> > configs/targets: remove target info definitions
>
>> > target-info: rename target-info-stub.c in target-info-def.c
>
> Does that mean target-info-def.c would be compiled N-times. N is the
> target list count and finally linkage into a single binary?
> How to choose this target-info?
>
Yes, correct.
We choose either from -target arch, or from binary name.
In case a single target-info is present, we don't check binary name and
simply use it.
>
>> >
>>
>> Gentle ping after a week.
>> You're welcome to review only your architecture if time is limited, and
>> validate the global approach.
>>
>> Regards,
>> Pierrick
>>
>
>
> --
> 此致
> 礼
> 罗勇刚
> Yours
> sincerely,
> Yonggang Luo
Regards,
Pierrick
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 00/27] single-binary: implement dynamic filtering for machine types
2026-08-05 16:20 ` Pierrick Bouvier
@ 2026-08-06 20:29 ` Daniel Henrique Barboza
0 siblings, 0 replies; 56+ messages in thread
From: Daniel Henrique Barboza @ 2026-08-06 20:29 UTC (permalink / raw)
To: Pierrick Bouvier, luoyonggang
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Bernhard Beschow, Anton Johansson, Alistair Francis,
Peter Maydell, Alistair Francis
On 8/5/2026 1:20 PM, Pierrick Bouvier wrote:
> On 8/5/2026 6:30 AM, Yonggang Luo wrote:
>>
>>
>> On Fri, Jul 31, 2026 at 1:34 AM Pierrick Bouvier
>> <pierrick.bouvier@oss.qualcomm.com
>> <mailto:pierrick.bouvier@oss.qualcomm.com>> wrote:
>>>
>>> On 7/23/2026 5:09 PM, Pierrick Bouvier wrote:
>>>> Now that we can link a single-binary with at least two targets (arm,
>> aarch64),
>>>> we want to make sure that we expose the same set of machines (later
>> devices and
>>>> cpus) than target binaries. For that, we implemented a static
>> filtering based on
>>>> target interfaces that each machine will implement to declare which
>> targets have
>>>> this machine.
>>>>
>>>> However, we discovered that this static filtering is not enough.
>> Indeed, some
>>>> machines and devices do not depend only on target, and their
>> presence can depend
>>>> on Kconfig or host/target combination. Thus, our static approach
>> can't work, and
>>>> we need something more flexible.
>>>>
>>>> This series adds a new TYPE_TARGET_SPECIFIC, that declare a single
>> function
>>>> bool is_available(void). From there, any machine type (and later
>> devices and
>>>> cpus) can implement it to override their presence for each target.
>>>> We first replace the existing static mechanism with this, and once
>> done, we
>>>> cleanup all the old interface. One nice benefit is that we can get
>> rid of
>>>> config/targets/*.c files, which saves duplication.
>>>>
>>>> This series was tested by comparing list of machines for all qemu system
>>>> binaries, before and after this change, to make sure we don't
>> introduce a
>>>> regression.
>>>>
>>
>> I am also tracing for this. So what's the shape of the final command line?
>>
>
> I have those commits ready, but I would like to get filtering done
> before so we can focus on command line independently.
>
> Currently, what we have implemented is:
> ./build/qemu-system -target {arm,aarch64,microblaze}
> Or
> cp ./build/qemu-system ./build/qemu-system-{arm,aarch64,microblaze} and
> there is no need to use -target in this case.
>
>> Maybe we can at least get arm/arm64/riscv32/risv64/riscv32-be/risv64-be
>> to be in a single binary.
>>
>
> v0 will be arm/arm64/microblaze.
> risvc64 is a wip, it's not yet ready for integration.
I talked with Mr. Pierrick and Mr. Phil and offered a hand in the riscv side.
So far I wasn't able to do much about it - qemu-riscv has been more active than
usual and we're barely keeping up with the reviews and ongoing work we want
to push for 11.2 ... I think we'll be in better shape for v1 of this effort.
Thanks,
Daniel
>
>> The -be is needed because gdbstub would need this to get gdb working
>> fine. so the endian mode is important. arm/arm64 have nothing about be
>> support yet, even though in spec also have
>>
>>
>>
>>>> Pierrick Bouvier (27):
>>>> include/qemu/target-info-qom.h: declare TYPE_TARGET_SPECIFIC interface
>>>> hw/arm: implement TYPE_TARGET_SPECIFIC
>>>> target-info: add target_riscv32 and target_base_riscv
>>>> hw/riscv: implement TYPE_TARGET_SPECIFIC
>>>> target-info: add target_config_multiprocess
>>>> hw/remote/machine: remove unsupported arm target
>>>> hw/remote/machine: implement TYPE_TARGET_SPECIFIC
>>>> target-info: add target_config_xen
>>>> hw/arm/xen-pvh: implement TYPE_TARGET_SPECIFIC
>>>> hw/xenpv/xen_machine_pv: implement TYPE_TARGET_SPECIFIC
>>>> target-info: add target_config_nitro
>>>> hw/nitro/machine: implement TYPE_TARGET_SPECIFIC
>>>> target-info-qom: implement new machine filtering per target
>>>> target-info-qom: use TYPE_MACHINE instead of target_machine_typename
>>>> target-info: remove target_machine_typename
>>>> target-info-qom: add type_target_specific
>>>> hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE
>>>> hw/arm: remove {arm,arm_aarch64,aarch64}_machine_interfaces
>>>> include/hw/core/boards.h: add DEFINE_MACHINE_TARGET_SPECIFIC
>>>> hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM}
>>>> hw/arm: remove machines-qom.h
>>>> hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE
>>>> hw/riscv: remove {riscv32,riscv32_64,riscv64}_machine_interfaces
>>>> hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64}
>>>> hw/riscv: remove machines-qom.h
>>>> configs/targets: remove target info definitions
>>
>>>> target-info: rename target-info-stub.c in target-info-def.c
>>
>> Does that mean target-info-def.c would be compiled N-times. N is the
>> target list count and finally linkage into a single binary?
>> How to choose this target-info?
>>
>
> Yes, correct.
> We choose either from -target arch, or from binary name.
> In case a single target-info is present, we don't check binary name and
> simply use it.
>
>>
>>>>
>>>
>>> Gentle ping after a week.
>>> You're welcome to review only your architecture if time is limited, and
>>> validate the global approach.
>>>
>>> Regards,
>>> Pierrick
>>>
>>
>>
>> --
>> 此致
>> 礼
>> 罗勇刚
>> Yours
>> sincerely,
>> Yonggang Luo
>
> Regards,
> Pierrick
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH 00/27] single-binary: implement dynamic filtering for machine types
2026-07-24 0:09 [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
` (27 preceding siblings ...)
2026-07-30 17:33 ` [PATCH 00/27] single-binary: implement dynamic filtering for machine types Pierrick Bouvier
@ 2026-08-10 15:46 ` Peter Maydell
2026-08-10 15:55 ` Pierrick Bouvier
28 siblings, 1 reply; 56+ messages in thread
From: Peter Maydell @ 2026-08-10 15:46 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Alistair Francis
On Fri, 24 Jul 2026 at 01:09, Pierrick Bouvier
<pierrick.bouvier@oss.qualcomm.com> wrote:
>
> Now that we can link a single-binary with at least two targets (arm, aarch64),
> we want to make sure that we expose the same set of machines (later devices and
> cpus) than target binaries. For that, we implemented a static filtering based on
> target interfaces that each machine will implement to declare which targets have
> this machine.
>
> However, we discovered that this static filtering is not enough. Indeed, some
> machines and devices do not depend only on target, and their presence can depend
> on Kconfig or host/target combination. Thus, our static approach can't work, and
> we need something more flexible.
Do you have some specific examples of where the static filtering isn't
sufficient? I can certainly believe that we have some at the moment,
but I'm curious about how much of that is "just by accident because
ifdefs were the easy thing to do" versus when the filtering makes
sense for avoiding showing the user things that won't work.
-- PMM
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 00/27] single-binary: implement dynamic filtering for machine types
2026-08-10 15:46 ` Peter Maydell
@ 2026-08-10 15:55 ` Pierrick Bouvier
2026-08-10 16:00 ` Peter Maydell
0 siblings, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-08-10 15:55 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Alistair Francis
On 8/10/2026 8:46 AM, Peter Maydell wrote:
> On Fri, 24 Jul 2026 at 01:09, Pierrick Bouvier
> <pierrick.bouvier@oss.qualcomm.com> wrote:
>>
>> Now that we can link a single-binary with at least two targets (arm, aarch64),
>> we want to make sure that we expose the same set of machines (later devices and
>> cpus) than target binaries. For that, we implemented a static filtering based on
>> target interfaces that each machine will implement to declare which targets have
>> this machine.
>>
>> However, we discovered that this static filtering is not enough. Indeed, some
>> machines and devices do not depend only on target, and their presence can depend
>> on Kconfig or host/target combination. Thus, our static approach can't work, and
>> we need something more flexible.
>
> Do you have some specific examples of where the static filtering isn't
> sufficient? I can certainly believe that we have some at the moment,
> but I'm curious about how much of that is "just by accident because
> ifdefs were the easy thing to do" versus when the filtering makes
> sense for avoiding showing the user things that won't work.
>
> -- PMM
As you can see in the series, machines nitro and x-remote are concerned
(they depend on host/guest combination - summarized by a target config
entry). There are additional devices I found also (igpd bus, plus nitro
devices), but I wanted to validate approach on machines first.
I didn't observe any cpu (yet) that needs this extra flexibility.
This is only for arm/aarch64 combination, I expect we'll have other
cases as we add new archs in single-binary.
Also, there is a benefit to register *all* types and filter them
afterward: we can identify conflicting QOM types with any combination,
and not only depending on which targets gets enabled.
Finally, this approach is much less verbose than adding an if (cond) {}
on every type_register_static location.
Do you have an alternative suggestion that would retain all those
benefits, but would be better in your option?
Thanks,
Pierrick
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 00/27] single-binary: implement dynamic filtering for machine types
2026-08-10 15:55 ` Pierrick Bouvier
@ 2026-08-10 16:00 ` Peter Maydell
2026-08-10 16:14 ` Pierrick Bouvier
0 siblings, 1 reply; 56+ messages in thread
From: Peter Maydell @ 2026-08-10 16:00 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Alistair Francis
On Mon, 10 Aug 2026 at 16:55, Pierrick Bouvier
<pierrick.bouvier@oss.qualcomm.com> wrote:
>
> On 8/10/2026 8:46 AM, Peter Maydell wrote:
> > On Fri, 24 Jul 2026 at 01:09, Pierrick Bouvier
> > <pierrick.bouvier@oss.qualcomm.com> wrote:
> >>
> >> Now that we can link a single-binary with at least two targets (arm, aarch64),
> >> we want to make sure that we expose the same set of machines (later devices and
> >> cpus) than target binaries. For that, we implemented a static filtering based on
> >> target interfaces that each machine will implement to declare which targets have
> >> this machine.
> >>
> >> However, we discovered that this static filtering is not enough. Indeed, some
> >> machines and devices do not depend only on target, and their presence can depend
> >> on Kconfig or host/target combination. Thus, our static approach can't work, and
> >> we need something more flexible.
> >
> > Do you have some specific examples of where the static filtering isn't
> > sufficient? I can certainly believe that we have some at the moment,
> > but I'm curious about how much of that is "just by accident because
> > ifdefs were the easy thing to do" versus when the filtering makes
> > sense for avoiding showing the user things that won't work.
> As you can see in the series, machines nitro and x-remote are concerned
> (they depend on host/guest combination - summarized by a target config
> entry). There are additional devices I found also (igpd bus, plus nitro
> devices), but I wanted to validate approach on machines first.
> I didn't observe any cpu (yet) that needs this extra flexibility.
> This is only for arm/aarch64 combination, I expect we'll have other
> cases as we add new archs in single-binary.
>
> Also, there is a benefit to register *all* types and filter them
> afterward: we can identify conflicting QOM types with any combination,
> and not only depending on which targets gets enabled.
> Finally, this approach is much less verbose than adding an if (cond) {}
> on every type_register_static location.
>
> Do you have an alternative suggestion that would retain all those
> benefits, but would be better in your option?
No, I'm not particularly strongly opinionated about the approach,
I was just trying to understand the background motivation for it.
thanks
-- PMM
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 00/27] single-binary: implement dynamic filtering for machine types
2026-08-10 16:00 ` Peter Maydell
@ 2026-08-10 16:14 ` Pierrick Bouvier
2026-08-10 16:42 ` Daniel P. Berrangé
0 siblings, 1 reply; 56+ messages in thread
From: Pierrick Bouvier @ 2026-08-10 16:14 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, Philippe Mathieu-Daudé, Nicholas Piggin,
Daniel Henrique Barboza, Bernhard Beschow, Anton Johansson,
Alistair Francis, Alistair Francis
On 8/10/2026 9:00 AM, Peter Maydell wrote:
> On Mon, 10 Aug 2026 at 16:55, Pierrick Bouvier
> <pierrick.bouvier@oss.qualcomm.com> wrote:
>>
>> On 8/10/2026 8:46 AM, Peter Maydell wrote:
>>> On Fri, 24 Jul 2026 at 01:09, Pierrick Bouvier
>>> <pierrick.bouvier@oss.qualcomm.com> wrote:
>>>>
>>>> Now that we can link a single-binary with at least two targets (arm, aarch64),
>>>> we want to make sure that we expose the same set of machines (later devices and
>>>> cpus) than target binaries. For that, we implemented a static filtering based on
>>>> target interfaces that each machine will implement to declare which targets have
>>>> this machine.
>>>>
>>>> However, we discovered that this static filtering is not enough. Indeed, some
>>>> machines and devices do not depend only on target, and their presence can depend
>>>> on Kconfig or host/target combination. Thus, our static approach can't work, and
>>>> we need something more flexible.
>>>
>>> Do you have some specific examples of where the static filtering isn't
>>> sufficient? I can certainly believe that we have some at the moment,
>>> but I'm curious about how much of that is "just by accident because
>>> ifdefs were the easy thing to do" versus when the filtering makes
>>> sense for avoiding showing the user things that won't work.
>
>> As you can see in the series, machines nitro and x-remote are concerned
>> (they depend on host/guest combination - summarized by a target config
>> entry). There are additional devices I found also (igpd bus, plus nitro
>> devices), but I wanted to validate approach on machines first.
>> I didn't observe any cpu (yet) that needs this extra flexibility.
>> This is only for arm/aarch64 combination, I expect we'll have other
>> cases as we add new archs in single-binary.
>>
>> Also, there is a benefit to register *all* types and filter them
>> afterward: we can identify conflicting QOM types with any combination,
>> and not only depending on which targets gets enabled.
>> Finally, this approach is much less verbose than adding an if (cond) {}
>> on every type_register_static location.
>>
>> Do you have an alternative suggestion that would retain all those
>> benefits, but would be better in your option?
>
> No, I'm not particularly strongly opinionated about the approach,
> I was just trying to understand the background motivation for it.
>
It would be more easy if we could expose the patches we have to enable
the single-binary itself, so people can test and see what is the value
of current series. However, given reception of such patches in the past,
we decided to present them as the last piece of puzzle, and not before.
So we're trying to make sure that existing targets (arm, aarch64) have
the exact same set of devices/machines/cpu, before adding the machinery
to build and run the single-binary.
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH 00/27] single-binary: implement dynamic filtering for machine types
2026-08-10 16:14 ` Pierrick Bouvier
@ 2026-08-10 16:42 ` Daniel P. Berrangé
0 siblings, 0 replies; 56+ messages in thread
From: Daniel P. Berrangé @ 2026-08-10 16:42 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: Peter Maydell, qemu-devel, Philippe Mathieu-Daudé,
Nicholas Piggin, Daniel Henrique Barboza, Bernhard Beschow,
Anton Johansson, Alistair Francis, Alistair Francis
On Mon, Aug 10, 2026 at 09:14:49AM -0700, Pierrick Bouvier wrote:
> On 8/10/2026 9:00 AM, Peter Maydell wrote:
> > On Mon, 10 Aug 2026 at 16:55, Pierrick Bouvier
> > <pierrick.bouvier@oss.qualcomm.com> wrote:
> >>
> >> On 8/10/2026 8:46 AM, Peter Maydell wrote:
> >>> On Fri, 24 Jul 2026 at 01:09, Pierrick Bouvier
> >>> <pierrick.bouvier@oss.qualcomm.com> wrote:
> >>>>
> >>>> Now that we can link a single-binary with at least two targets (arm, aarch64),
> >>>> we want to make sure that we expose the same set of machines (later devices and
> >>>> cpus) than target binaries. For that, we implemented a static filtering based on
> >>>> target interfaces that each machine will implement to declare which targets have
> >>>> this machine.
> >>>>
> >>>> However, we discovered that this static filtering is not enough. Indeed, some
> >>>> machines and devices do not depend only on target, and their presence can depend
> >>>> on Kconfig or host/target combination. Thus, our static approach can't work, and
> >>>> we need something more flexible.
> >>>
> >>> Do you have some specific examples of where the static filtering isn't
> >>> sufficient? I can certainly believe that we have some at the moment,
> >>> but I'm curious about how much of that is "just by accident because
> >>> ifdefs were the easy thing to do" versus when the filtering makes
> >>> sense for avoiding showing the user things that won't work.
> >
> >> As you can see in the series, machines nitro and x-remote are concerned
> >> (they depend on host/guest combination - summarized by a target config
> >> entry). There are additional devices I found also (igpd bus, plus nitro
> >> devices), but I wanted to validate approach on machines first.
> >> I didn't observe any cpu (yet) that needs this extra flexibility.
> >> This is only for arm/aarch64 combination, I expect we'll have other
> >> cases as we add new archs in single-binary.
> >>
> >> Also, there is a benefit to register *all* types and filter them
> >> afterward: we can identify conflicting QOM types with any combination,
> >> and not only depending on which targets gets enabled.
> >> Finally, this approach is much less verbose than adding an if (cond) {}
> >> on every type_register_static location.
> >>
> >> Do you have an alternative suggestion that would retain all those
> >> benefits, but would be better in your option?
> >
> > No, I'm not particularly strongly opinionated about the approach,
> > I was just trying to understand the background motivation for it.
> >
>
> It would be more easy if we could expose the patches we have to enable
> the single-binary itself, so people can test and see what is the value
> of current series. However, given reception of such patches in the past,
> we decided to present them as the last piece of puzzle, and not before.
This is the big challege of large work like this.
Saving everything up until a complete solution is done leads to giant
patch series that no one likes reviewing, and potentially wastes effort
if the design took a poor direction before being shared.
Drip-feeding though means the reviewers are evaluating patches without
being able to fully understand how it all goes together, or even how it
interacts with the next incremental chunk of work. Each small series in
isolation may look ok but put together may look undesirable. So it is a
bit like reviewing with a blindfold on.
Doing arm + aarch64 may be simple but also doesn't expose the full
scope of the complexity that two fully separate arches would
experiance given their commonality.
I see there are patches related to riscv64 in flight. Is there a
buildable single binary covering risc64 + aarch64, as that would
be a more compelling demonstration of edge cases and the possible
final state.
With regards,
Daniel
--
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^ permalink raw reply [flat|nested] 56+ messages in thread