* [PATCH 00/11] tcg: Add revbit opcodes
@ 2026-07-31 0:04 Richard Henderson
2026-07-31 0:04 ` [PATCH 01/11] tcg: Fix opcode dump for bswap Richard Henderson
` (11 more replies)
0 siblings, 12 replies; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
Adding these have been at the back of my mind for a while. Most recently
tickled by the Octeon additions, and Anton's helper-to-tcg work.
I didn't add a 16-bit function or opcode because no host implements it.
The 16-bit reverse that the hexagon target does can be implemented with
a 32-bit reverse plus a shift.
r~
Richard Henderson (11):
tcg: Fix opcode dump for bswap
tcg: Add tcg_gen_revbit{32,64}
target/arm: Use generic tcg_gen_revbit*
target/loongarch: Use generic tcg_gen_revbit*
target/loongarch: Expand bitswap inline
target/mips: Expand octeon reflections inline
tcg: Add revbit{32,64} opcodes
tcg/optimize: Handle revbit{32,64}
tcg/aarch64: Implement revbit{32,64}
tcg/loongarch64: Import REVBIT insns
tcg/loongarch64: Implement revbit{32,64}
include/tcg/tcg-op-common.h | 3 +
include/tcg/tcg-op.h | 5 +
include/tcg/tcg-opc.h | 2 +
target/arm/tcg/helper-a64-defs.h | 1 -
target/arm/tcg/helper-defs.h | 1 -
target/loongarch/tcg/helper.h | 4 -
target/mips/helper.h | 7 -
target/arm/tcg/helper-a64.c | 5 -
target/arm/tcg/op_helper.c | 5 -
target/arm/tcg/translate-a64.c | 4 +-
target/arm/tcg/translate.c | 2 +-
target/loongarch/tcg/op_helper.c | 21 -
target/mips/tcg/octeon_crypto.c | 35 -
target/mips/tcg/octeon_translate.c | 49 +-
tcg/optimize.c | 48 +-
tcg/tcg-op.c | 78 ++
tcg/tcg.c | 8 +-
docs/devel/tcg-ops.rst | 11 +
.../loongarch/tcg/insn_trans/trans_bit.c.inc | 29 +-
tcg/aarch64/tcg-target.c.inc | 24 +
tcg/loongarch64/tcg-insn-defs.c.inc | 944 +++++++++---------
tcg/loongarch64/tcg-target.c.inc | 26 +
tcg/ppc64/tcg-target.c.inc | 8 +
tcg/riscv64/tcg-target.c.inc | 8 +
tcg/s390x/tcg-target.c.inc | 8 +
tcg/sparc64/tcg-target.c.inc | 8 +
tcg/tci/tcg-target.c.inc | 8 +
tcg/x86_64/tcg-target.c.inc | 8 +
28 files changed, 787 insertions(+), 573 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 01/11] tcg: Fix opcode dump for bswap
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
@ 2026-07-31 0:04 ` Richard Henderson
2026-08-03 15:08 ` Philippe Mathieu-Daudé
2026-07-31 0:04 ` [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64} Richard Henderson
` (10 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
We use an array of char for bswap_flag_name, so some
entries in the array are non-null but empty. Check that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 1e77f2365a..e023ee8b9a 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2951,7 +2951,7 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
if (flags < ARRAY_SIZE(bswap_flag_name)) {
name = bswap_flag_name[flags];
}
- if (name) {
+ if (name && name[0]) {
col += ne_fprintf(f, ",%s", name);
} else {
col += ne_fprintf(f, ",$0x%" TCG_PRIlx, flags);
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64}
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
2026-07-31 0:04 ` [PATCH 01/11] tcg: Fix opcode dump for bswap Richard Henderson
@ 2026-07-31 0:04 ` Richard Henderson
2026-07-31 6:08 ` Philippe Mathieu-Daudé
` (2 more replies)
2026-07-31 0:04 ` [PATCH 03/11] target/arm: Use generic tcg_gen_revbit* Richard Henderson
` (9 subsequent siblings)
11 siblings, 3 replies; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
Add generic expanders for reversing bits within a word.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op-common.h | 3 ++
include/tcg/tcg-op.h | 5 ++++
tcg/tcg-op.c | 59 +++++++++++++++++++++++++++++++++++++
3 files changed, 67 insertions(+)
diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index 1fe342db0d..91f59dc11e 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -164,6 +164,7 @@ void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_abs_i32(TCGv_i32, TCGv_i32);
+void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg);
/* Replicate a value of size @vece from @in to all the lanes in @out */
void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in);
@@ -275,6 +276,8 @@ void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_abs_i64(TCGv_i64, TCGv_i64);
+void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
+void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg);
/* Replicate a value of size @vece from @in to all the lanes in @out */
void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in);
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 96a5af1a29..401ee21cdf 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -115,6 +115,9 @@ typedef TCGv_i64 TCGv;
#define tcg_gen_bswap_tl tcg_gen_bswap64_i64
#define tcg_gen_hswap_tl tcg_gen_hswap_i64
#define tcg_gen_wswap_tl tcg_gen_wswap_i64
+#define tcg_gen_revbit32_tl tcg_gen_revbit32_i64
+#define tcg_gen_revbit64_tl tcg_gen_revbit64_i64
+#define tcg_gen_revbit_tl tcg_gen_revbit64_i64
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
#define tcg_gen_andc_tl tcg_gen_andc_i64
@@ -234,6 +237,8 @@ typedef TCGv_i64 TCGv;
#define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S)
#define tcg_gen_bswap_tl tcg_gen_bswap32_i32
#define tcg_gen_hswap_tl tcg_gen_hswap_i32
+#define tcg_gen_revbit32_tl(D, S, F) tcg_gen_revbit32_i32(D, S)
+#define tcg_gen_revbit_tl tcg_gen_revbit32_i32
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
#define tcg_gen_andc_tl tcg_gen_andc_i32
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index bbcb510c76..02fb3504b1 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1244,6 +1244,30 @@ void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg)
tcg_gen_rotli_i32(ret, arg, 16);
}
+static void gen_bitswap_i32(TCGv_i32 ret, TCGv_i32 arg, uint32_t mask)
+{
+ TCGv_i32 t0 = tcg_temp_ebb_new_i32();
+ TCGv_i32 t1 = tcg_temp_ebb_new_i32();
+ int sh = cto32(mask);
+
+ tcg_gen_andi_i32(t0, arg, mask);
+ tcg_gen_shri_i32(t1, arg, sh);
+ tcg_gen_shli_i32(t0, t0, sh);
+ tcg_gen_andi_i32(t1, t1, mask);
+ tcg_gen_or_i32(ret, t0, t1);
+
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+}
+
+void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg)
+{
+ gen_bitswap_i32(ret, arg, 0x55555555u);
+ gen_bitswap_i32(ret, ret, 0x33333333u);
+ gen_bitswap_i32(ret, ret, 0x0f0f0f0fu);
+ tcg_gen_bswap32_i32(ret, ret);
+}
+
void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
{
tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b);
@@ -1869,6 +1893,41 @@ void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg)
tcg_gen_rotli_i64(ret, arg, 32);
}
+static void gen_bitswap_i64(TCGv_i64 ret, TCGv_i64 arg, uint64_t mask)
+{
+ TCGv_i64 t0 = tcg_temp_ebb_new_i64();
+ TCGv_i64 t1 = tcg_temp_ebb_new_i64();
+ int sh = cto64(mask);
+
+ tcg_gen_andi_i64(t0, arg, mask);
+ tcg_gen_shri_i64(t1, arg, sh);
+ tcg_gen_shli_i64(t0, t0, sh);
+ tcg_gen_andi_i64(t1, t1, mask);
+ tcg_gen_or_i64(ret, t0, t1);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
+{
+ /* Only one extension flag may be present. */
+ tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));
+
+ gen_bitswap_i64(ret, arg, 0x55555555ull);
+ gen_bitswap_i64(ret, ret, 0x33333333ull);
+ gen_bitswap_i64(ret, ret, 0x0f0f0f0full);
+ tcg_gen_bswap32_i64(ret, ret, flags | TCG_BSWAP_IZ);
+}
+
+void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg)
+{
+ gen_bitswap_i64(ret, arg, 0x5555555555555555ull);
+ gen_bitswap_i64(ret, ret, 0x3333333333333333ull);
+ gen_bitswap_i64(ret, ret, 0x0f0f0f0f0f0f0f0full);
+ tcg_gen_bswap64_i64(ret, ret);
+}
+
void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
{
if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I64, 0)) {
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 03/11] target/arm: Use generic tcg_gen_revbit*
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
2026-07-31 0:04 ` [PATCH 01/11] tcg: Fix opcode dump for bswap Richard Henderson
2026-07-31 0:04 ` [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64} Richard Henderson
@ 2026-07-31 0:04 ` Richard Henderson
2026-07-31 6:08 ` Philippe Mathieu-Daudé
2026-07-31 0:04 ` [PATCH 04/11] target/loongarch: " Richard Henderson
` (8 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/helper-a64-defs.h | 1 -
target/arm/tcg/helper-defs.h | 1 -
target/arm/tcg/helper-a64.c | 5 -----
target/arm/tcg/op_helper.c | 5 -----
target/arm/tcg/translate-a64.c | 4 ++--
target/arm/tcg/translate.c | 2 +-
6 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h
index 0e56e00f45..12f58c6a44 100644
--- a/target/arm/tcg/helper-a64-defs.h
+++ b/target/arm/tcg/helper-a64-defs.h
@@ -18,7 +18,6 @@
*/
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
-DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_2(msr_i_spsel, void, env, i32)
DEF_HELPER_2(msr_i_daifset, void, env, i32)
DEF_HELPER_2(msr_i_daifclear, void, env, i32)
diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h
index 0077aeb4e2..42376af2c6 100644
--- a/target/arm/tcg/helper-defs.h
+++ b/target/arm/tcg/helper-defs.h
@@ -10,7 +10,6 @@ DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32)
DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32)
-DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32)
#define PAS_OP(pfx) \
DEF_HELPER_3(pfx ## add8, i32, i32, i32, ptr) \
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 05ab9ab6d3..9d805231a0 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -69,11 +69,6 @@ int64_t HELPER(sdiv64)(int64_t num, int64_t den)
return num / den;
}
-uint64_t HELPER(rbit64)(uint64_t x)
-{
- return revbit64(x);
-}
-
void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm)
{
update_spsel(env, imm);
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index c4433be2ed..857e897a48 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -172,11 +172,6 @@ uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den)
return num / den;
}
-uint32_t HELPER(rbit)(uint32_t x)
-{
- return revbit32(x);
-}
-
uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a + b;
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 1780490065..4f9a93950b 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8963,7 +8963,7 @@ static void gen_wrap2_i32(TCGv_i64 d, TCGv_i64 n, NeonGenOneOpFn fn)
static void gen_rbit32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
- gen_wrap2_i32(tcg_rd, tcg_rn, gen_helper_rbit);
+ tcg_gen_revbit32_i64(tcg_rd, tcg_rn, TCG_BSWAP_OZ);
}
static void gen_rev16_xx(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 mask)
@@ -8998,7 +8998,7 @@ static void gen_rev32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
tcg_gen_rotri_i64(tcg_rd, tcg_rd, 32);
}
-TRANS(RBIT, gen_rr, a->rd, a->rn, a->sf ? gen_helper_rbit64 : gen_rbit32)
+TRANS(RBIT, gen_rr, a->rd, a->rn, a->sf ? tcg_gen_revbit64_i64 : gen_rbit32)
TRANS(REV16, gen_rr, a->rd, a->rn, a->sf ? gen_rev16_64 : gen_rev16_32)
TRANS(REV32, gen_rr, a->rd, a->rn, a->sf ? gen_rev32 : gen_rev_32)
TRANS(REV64, gen_rr, a->rd, a->rn, tcg_gen_bswap64_i64)
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index a1fc050618..1ee8ac9ffe 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -4811,7 +4811,7 @@ static bool trans_RBIT(DisasContext *s, arg_rr *a)
if (!ENABLE_ARCH_6T2) {
return false;
}
- return op_rr(s, a, gen_helper_rbit);
+ return op_rr(s, a, tcg_gen_revbit32_i32);
}
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 04/11] target/loongarch: Use generic tcg_gen_revbit*
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
` (2 preceding siblings ...)
2026-07-31 0:04 ` [PATCH 03/11] target/arm: Use generic tcg_gen_revbit* Richard Henderson
@ 2026-07-31 0:04 ` Richard Henderson
2026-07-31 6:10 ` Philippe Mathieu-Daudé
2026-08-05 9:16 ` Song Gao
2026-07-31 0:04 ` [PATCH 05/11] target/loongarch: Expand bitswap inline Richard Henderson
` (7 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/tcg/helper.h | 2 --
target/loongarch/tcg/op_helper.c | 10 ----------
target/loongarch/tcg/insn_trans/trans_bit.c.inc | 9 +++++++--
3 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h
index 8a6c62f116..4b0fc81db6 100644
--- a/target/loongarch/tcg/helper.h
+++ b/target/loongarch/tcg/helper.h
@@ -5,8 +5,6 @@
DEF_HELPER_2(raise_exception, noreturn, env, i32)
-DEF_HELPER_FLAGS_1(bitrev_w, TCG_CALL_NO_RWG_SE, tl, tl)
-DEF_HELPER_FLAGS_1(bitrev_d, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_3(asrtle_d, TCG_CALL_NO_WG, void, env, tl, tl)
diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c
index e63ac66daa..37afa8e92d 100644
--- a/target/loongarch/tcg/op_helper.c
+++ b/target/loongarch/tcg/op_helper.c
@@ -22,16 +22,6 @@ void helper_raise_exception(CPULoongArchState *env, uint32_t exception)
do_raise_exception(env, exception, GETPC());
}
-target_ulong helper_bitrev_w(target_ulong rj)
-{
- return (int32_t)revbit32(rj);
-}
-
-target_ulong helper_bitrev_d(target_ulong rj)
-{
- return revbit64(rj);
-}
-
target_ulong helper_bitswap(target_ulong v)
{
v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
diff --git a/target/loongarch/tcg/insn_trans/trans_bit.c.inc b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
index ee5fa003ce..3d24e320ce 100644
--- a/target/loongarch/tcg/insn_trans/trans_bit.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
@@ -178,6 +178,11 @@ static void gen_masknez(TCGv dest, TCGv src1, TCGv src2)
tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, zero, zero, src1);
}
+static void gen_bitrev_w(TCGv dest, TCGv src)
+{
+ tcg_gen_revbit32_tl(dest, src, TCG_BSWAP_OS);
+}
+
TRANS(ext_w_h, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext16s_tl)
TRANS(ext_w_b, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext8s_tl)
TRANS(clo_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w)
@@ -196,8 +201,8 @@ TRANS(revh_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
TRANS(revh_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)
TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)
-TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w)
-TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d)
+TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_bitrev_w)
+TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_revbit64_i64)
TRANS(maskeqz, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
TRANS(masknez, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
TRANS(bytepick_w, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 05/11] target/loongarch: Expand bitswap inline
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
` (3 preceding siblings ...)
2026-07-31 0:04 ` [PATCH 04/11] target/loongarch: " Richard Henderson
@ 2026-07-31 0:04 ` Richard Henderson
2026-08-05 9:17 ` Song Gao
2026-07-31 0:04 ` [PATCH 06/11] target/mips: Expand octeon reflections inline Richard Henderson
` (6 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
The bitrev_[48]b instructions reverse bits within each byte.
This may be accomplished by reversing bits within the entire
word followed by reversing the bytes with the entire word.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/tcg/helper.h | 2 --
target/loongarch/tcg/op_helper.c | 11 ----------
.../loongarch/tcg/insn_trans/trans_bit.c.inc | 20 +++++++++++++++++--
3 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h
index 4b0fc81db6..e76c73c775 100644
--- a/target/loongarch/tcg/helper.h
+++ b/target/loongarch/tcg/helper.h
@@ -5,8 +5,6 @@
DEF_HELPER_2(raise_exception, noreturn, env, i32)
-DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
-
DEF_HELPER_FLAGS_3(asrtle_d, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_3(asrtgt_d, TCG_CALL_NO_WG, void, env, tl, tl)
diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c
index 37afa8e92d..f41f0cb1e6 100644
--- a/target/loongarch/tcg/op_helper.c
+++ b/target/loongarch/tcg/op_helper.c
@@ -22,17 +22,6 @@ void helper_raise_exception(CPULoongArchState *env, uint32_t exception)
do_raise_exception(env, exception, GETPC());
}
-target_ulong helper_bitswap(target_ulong v)
-{
- v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
- ((v & (target_ulong)0x5555555555555555ULL) << 1);
- v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
- ((v & (target_ulong)0x3333333333333333ULL) << 2);
- v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
- ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
- return v;
-}
-
/* loongarch assert op */
void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
{
diff --git a/target/loongarch/tcg/insn_trans/trans_bit.c.inc b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
index 3d24e320ce..1200f931fa 100644
--- a/target/loongarch/tcg/insn_trans/trans_bit.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
@@ -178,6 +178,22 @@ static void gen_masknez(TCGv dest, TCGv src1, TCGv src2)
tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, zero, zero, src1);
}
+static void gen_bitrev_4b(TCGv dest, TCGv src)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_trunc_tl_i32(t, src);
+ tcg_gen_revbit32_i32(t, t);
+ tcg_gen_bswap32_i32(t, t);
+ tcg_gen_ext_i32_tl(dest, t);
+}
+
+static void gen_bitrev_8b(TCGv dest, TCGv src)
+{
+ tcg_gen_revbit_tl(dest, src);
+ tcg_gen_bswap_tl(dest, dest);
+}
+
static void gen_bitrev_w(TCGv dest, TCGv src)
{
tcg_gen_revbit32_tl(dest, src, TCG_BSWAP_OS);
@@ -199,8 +215,8 @@ TRANS(revb_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)
TRANS(revb_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)
TRANS(revh_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
TRANS(revh_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
-TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)
-TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)
+TRANS(bitrev_4b, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_bitrev_4b)
+TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, gen_bitrev_8b)
TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_bitrev_w)
TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_revbit64_i64)
TRANS(maskeqz, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 06/11] target/mips: Expand octeon reflections inline
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
` (4 preceding siblings ...)
2026-07-31 0:04 ` [PATCH 05/11] target/loongarch: Expand bitswap inline Richard Henderson
@ 2026-07-31 0:04 ` Richard Henderson
2026-08-10 11:29 ` Anton Johansson via qemu development
2026-07-31 0:04 ` [PATCH 07/11] tcg: Add revbit{32,64} opcodes Richard Henderson
` (5 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
Use tcg_gen_revbit64_i64 instead of out-of-line helpers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/helper.h | 7 -----
target/mips/tcg/octeon_crypto.c | 35 ---------------------
target/mips/tcg/octeon_translate.c | 49 ++++++++++++++++++++++++++----
3 files changed, 43 insertions(+), 48 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 786117813a..779b87101d 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -27,10 +27,6 @@ DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
/* Octeon COP2 selector operation helpers. */
DEF_HELPER_1(octeon_cp2_mf_crc_iv_reflect, i64, env)
-DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect0, i64, env)
-DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect1, i64, env)
-DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect0, i64, env)
-DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect1, i64, env)
DEF_HELPER_2(octeon_cp2_mt_crc_write_iv_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_polynomial_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_byte, void, env, i64)
@@ -43,9 +39,6 @@ DEF_HELPER_2(octeon_cp2_mt_crc_write_dword, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_var, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_dword_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_var_reflect, void, env, i64)
-DEF_HELPER_2(octeon_cp2_mt_gfm_mul_reflect0, void, env, i64)
-DEF_HELPER_2(octeon_cp2_mt_gfm_mul_reflect1, void, env, i64)
-DEF_HELPER_2(octeon_cp2_mt_gfm_xor0_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1, void, env, i64)
DEF_HELPER_1(octeon_cp2_mt_sha3_startop, void, env)
diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypto.c
index fbf80be2a5..118397e632 100644
--- a/target/mips/tcg/octeon_crypto.c
+++ b/target/mips/tcg/octeon_crypto.c
@@ -2127,41 +2127,6 @@ uint64_t helper_octeon_cp2_mf_crc_iv_reflect(CPUMIPSState *env)
return octeon_crc_reflect32_by_byte(env->octeon_crypto.crc_iv);
}
-uint64_t helper_octeon_cp2_mf_gfm_mul_reflect0(CPUMIPSState *env)
-{
- return revbit64(env->octeon_crypto.gfm_mul[0]);
-}
-
-uint64_t helper_octeon_cp2_mf_gfm_mul_reflect1(CPUMIPSState *env)
-{
- return revbit64(env->octeon_crypto.gfm_mul[1]);
-}
-
-uint64_t helper_octeon_cp2_mf_gfm_resinp_reflect0(CPUMIPSState *env)
-{
- return revbit64(env->octeon_crypto.gfm_resinp[0]);
-}
-
-uint64_t helper_octeon_cp2_mf_gfm_resinp_reflect1(CPUMIPSState *env)
-{
- return revbit64(env->octeon_crypto.gfm_resinp[1]);
-}
-
-void helper_octeon_cp2_mt_gfm_mul_reflect0(CPUMIPSState *env, uint64_t value)
-{
- env->octeon_crypto.gfm_mul[0] = revbit64(value);
-}
-
-void helper_octeon_cp2_mt_gfm_mul_reflect1(CPUMIPSState *env, uint64_t value)
-{
- env->octeon_crypto.gfm_mul[1] = revbit64(value);
-}
-
-void helper_octeon_cp2_mt_gfm_xor0_reflect(CPUMIPSState *env, uint64_t value)
-{
- env->octeon_crypto.gfm_resinp[0] ^= revbit64(value);
-}
-
static void octeon_gfm_xormul1_common(MIPSOcteonCryptoState *crypto,
uint64_t value)
{
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index a0db6630c7..b689adb46b 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -28,6 +28,8 @@
TRANS(NAME, trans_octeon_cp2_mf_hsh_pair, \
OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \
OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1]))
+#define CP2_MF_REFLECT(NAME, FIELD) \
+ TRANS(NAME, trans_octeon_cp2_mf_reflect, OCTEON_CRYPTO_OFFSET(FIELD))
#define CP2_MF_HELPER(NAME, SUFFIX) \
TRANS(NAME, trans_octeon_cp2_mf_helper, \
gen_helper_octeon_cp2_mf_ ## SUFFIX)
@@ -44,6 +46,8 @@
TRANS(NAME, trans_octeon_cp2_mt_hsh_pair, \
OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \
OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1]))
+#define CP2_MT_REFLECT(NAME, FIELD) \
+ TRANS(NAME, trans_octeon_cp2_mt_reflect, OCTEON_CRYPTO_OFFSET(FIELD))
#define CP2_MT_HELPER(NAME, SUFFIX) \
TRANS(NAME, trans_octeon_cp2_mt_helper, \
gen_helper_octeon_cp2_mt_ ## SUFFIX)
@@ -110,6 +114,17 @@ static bool trans_octeon_cp2_mf_hsh_pair(DisasContext *ctx, arg_cp2 *a,
return true;
}
+static bool trans_octeon_cp2_mf_reflect(DisasContext *ctx, arg_cp2 *a,
+ int offset)
+{
+ TCGv_i64 value = tcg_temp_new_i64();
+
+ tcg_gen_ld_i64(value, tcg_env, offset);
+ tcg_gen_revbit64_i64(value, value);
+ gen_store_gpr(value, a->rt);
+ return true;
+}
+
static bool trans_octeon_cp2_mf_helper(DisasContext *ctx, arg_cp2 *a,
void (*gen_helper)(TCGv_i64, TCGv_env))
{
@@ -183,6 +198,17 @@ static bool trans_octeon_cp2_mt_xor_i64(DisasContext *ctx, arg_cp2 *a,
return true;
}
+static bool trans_octeon_cp2_mt_reflect(DisasContext *ctx, arg_cp2 *a,
+ int offset)
+{
+ TCGv_i64 value = tcg_temp_new_i64();
+
+ gen_load_gpr(value, a->rt);
+ tcg_gen_revbit64_i64(value, value);
+ tcg_gen_st_i64(value, tcg_env, offset);
+ return true;
+}
+
static bool trans_octeon_cp2_mt_helper(DisasContext *ctx, arg_cp2 *a,
void (*gen_helper)(TCGv_env, TCGv_i64))
{
@@ -200,6 +226,17 @@ static bool trans_octeon_cp2_mt_helper_env(DisasContext *ctx, arg_cp2 *a,
return true;
}
+static void gen_helper_octeon_cp2_mt_gfm_xor0_reflect(TCGv_env t_env,
+ TCGv_i64 value)
+{
+ TCGv_i64 resinp = tcg_temp_new_i64();
+
+ tcg_gen_revbit64_i64(value, value);
+ tcg_gen_ld_i64(resinp, t_env, OCTEON_CRYPTO_OFFSET(gfm_resinp[0]));
+ tcg_gen_xor_i64(resinp, resinp, value);
+ tcg_gen_st_i64(resinp, t_env, OCTEON_CRYPTO_OFFSET(gfm_resinp[0]));
+}
+
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT0, hsh_dat, 0);
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT1, hsh_dat, 1);
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT2, hsh_dat, 2);
@@ -241,10 +278,10 @@ CP2_MF_I64(CVM_MF_LLM_DATA1, llm_data[1]);
CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect);
CP2_MF_I64(CVM_MF_SHA3_DAT24, sha3_dat24);
-CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT0, gfm_mul_reflect0);
-CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT1, gfm_mul_reflect1);
-CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT0, gfm_resinp_reflect0);
-CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT1, gfm_resinp_reflect1);
+CP2_MF_REFLECT(CVM_MF_GFM_MUL_REFLECT0, gfm_mul[0])
+CP2_MF_REFLECT(CVM_MF_GFM_MUL_REFLECT1, gfm_mul[1])
+CP2_MF_REFLECT(CVM_MF_GFM_RESINP_REFLECT0, gfm_resinp[0])
+CP2_MF_REFLECT(CVM_MF_GFM_RESINP_REFLECT1, gfm_resinp[1])
CP2_MF_I64(CVM_MF_HSH_DATW0, hsh_dat[0]);
CP2_MF_I64(CVM_MF_HSH_DATW1, hsh_dat[1]);
CP2_MF_I64(CVM_MF_HSH_DATW2, hsh_dat[2]);
@@ -281,8 +318,8 @@ CP2_MT_HSH_PAIR(CVM_MT_HSH_IV0, hsh_iv, 0);
CP2_MT_HSH_PAIR(CVM_MT_HSH_IV1, hsh_iv, 1);
CP2_MT_HSH_PAIR(CVM_MT_HSH_IV2, hsh_iv, 2);
CP2_MT_HSH_PAIR(CVM_MT_HSH_IV3, hsh_iv, 3);
-CP2_MT_HELPER(CVM_MT_GFM_MUL_REFLECT0, gfm_mul_reflect0);
-CP2_MT_HELPER(CVM_MT_GFM_MUL_REFLECT1, gfm_mul_reflect1);
+CP2_MT_REFLECT(CVM_MT_GFM_MUL_REFLECT0, gfm_mul[0]);
+CP2_MT_REFLECT(CVM_MT_GFM_MUL_REFLECT1, gfm_mul[1]);
CP2_MT_HELPER(CVM_MT_GFM_XOR0_REFLECT, gfm_xor0_reflect);
CP2_MT_I64(CVM_MT_3DES_KEY0, des3_key[0]);
CP2_MT_I64(CVM_MT_3DES_KEY1, des3_key[1]);
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 07/11] tcg: Add revbit{32,64} opcodes
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
` (5 preceding siblings ...)
2026-07-31 0:04 ` [PATCH 06/11] target/mips: Expand octeon reflections inline Richard Henderson
@ 2026-07-31 0:04 ` Richard Henderson
2026-07-31 7:02 ` Philippe Mathieu-Daudé
2026-08-10 12:15 ` Anton Johansson via
2026-07-31 0:05 ` [PATCH 08/11] tcg/optimize: Handle revbit{32,64} Richard Henderson
` (4 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
Add the plumbing, but not yet implemented for any host.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-opc.h | 2 ++
tcg/tcg-op.c | 43 +++++++++++++++++++++++---------
tcg/tcg.c | 6 +++++
docs/devel/tcg-ops.rst | 11 ++++++++
tcg/aarch64/tcg-target.c.inc | 8 ++++++
tcg/loongarch64/tcg-target.c.inc | 8 ++++++
tcg/ppc64/tcg-target.c.inc | 8 ++++++
tcg/riscv64/tcg-target.c.inc | 8 ++++++
tcg/s390x/tcg-target.c.inc | 8 ++++++
tcg/sparc64/tcg-target.c.inc | 8 ++++++
tcg/tci/tcg-target.c.inc | 8 ++++++
tcg/x86_64/tcg-target.c.inc | 8 ++++++
12 files changed, 114 insertions(+), 12 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 61f1c28858..ca2077733e 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -79,6 +79,8 @@ DEF(or, 1, 2, 0, TCG_OPF_INT)
DEF(orc, 1, 2, 0, TCG_OPF_INT)
DEF(rems, 1, 2, 0, TCG_OPF_INT)
DEF(remu, 1, 2, 0, TCG_OPF_INT)
+DEF(revbit32, 1, 1, 1, TCG_OPF_INT)
+DEF(revbit64, 1, 1, 1, TCG_OPF_INT)
DEF(rotl, 1, 2, 0, TCG_OPF_INT)
DEF(rotr, 1, 2, 0, TCG_OPF_INT)
DEF(sar, 1, 2, 0, TCG_OPF_INT)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 02fb3504b1..04d5e15167 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1262,10 +1262,14 @@ static void gen_bitswap_i32(TCGv_i32 ret, TCGv_i32 arg, uint32_t mask)
void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg)
{
- gen_bitswap_i32(ret, arg, 0x55555555u);
- gen_bitswap_i32(ret, ret, 0x33333333u);
- gen_bitswap_i32(ret, ret, 0x0f0f0f0fu);
- tcg_gen_bswap32_i32(ret, ret);
+ if (tcg_op_supported(INDEX_op_revbit32, TCG_TYPE_I32, 0)) {
+ tcg_gen_op3i_i32(INDEX_op_revbit32, ret, arg, 0);
+ } else {
+ gen_bitswap_i32(ret, arg, 0x55555555u);
+ gen_bitswap_i32(ret, ret, 0x33333333u);
+ gen_bitswap_i32(ret, ret, 0x0f0f0f0fu);
+ tcg_gen_bswap32_i32(ret, ret);
+ }
}
void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
@@ -1914,18 +1918,33 @@ void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
/* Only one extension flag may be present. */
tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));
- gen_bitswap_i64(ret, arg, 0x55555555ull);
- gen_bitswap_i64(ret, ret, 0x33333333ull);
- gen_bitswap_i64(ret, ret, 0x0f0f0f0full);
- tcg_gen_bswap32_i64(ret, ret, flags | TCG_BSWAP_IZ);
+ if (tcg_op_supported(INDEX_op_revbit32, TCG_TYPE_I64, 0)) {
+ tcg_gen_op3i_i64(INDEX_op_revbit32, ret, arg, flags);
+ } else if (tcg_op_supported(INDEX_op_revbit64, TCG_TYPE_I64, 0)) {
+ tcg_gen_op3i_i64(INDEX_op_revbit64, ret, arg, 0);
+ if (flags & TCG_BSWAP_OS) {
+ tcg_gen_sari_i64(ret, ret, 32);
+ } else {
+ tcg_gen_shri_i64(ret, ret, 32);
+ }
+ } else {
+ gen_bitswap_i64(ret, arg, 0x55555555ull);
+ gen_bitswap_i64(ret, ret, 0x33333333ull);
+ gen_bitswap_i64(ret, ret, 0x0f0f0f0full);
+ tcg_gen_bswap32_i64(ret, ret, flags | TCG_BSWAP_IZ);
+ }
}
void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg)
{
- gen_bitswap_i64(ret, arg, 0x5555555555555555ull);
- gen_bitswap_i64(ret, ret, 0x3333333333333333ull);
- gen_bitswap_i64(ret, ret, 0x0f0f0f0f0f0f0f0full);
- tcg_gen_bswap64_i64(ret, ret);
+ if (tcg_op_supported(INDEX_op_revbit64, TCG_TYPE_I64, 0)) {
+ tcg_gen_op3i_i64(INDEX_op_revbit64, ret, arg, 0);
+ } else {
+ gen_bitswap_i64(ret, arg, 0x5555555555555555ull);
+ gen_bitswap_i64(ret, ret, 0x3333333333333333ull);
+ gen_bitswap_i64(ret, ret, 0x0f0f0f0f0f0f0f0full);
+ tcg_gen_bswap64_i64(ret, ret);
+ }
}
void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index e023ee8b9a..c2eb591f86 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1203,6 +1203,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_qemu_st2, TCGOutOpQemuLdSt2, outop_qemu_st2),
OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems),
OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu),
+ OUTOP(INDEX_op_revbit32, TCGOutOpBswap, outop_revbit32),
OUTOP(INDEX_op_rotl, TCGOutOpBinary, outop_rotl),
OUTOP(INDEX_op_rotr, TCGOutOpBinary, outop_rotr),
OUTOP(INDEX_op_sar, TCGOutOpBinary, outop_sar),
@@ -1230,6 +1231,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_extrh_i64_i32, TCGOutOpUnary, outop_extrh_i64_i32),
OUTOP(INDEX_op_ld32u, TCGOutOpLoad, outop_ld32u),
OUTOP(INDEX_op_ld32s, TCGOutOpLoad, outop_ld32s),
+ OUTOP(INDEX_op_revbit64, TCGOutOpUnary, outop_revbit64),
OUTOP(INDEX_op_st32, TCGOutOpStore, outop_st),
};
@@ -2944,6 +2946,8 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
case INDEX_op_bswap16:
case INDEX_op_bswap32:
case INDEX_op_bswap64:
+ case INDEX_op_revbit32:
+ case INDEX_op_revbit64:
{
TCGArg flags = op->args[k];
const char *name = NULL;
@@ -5575,6 +5579,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_ctpop:
case INDEX_op_neg:
case INDEX_op_not:
+ case INDEX_op_revbit64:
{
const TCGOutOpUnary *out =
container_of(all_outop[op->opc], TCGOutOpUnary, base);
@@ -5587,6 +5592,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_bswap16:
case INDEX_op_bswap32:
+ case INDEX_op_revbit32:
{
const TCGOutOpBswap *out =
container_of(all_outop[op->opc], TCGOutOpBswap, base);
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
index 92ef127c80..1b3a2618b6 100644
--- a/docs/devel/tcg-ops.rst
+++ b/docs/devel/tcg-ops.rst
@@ -495,6 +495,17 @@ Misc
into 32-bit output *t0*. Depending on the host, this may be a simple shift,
or may require additional canonicalization.
+ * - revbit32 *t0*, *t1*, *flags*
+
+ - | 32 bit bit reverse. The flags are the same as for bswap32.
+ On TCG_TYPE_I32, the flags should be zero.
+
+ * - revbit64 *t0*, *t1*, *flags*
+
+ - | 64 bit bit reverse. The flags are ignored, but still present
+ for consistency with the other revbit opcodes. For future
+ compatibility, the flags should be zero.
+
Conditional moves
-----------------
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index cc9c2a5158..aa2c4e42ed 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2652,6 +2652,14 @@ static const TCGOutOpUnary outop_bswap64 = {
.out_rr = tgen_bswap64,
};
+static const TCGOutOpBswap outop_revbit32 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
+static const TCGOutOpUnary outop_revbit64 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_XZR, a1);
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 182dcfd5eb..a5cd3c3b1e 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1866,6 +1866,14 @@ static const TCGOutOpUnary outop_bswap64 = {
.out_rr = tgen_bswap64,
};
+static const TCGOutOpBswap outop_revbit32 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
+static const TCGOutOpUnary outop_revbit64 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
diff --git a/tcg/ppc64/tcg-target.c.inc b/tcg/ppc64/tcg-target.c.inc
index b54afa0b6d..a9a41ebd4f 100644
--- a/tcg/ppc64/tcg-target.c.inc
+++ b/tcg/ppc64/tcg-target.c.inc
@@ -3421,6 +3421,14 @@ static const TCGOutOpUnary outop_bswap64 = {
.out_rr = tgen_bswap64,
};
+static const TCGOutOpBswap outop_revbit32 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
+static const TCGOutOpUnary outop_revbit64 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out32(s, NEG | RT(a0) | RA(a1));
diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc
index 76dd4fca97..4ebbe24774 100644
--- a/tcg/riscv64/tcg-target.c.inc
+++ b/tcg/riscv64/tcg-target.c.inc
@@ -2469,6 +2469,14 @@ static const TCGOutOpUnary outop_bswap64 = {
.out_rr = tgen_bswap64,
};
+static const TCGOutOpBswap outop_revbit32 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
+static const TCGOutOpUnary outop_revbit64 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_ZERO, a1);
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 84a9e73a46..10b9dcb0cf 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -3020,6 +3020,14 @@ static const TCGOutOpUnary outop_bswap64 = {
.out_rr = tgen_bswap64,
};
+static const TCGOutOpBswap outop_revbit32 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
+static const TCGOutOpUnary outop_revbit64 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
if (type == TCG_TYPE_I32) {
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 5e5c3f1cda..d22c1bd566 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -1947,6 +1947,14 @@ static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_NotImplemented,
};
+static const TCGOutOpBswap outop_revbit32 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
+static const TCGOutOpUnary outop_revbit64 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tgen_sub(s, type, a0, TCG_REG_G0, a1);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 1b22c70616..e8b82a0c85 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -959,6 +959,14 @@ static const TCGOutOpUnary outop_bswap64 = {
.out_rr = tgen_bswap64,
};
+static const TCGOutOpBswap outop_revbit32 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
+static const TCGOutOpUnary outop_revbit64 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
tcg_out_op_rr(s, INDEX_op_neg, a0, a1);
diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc
index 1fc45e4ec6..70fec08c4c 100644
--- a/tcg/x86_64/tcg-target.c.inc
+++ b/tcg/x86_64/tcg-target.c.inc
@@ -1290,6 +1290,14 @@ static inline void tcg_out_bswap64(TCGContext *s, int reg)
tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0);
}
+static const TCGOutOpBswap outop_revbit32 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
+static const TCGOutOpUnary outop_revbit64 = {
+ .base.static_constraint = C_NotImplemented,
+};
+
static void tgen_arithi(TCGContext *s, int c, int r0,
tcg_target_long val, int cf)
{
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 08/11] tcg/optimize: Handle revbit{32,64}
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
` (6 preceding siblings ...)
2026-07-31 0:04 ` [PATCH 07/11] tcg: Add revbit{32,64} opcodes Richard Henderson
@ 2026-07-31 0:05 ` Richard Henderson
2026-08-03 14:58 ` Philippe Mathieu-Daudé
2026-08-10 10:44 ` Anton Johansson via qemu development
2026-07-31 0:05 ` [PATCH 09/11] tcg/aarch64: Implement revbit{32,64} Richard Henderson
` (3 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:05 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
These are nearly identical to bswap, so reuse fold_bswap.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 48 +++++++++++++++++++++++++-----------------------
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index fcdef25bee..49242bdacb 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -534,6 +534,13 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
case INDEX_op_bswap64:
return bswap64(x);
+ case INDEX_op_revbit32:
+ x = revbit32(x);
+ return y & TCG_BSWAP_OS ? (int32_t)x : x;
+
+ case INDEX_op_revbit64:
+ return revbit64(x);
+
case INDEX_op_ext_i32_i64:
return (int32_t)x;
@@ -1491,41 +1498,34 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
ti_const_val(t1), flags));
}
- z_mask = t1->z_mask;
- o_mask = t1->o_mask;
- s_mask = 0;
+ z_mask = do_constant_folding(op->opc, ctx->type, t1->z_mask, flags);
+ o_mask = do_constant_folding(op->opc, ctx->type, t1->o_mask, flags);
switch (op->opc) {
case INDEX_op_bswap16:
- z_mask = bswap16(z_mask);
- o_mask = bswap16(o_mask);
- if (flags & TCG_BSWAP_OS) {
- z_mask = (int16_t)z_mask;
- o_mask = (int16_t)o_mask;
- s_mask = INT16_MIN;
- } else if (!(flags & TCG_BSWAP_OZ)) {
- z_mask |= MAKE_64BIT_MASK(16, 48);
- }
+ s_mask = INT16_MIN;
break;
case INDEX_op_bswap32:
- z_mask = bswap32(z_mask);
- o_mask = bswap32(o_mask);
- if (flags & TCG_BSWAP_OS) {
- z_mask = (int32_t)z_mask;
- o_mask = (int32_t)o_mask;
- s_mask = INT32_MIN;
- } else if (!(flags & TCG_BSWAP_OZ)) {
- z_mask |= MAKE_64BIT_MASK(32, 32);
- }
+ case INDEX_op_revbit32:
+ s_mask = INT32_MIN;
break;
case INDEX_op_bswap64:
- z_mask = bswap64(z_mask);
- o_mask = bswap64(o_mask);
+ case INDEX_op_revbit64:
+ s_mask = 0;
break;
default:
g_assert_not_reached();
}
+ if (flags & TCG_BSWAP_OS) {
+ /* s_mask set */
+ } else {
+ if (!(flags & TCG_BSWAP_OZ)) {
+ z_mask |= s_mask << 1;
+ }
+ s_mask = 0;
+ }
+
return fold_masks_zos(ctx, op, z_mask, o_mask, s_mask);
}
@@ -3095,6 +3095,8 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_bswap16:
case INDEX_op_bswap32:
case INDEX_op_bswap64:
+ case INDEX_op_revbit32:
+ case INDEX_op_revbit64:
done = fold_bswap(&ctx, op);
break;
case INDEX_op_clz:
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 09/11] tcg/aarch64: Implement revbit{32,64}
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
` (7 preceding siblings ...)
2026-07-31 0:05 ` [PATCH 08/11] tcg/optimize: Handle revbit{32,64} Richard Henderson
@ 2026-07-31 0:05 ` Richard Henderson
2026-07-31 7:12 ` Philippe Mathieu-Daudé
2026-07-31 0:05 ` [PATCH 10/11] tcg/loongarch64: Import REVBIT insns Richard Henderson
` (2 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:05 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index aa2c4e42ed..2622f89880 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2652,12 +2652,28 @@ static const TCGOutOpUnary outop_bswap64 = {
.out_rr = tgen_bswap64,
};
+static void tgen_revbit32(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, unsigned flags)
+{
+ tcg_out_insn(s, rr_sf, RBIT, TCG_TYPE_I32, a0, a1);
+ if (flags & TCG_BSWAP_OS) {
+ tcg_out_ext32s(s, a0, a0);
+ }
+}
+
static const TCGOutOpBswap outop_revbit32 = {
- .base.static_constraint = C_NotImplemented,
+ .base.static_constraint = C_O1_I1(r, r),
+ .out_rr = tgen_revbit32,
};
+static void tgen_revbit64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
+{
+ tcg_out_insn(s, rr_sf, RBIT, TCG_TYPE_I64, a0, a1);
+}
+
static const TCGOutOpUnary outop_revbit64 = {
- .base.static_constraint = C_NotImplemented,
+ .base.static_constraint = C_O1_I1(r, r),
+ .out_rr = tgen_revbit64,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 10/11] tcg/loongarch64: Import REVBIT insns
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
` (8 preceding siblings ...)
2026-07-31 0:05 ` [PATCH 09/11] tcg/aarch64: Implement revbit{32,64} Richard Henderson
@ 2026-07-31 0:05 ` Richard Henderson
2026-08-03 15:06 ` Philippe Mathieu-Daudé
2026-07-31 0:05 ` [PATCH 11/11] tcg/loongarch64: Implement revbit{32,64} Richard Henderson
2026-08-10 10:46 ` Anton Johansson via
11 siblings, 1 reply; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:05 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-insn-defs.c.inc | 944 ++++++++++++++--------------
1 file changed, 487 insertions(+), 457 deletions(-)
diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-insn-defs.c.inc
index 6bb8656fd8..c308b770ef 100644
--- a/tcg/loongarch64/tcg-insn-defs.c.inc
+++ b/tcg/loongarch64/tcg-insn-defs.c.inc
@@ -4,7 +4,7 @@
*
* This file is auto-generated by genqemutcgdefs from
* https://github.com/loongson-community/loongarch-opcodes,
- * from commit 7f353fb69bd99ce6edfad7ad63948c4bb526f0bf.
+ * from commit 40ea52087699392ad911387b666541891d33da31.
* DO NOT EDIT.
*/
@@ -18,6 +18,8 @@ typedef enum {
OPC_REVB_2H = 0x00003000,
OPC_REVB_2W = 0x00003800,
OPC_REVB_D = 0x00003c00,
+ OPC_REVBIT_W = 0x00005000,
+ OPC_REVBIT_D = 0x00005400,
OPC_SEXT_H = 0x00005800,
OPC_SEXT_B = 0x00005c00,
OPC_ADD_W = 0x00100000,
@@ -545,14 +547,14 @@ typedef enum {
OPC_XVLDI = 0x77e00000,
} LoongArchInsn;
-static int32_t __attribute__((unused))
-encode_d_slot(LoongArchInsn opc, uint32_t d)
+static int32_t __attribute__((unused)) encode_d_slot(LoongArchInsn opc,
+ uint32_t d)
{
return opc | d;
}
-static int32_t __attribute__((unused))
-encode_dj_slots(LoongArchInsn opc, uint32_t d, uint32_t j)
+static int32_t __attribute__((unused)) encode_dj_slots(LoongArchInsn opc,
+ uint32_t d, uint32_t j)
{
return opc | d | j << 5;
}
@@ -563,43 +565,43 @@ encode_djk_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k)
return opc | d | j << 5 | k << 10;
}
-static int32_t __attribute__((unused))
-encode_djka_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k,
- uint32_t a)
+static int32_t __attribute__((unused)) encode_djka_slots(LoongArchInsn opc,
+ uint32_t d, uint32_t j,
+ uint32_t k, uint32_t a)
{
return opc | d | j << 5 | k << 10 | a << 15;
}
-static int32_t __attribute__((unused))
-encode_djkm_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k,
- uint32_t m)
+static int32_t __attribute__((unused)) encode_djkm_slots(LoongArchInsn opc,
+ uint32_t d, uint32_t j,
+ uint32_t k, uint32_t m)
{
return opc | d | j << 5 | k << 10 | m << 16;
}
-static int32_t __attribute__((unused))
-encode_djkn_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k,
- uint32_t n)
+static int32_t __attribute__((unused)) encode_djkn_slots(LoongArchInsn opc,
+ uint32_t d, uint32_t j,
+ uint32_t k, uint32_t n)
{
return opc | d | j << 5 | k << 10 | n << 18;
}
-static int32_t __attribute__((unused))
-encode_dk_slots(LoongArchInsn opc, uint32_t d, uint32_t k)
+static int32_t __attribute__((unused)) encode_dk_slots(LoongArchInsn opc,
+ uint32_t d, uint32_t k)
{
return opc | d | k << 10;
}
-static int32_t __attribute__((unused))
-encode_dfj_insn(LoongArchInsn opc, TCGReg d, TCGReg fj)
+static int32_t __attribute__((unused)) encode_dfj_insn(LoongArchInsn opc,
+ TCGReg d, TCGReg fj)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(fj >= 0x20 && fj <= 0x3f);
return encode_dj_slots(opc, d, fj & 0x1f);
}
-static int32_t __attribute__((unused))
-encode_dj_insn(LoongArchInsn opc, TCGReg d, TCGReg j)
+static int32_t __attribute__((unused)) encode_dj_insn(LoongArchInsn opc,
+ TCGReg d, TCGReg j)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
@@ -669,9 +671,10 @@ encode_djuk5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk5)
return encode_djk_slots(opc, d, j, uk5);
}
-static int32_t __attribute__((unused))
-encode_djuk5um5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk5,
- uint32_t um5)
+static int32_t __attribute__((unused)) encode_djuk5um5_insn(LoongArchInsn opc,
+ TCGReg d, TCGReg j,
+ uint32_t uk5,
+ uint32_t um5)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
@@ -689,9 +692,10 @@ encode_djuk6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk6)
return encode_djk_slots(opc, d, j, uk6);
}
-static int32_t __attribute__((unused))
-encode_djuk6um6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk6,
- uint32_t um6)
+static int32_t __attribute__((unused)) encode_djuk6um6_insn(LoongArchInsn opc,
+ TCGReg d, TCGReg j,
+ uint32_t uk6,
+ uint32_t um6)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
@@ -700,16 +704,16 @@ encode_djuk6um6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk6,
return encode_djkm_slots(opc, d, j, uk6, um6);
}
-static int32_t __attribute__((unused))
-encode_dsj20_insn(LoongArchInsn opc, TCGReg d, int32_t sj20)
+static int32_t __attribute__((unused)) encode_dsj20_insn(LoongArchInsn opc,
+ TCGReg d, int32_t sj20)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(sj20 >= -0x80000 && sj20 <= 0x7ffff);
return encode_dj_slots(opc, d, sj20 & 0xfffff);
}
-static int32_t __attribute__((unused))
-encode_dtj_insn(LoongArchInsn opc, TCGReg d, TCGReg tj)
+static int32_t __attribute__((unused)) encode_dtj_insn(LoongArchInsn opc,
+ TCGReg d, TCGReg tj)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(tj >= 0 && tj <= 0x3);
@@ -770,16 +774,16 @@ encode_dxjuk3_insn(LoongArchInsn opc, TCGReg d, TCGReg xj, uint32_t uk3)
return encode_djk_slots(opc, d, xj & 0x1f, uk3);
}
-static int32_t __attribute__((unused))
-encode_fdfj_insn(LoongArchInsn opc, TCGReg fd, TCGReg fj)
+static int32_t __attribute__((unused)) encode_fdfj_insn(LoongArchInsn opc,
+ TCGReg fd, TCGReg fj)
{
tcg_debug_assert(fd >= 0x20 && fd <= 0x3f);
tcg_debug_assert(fj >= 0x20 && fj <= 0x3f);
return encode_dj_slots(opc, fd & 0x1f, fj & 0x1f);
}
-static int32_t __attribute__((unused))
-encode_fdj_insn(LoongArchInsn opc, TCGReg fd, TCGReg j)
+static int32_t __attribute__((unused)) encode_fdj_insn(LoongArchInsn opc,
+ TCGReg fd, TCGReg j)
{
tcg_debug_assert(fd >= 0x20 && fd <= 0x3f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
@@ -804,37 +808,37 @@ encode_fdjsk12_insn(LoongArchInsn opc, TCGReg fd, TCGReg j, int32_t sk12)
return encode_djk_slots(opc, fd & 0x1f, j, sk12 & 0xfff);
}
-static int32_t __attribute__((unused))
-encode_sd10k16_insn(LoongArchInsn opc, int32_t sd10k16)
+static int32_t __attribute__((unused)) encode_sd10k16_insn(LoongArchInsn opc,
+ int32_t sd10k16)
{
tcg_debug_assert(sd10k16 >= -0x2000000 && sd10k16 <= 0x1ffffff);
return encode_dk_slots(opc, (sd10k16 >> 16) & 0x3ff, sd10k16 & 0xffff);
}
-static int32_t __attribute__((unused))
-encode_sd5k16_insn(LoongArchInsn opc, int32_t sd5k16)
+static int32_t __attribute__((unused)) encode_sd5k16_insn(LoongArchInsn opc,
+ int32_t sd5k16)
{
tcg_debug_assert(sd5k16 >= -0x100000 && sd5k16 <= 0xfffff);
return encode_dk_slots(opc, (sd5k16 >> 16) & 0x1f, sd5k16 & 0xffff);
}
-static int32_t __attribute__((unused))
-encode_tdj_insn(LoongArchInsn opc, TCGReg td, TCGReg j)
+static int32_t __attribute__((unused)) encode_tdj_insn(LoongArchInsn opc,
+ TCGReg td, TCGReg j)
{
tcg_debug_assert(td >= 0 && td <= 0x3);
tcg_debug_assert(j >= 0 && j <= 0x1f);
return encode_dj_slots(opc, td, j);
}
-static int32_t __attribute__((unused))
-encode_ud15_insn(LoongArchInsn opc, uint32_t ud15)
+static int32_t __attribute__((unused)) encode_ud15_insn(LoongArchInsn opc,
+ uint32_t ud15)
{
tcg_debug_assert(ud15 <= 0x7fff);
return encode_d_slot(opc, ud15);
}
-static int32_t __attribute__((unused))
-encode_vdj_insn(LoongArchInsn opc, TCGReg vd, TCGReg j)
+static int32_t __attribute__((unused)) encode_vdj_insn(LoongArchInsn opc,
+ TCGReg vd, TCGReg j)
{
tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
@@ -974,8 +978,8 @@ encode_vdsj13_insn(LoongArchInsn opc, TCGReg vd, int32_t sj13)
return encode_dj_slots(opc, vd & 0x1f, sj13 & 0x1fff);
}
-static int32_t __attribute__((unused))
-encode_vdvj_insn(LoongArchInsn opc, TCGReg vd, TCGReg vj)
+static int32_t __attribute__((unused)) encode_vdvj_insn(LoongArchInsn opc,
+ TCGReg vd, TCGReg vj)
{
tcg_debug_assert(vd >= 0x20 && vd <= 0x3f);
tcg_debug_assert(vj >= 0x20 && vj <= 0x3f);
@@ -1083,8 +1087,8 @@ encode_vdvjvkva_insn(LoongArchInsn opc, TCGReg vd, TCGReg vj, TCGReg vk,
return encode_djka_slots(opc, vd & 0x1f, vj & 0x1f, vk & 0x1f, va & 0x1f);
}
-static int32_t __attribute__((unused))
-encode_xdj_insn(LoongArchInsn opc, TCGReg xd, TCGReg j)
+static int32_t __attribute__((unused)) encode_xdj_insn(LoongArchInsn opc,
+ TCGReg xd, TCGReg j)
{
tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
@@ -1206,8 +1210,8 @@ encode_xdsj13_insn(LoongArchInsn opc, TCGReg xd, int32_t sj13)
return encode_dj_slots(opc, xd & 0x1f, sj13 & 0x1fff);
}
-static int32_t __attribute__((unused))
-encode_xdxj_insn(LoongArchInsn opc, TCGReg xd, TCGReg xj)
+static int32_t __attribute__((unused)) encode_xdxj_insn(LoongArchInsn opc,
+ TCGReg xd, TCGReg xj)
{
tcg_debug_assert(xd >= 0x20 && xd <= 0x3f);
tcg_debug_assert(xj >= 0x20 && xj <= 0x3f);
@@ -1316,523 +1320,541 @@ encode_xdxjxkxa_insn(LoongArchInsn opc, TCGReg xd, TCGReg xj, TCGReg xk,
}
/* Emits the `movgr2scr td, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_movgr2scr(TCGContext *s, TCGReg td, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_movgr2scr(TCGContext *s,
+ TCGReg td, TCGReg j)
{
tcg_out32(s, encode_tdj_insn(OPC_MOVGR2SCR, td, j));
}
/* Emits the `movscr2gr d, tj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_movscr2gr(TCGContext *s, TCGReg d, TCGReg tj)
+static void __attribute__((unused)) tcg_out_opc_movscr2gr(TCGContext *s,
+ TCGReg d, TCGReg tj)
{
tcg_out32(s, encode_dtj_insn(OPC_MOVSCR2GR, d, tj));
}
/* Emits the `clz.w d, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_clz_w(TCGContext *s, TCGReg d, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_clz_w(TCGContext *s, TCGReg d,
+ TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_CLZ_W, d, j));
}
/* Emits the `ctz.w d, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ctz_w(TCGContext *s, TCGReg d, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_ctz_w(TCGContext *s, TCGReg d,
+ TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_CTZ_W, d, j));
}
/* Emits the `clz.d d, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_clz_d(TCGContext *s, TCGReg d, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_clz_d(TCGContext *s, TCGReg d,
+ TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_CLZ_D, d, j));
}
/* Emits the `ctz.d d, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ctz_d(TCGContext *s, TCGReg d, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_ctz_d(TCGContext *s, TCGReg d,
+ TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_CTZ_D, d, j));
}
/* Emits the `revb.2h d, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_revb_2h(TCGContext *s, TCGReg d, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_revb_2h(TCGContext *s, TCGReg d,
+ TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_REVB_2H, d, j));
}
/* Emits the `revb.2w d, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_revb_2w(TCGContext *s, TCGReg d, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_revb_2w(TCGContext *s, TCGReg d,
+ TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_REVB_2W, d, j));
}
/* Emits the `revb.d d, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_revb_d(TCGContext *s, TCGReg d, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_revb_d(TCGContext *s, TCGReg d,
+ TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_REVB_D, d, j));
}
+/* Emits the `revbit.w d, j` instruction. */
+static void __attribute__((unused)) tcg_out_opc_revbit_w(TCGContext *s,
+ TCGReg d, TCGReg j)
+{
+ tcg_out32(s, encode_dj_insn(OPC_REVBIT_W, d, j));
+}
+
+/* Emits the `revbit.d d, j` instruction. */
+static void __attribute__((unused)) tcg_out_opc_revbit_d(TCGContext *s,
+ TCGReg d, TCGReg j)
+{
+ tcg_out32(s, encode_dj_insn(OPC_REVBIT_D, d, j));
+}
+
/* Emits the `sext.h d, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_sext_h(TCGContext *s, TCGReg d, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_sext_h(TCGContext *s, TCGReg d,
+ TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_SEXT_H, d, j));
}
/* Emits the `sext.b d, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_sext_b(TCGContext *s, TCGReg d, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_sext_b(TCGContext *s, TCGReg d,
+ TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_SEXT_B, d, j));
}
/* Emits the `add.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_add_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_add_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ADD_W, d, j, k));
}
/* Emits the `add.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_add_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_add_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ADD_D, d, j, k));
}
/* Emits the `sub.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_sub_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_sub_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SUB_W, d, j, k));
}
/* Emits the `sub.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_sub_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_sub_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SUB_D, d, j, k));
}
/* Emits the `slt d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_slt(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_slt(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SLT, d, j, k));
}
/* Emits the `sltu d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_sltu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_sltu(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SLTU, d, j, k));
}
/* Emits the `maskeqz d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_maskeqz(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_maskeqz(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MASKEQZ, d, j, k));
}
/* Emits the `masknez d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_masknez(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_masknez(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MASKNEZ, d, j, k));
}
/* Emits the `nor d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_nor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_nor(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_NOR, d, j, k));
}
/* Emits the `and d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_and(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_and(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_AND, d, j, k));
}
/* Emits the `or d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_or(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_or(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_OR, d, j, k));
}
/* Emits the `xor d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_xor(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_XOR, d, j, k));
}
/* Emits the `orn d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_orn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_orn(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ORN, d, j, k));
}
/* Emits the `andn d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_andn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_andn(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ANDN, d, j, k));
}
/* Emits the `sll.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_sll_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_sll_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SLL_W, d, j, k));
}
/* Emits the `srl.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_srl_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_srl_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SRL_W, d, j, k));
}
/* Emits the `sra.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_sra_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_sra_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SRA_W, d, j, k));
}
/* Emits the `sll.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_sll_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_sll_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SLL_D, d, j, k));
}
/* Emits the `srl.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_srl_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_srl_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SRL_D, d, j, k));
}
/* Emits the `sra.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_sra_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_sra_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SRA_D, d, j, k));
}
/* Emits the `rotr.b d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_rotr_b(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_rotr_b(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ROTR_B, d, j, k));
}
/* Emits the `rotr.h d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_rotr_h(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_rotr_h(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ROTR_H, d, j, k));
}
/* Emits the `rotr.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_rotr_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_rotr_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ROTR_W, d, j, k));
}
/* Emits the `rotr.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_rotr_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_rotr_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ROTR_D, d, j, k));
}
/* Emits the `mul.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_mul_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_mul_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MUL_W, d, j, k));
}
/* Emits the `mulh.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_mulh_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_mulh_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MULH_W, d, j, k));
}
/* Emits the `mulh.wu d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_mulh_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_mulh_wu(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MULH_WU, d, j, k));
}
/* Emits the `mul.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_mul_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_mul_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MUL_D, d, j, k));
}
/* Emits the `mulh.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_mulh_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_mulh_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MULH_D, d, j, k));
}
/* Emits the `mulh.du d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_mulh_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_mulh_du(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MULH_DU, d, j, k));
}
/* Emits the `div.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_div_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_div_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_DIV_W, d, j, k));
}
/* Emits the `mod.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_mod_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_mod_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MOD_W, d, j, k));
}
/* Emits the `div.wu d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_div_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_div_wu(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_DIV_WU, d, j, k));
}
/* Emits the `mod.wu d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_mod_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_mod_wu(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MOD_WU, d, j, k));
}
/* Emits the `div.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_div_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_div_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_DIV_D, d, j, k));
}
/* Emits the `mod.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_mod_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_mod_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MOD_D, d, j, k));
}
/* Emits the `div.du d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_div_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_div_du(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_DIV_DU, d, j, k));
}
/* Emits the `mod.du d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_mod_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_mod_du(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MOD_DU, d, j, k));
}
/* Emits the `slli.w d, j, uk5` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_slli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5)
+static void __attribute__((unused)) tcg_out_opc_slli_w(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk5)
{
tcg_out32(s, encode_djuk5_insn(OPC_SLLI_W, d, j, uk5));
}
/* Emits the `slli.d d, j, uk6` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_slli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6)
+static void __attribute__((unused)) tcg_out_opc_slli_d(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk6)
{
tcg_out32(s, encode_djuk6_insn(OPC_SLLI_D, d, j, uk6));
}
/* Emits the `srli.w d, j, uk5` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_srli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5)
+static void __attribute__((unused)) tcg_out_opc_srli_w(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk5)
{
tcg_out32(s, encode_djuk5_insn(OPC_SRLI_W, d, j, uk5));
}
/* Emits the `srli.d d, j, uk6` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_srli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6)
+static void __attribute__((unused)) tcg_out_opc_srli_d(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk6)
{
tcg_out32(s, encode_djuk6_insn(OPC_SRLI_D, d, j, uk6));
}
/* Emits the `srai.w d, j, uk5` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_srai_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5)
+static void __attribute__((unused)) tcg_out_opc_srai_w(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk5)
{
tcg_out32(s, encode_djuk5_insn(OPC_SRAI_W, d, j, uk5));
}
/* Emits the `srai.d d, j, uk6` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_srai_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6)
+static void __attribute__((unused)) tcg_out_opc_srai_d(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk6)
{
tcg_out32(s, encode_djuk6_insn(OPC_SRAI_D, d, j, uk6));
}
/* Emits the `rotri.b d, j, uk3` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_rotri_b(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk3)
+static void __attribute__((unused)) tcg_out_opc_rotri_b(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk3)
{
tcg_out32(s, encode_djuk3_insn(OPC_ROTRI_B, d, j, uk3));
}
/* Emits the `rotri.h d, j, uk4` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_rotri_h(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk4)
+static void __attribute__((unused)) tcg_out_opc_rotri_h(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk4)
{
tcg_out32(s, encode_djuk4_insn(OPC_ROTRI_H, d, j, uk4));
}
/* Emits the `rotri.w d, j, uk5` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_rotri_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5)
+static void __attribute__((unused)) tcg_out_opc_rotri_w(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk5)
{
tcg_out32(s, encode_djuk5_insn(OPC_ROTRI_W, d, j, uk5));
}
/* Emits the `rotri.d d, j, uk6` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_rotri_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6)
+static void __attribute__((unused)) tcg_out_opc_rotri_d(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk6)
{
tcg_out32(s, encode_djuk6_insn(OPC_ROTRI_D, d, j, uk6));
}
/* Emits the `bstrins.w d, j, uk5, um5` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_bstrins_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5,
- uint32_t um5)
+static void __attribute__((unused)) tcg_out_opc_bstrins_w(TCGContext *s,
+ TCGReg d, TCGReg j,
+ uint32_t uk5,
+ uint32_t um5)
{
tcg_out32(s, encode_djuk5um5_insn(OPC_BSTRINS_W, d, j, uk5, um5));
}
/* Emits the `bstrpick.w d, j, uk5, um5` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_bstrpick_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5,
- uint32_t um5)
+static void __attribute__((unused)) tcg_out_opc_bstrpick_w(TCGContext *s,
+ TCGReg d, TCGReg j,
+ uint32_t uk5,
+ uint32_t um5)
{
tcg_out32(s, encode_djuk5um5_insn(OPC_BSTRPICK_W, d, j, uk5, um5));
}
/* Emits the `bstrins.d d, j, uk6, um6` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_bstrins_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6,
- uint32_t um6)
+static void __attribute__((unused)) tcg_out_opc_bstrins_d(TCGContext *s,
+ TCGReg d, TCGReg j,
+ uint32_t uk6,
+ uint32_t um6)
{
tcg_out32(s, encode_djuk6um6_insn(OPC_BSTRINS_D, d, j, uk6, um6));
}
/* Emits the `bstrpick.d d, j, uk6, um6` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_bstrpick_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6,
- uint32_t um6)
+static void __attribute__((unused)) tcg_out_opc_bstrpick_d(TCGContext *s,
+ TCGReg d, TCGReg j,
+ uint32_t uk6,
+ uint32_t um6)
{
tcg_out32(s, encode_djuk6um6_insn(OPC_BSTRPICK_D, d, j, uk6, um6));
}
/* Emits the `fmov.d fd, fj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_fmov_d(TCGContext *s, TCGReg fd, TCGReg fj)
+static void __attribute__((unused)) tcg_out_opc_fmov_d(TCGContext *s, TCGReg fd,
+ TCGReg fj)
{
tcg_out32(s, encode_fdfj_insn(OPC_FMOV_D, fd, fj));
}
/* Emits the `movgr2fr.d fd, j` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_movgr2fr_d(TCGContext *s, TCGReg fd, TCGReg j)
+static void __attribute__((unused)) tcg_out_opc_movgr2fr_d(TCGContext *s,
+ TCGReg fd, TCGReg j)
{
tcg_out32(s, encode_fdj_insn(OPC_MOVGR2FR_D, fd, j));
}
/* Emits the `movfr2gr.d d, fj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_movfr2gr_d(TCGContext *s, TCGReg d, TCGReg fj)
+static void __attribute__((unused)) tcg_out_opc_movfr2gr_d(TCGContext *s,
+ TCGReg d, TCGReg fj)
{
tcg_out32(s, encode_dfj_insn(OPC_MOVFR2GR_D, d, fj));
}
/* Emits the `slti d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_slti(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_slti(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_SLTI, d, j, sk12));
}
/* Emits the `sltui d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_sltui(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_sltui(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_SLTUI, d, j, sk12));
}
/* Emits the `addi.w d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_addi_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_addi_w(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ADDI_W, d, j, sk12));
}
/* Emits the `addi.d d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_addi_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_addi_d(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ADDI_D, d, j, sk12));
}
/* Emits the `cu52i.d d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_cu52i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_cu52i_d(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_CU52I_D, d, j, sk12));
}
/* Emits the `andi d, j, uk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_andi(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12)
+static void __attribute__((unused)) tcg_out_opc_andi(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk12)
{
tcg_out32(s, encode_djuk12_insn(OPC_ANDI, d, j, uk12));
}
/* Emits the `ori d, j, uk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12)
+static void __attribute__((unused)) tcg_out_opc_ori(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk12)
{
tcg_out32(s, encode_djuk12_insn(OPC_ORI, d, j, uk12));
}
/* Emits the `xori d, j, uk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12)
+static void __attribute__((unused)) tcg_out_opc_xori(TCGContext *s, TCGReg d,
+ TCGReg j, uint32_t uk12)
{
tcg_out32(s, encode_djuk12_insn(OPC_XORI, d, j, uk12));
}
@@ -1845,9 +1867,9 @@ tcg_out_opc_vbitsel_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk, TCGReg va)
}
/* Emits the `xvbitsel.v xd, xj, xk, xa` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvbitsel_v(TCGContext *s, TCGReg xd, TCGReg xj, TCGReg xk,
- TCGReg xa)
+static void __attribute__((unused)) tcg_out_opc_xvbitsel_v(TCGContext *s,
+ TCGReg xd, TCGReg xj,
+ TCGReg xk, TCGReg xa)
{
tcg_out32(s, encode_xdxjxkxa_insn(OPC_XVBITSEL_V, xd, xj, xk, xa));
}
@@ -1874,22 +1896,22 @@ tcg_out_opc_addu16i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
}
/* Emits the `lu12i.w d, sj20` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d, int32_t sj20)
+static void __attribute__((unused)) tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d,
+ int32_t sj20)
{
tcg_out32(s, encode_dsj20_insn(OPC_LU12I_W, d, sj20));
}
/* Emits the `cu32i.d d, sj20` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_cu32i_d(TCGContext *s, TCGReg d, int32_t sj20)
+static void __attribute__((unused)) tcg_out_opc_cu32i_d(TCGContext *s, TCGReg d,
+ int32_t sj20)
{
tcg_out32(s, encode_dsj20_insn(OPC_CU32I_D, d, sj20));
}
/* Emits the `pcaddu2i d, sj20` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_pcaddu2i(TCGContext *s, TCGReg d, int32_t sj20)
+static void __attribute__((unused)) tcg_out_opc_pcaddu2i(TCGContext *s,
+ TCGReg d, int32_t sj20)
{
tcg_out32(s, encode_dsj20_insn(OPC_PCADDU2I, d, sj20));
}
@@ -1916,134 +1938,134 @@ tcg_out_opc_pcaddu18i(TCGContext *s, TCGReg d, int32_t sj20)
}
/* Emits the `ld.b d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ld_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_ld_b(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_B, d, j, sk12));
}
/* Emits the `ld.h d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ld_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_ld_h(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_H, d, j, sk12));
}
/* Emits the `ld.w d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ld_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_ld_w(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_W, d, j, sk12));
}
/* Emits the `ld.d d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ld_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_ld_d(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_D, d, j, sk12));
}
/* Emits the `st.b d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_st_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_st_b(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ST_B, d, j, sk12));
}
/* Emits the `st.h d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_st_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_st_h(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ST_H, d, j, sk12));
}
/* Emits the `st.w d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_st_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_st_w(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ST_W, d, j, sk12));
}
/* Emits the `st.d d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_st_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_st_d(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ST_D, d, j, sk12));
}
/* Emits the `ld.bu d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ld_bu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_ld_bu(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_BU, d, j, sk12));
}
/* Emits the `ld.hu d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ld_hu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_ld_hu(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_HU, d, j, sk12));
}
/* Emits the `ld.wu d, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ld_wu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_ld_wu(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_WU, d, j, sk12));
}
/* Emits the `fld.s fd, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_fld_s(TCGContext *s, TCGReg fd, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_fld_s(TCGContext *s, TCGReg fd,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_fdjsk12_insn(OPC_FLD_S, fd, j, sk12));
}
/* Emits the `fst.s fd, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_fst_s(TCGContext *s, TCGReg fd, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_fst_s(TCGContext *s, TCGReg fd,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_fdjsk12_insn(OPC_FST_S, fd, j, sk12));
}
/* Emits the `fld.d fd, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_fld_d(TCGContext *s, TCGReg fd, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_fld_d(TCGContext *s, TCGReg fd,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_fdjsk12_insn(OPC_FLD_D, fd, j, sk12));
}
/* Emits the `fst.d fd, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_fst_d(TCGContext *s, TCGReg fd, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_fst_d(TCGContext *s, TCGReg fd,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_fdjsk12_insn(OPC_FST_D, fd, j, sk12));
}
/* Emits the `vld vd, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vld(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_vld(TCGContext *s, TCGReg vd,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_vdjsk12_insn(OPC_VLD, vd, j, sk12));
}
/* Emits the `vst vd, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vst(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_vst(TCGContext *s, TCGReg vd,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_vdjsk12_insn(OPC_VST, vd, j, sk12));
}
/* Emits the `xvld xd, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvld(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_xvld(TCGContext *s, TCGReg xd,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_xdjsk12_insn(OPC_XVLD, xd, j, sk12));
}
/* Emits the `xvst xd, j, sk12` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvst(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk12)
+static void __attribute__((unused)) tcg_out_opc_xvst(TCGContext *s, TCGReg xd,
+ TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_xdjsk12_insn(OPC_XVST, xd, j, sk12));
}
@@ -2077,33 +2099,37 @@ tcg_out_opc_vldrepl_b(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk12)
}
/* Emits the `vstelm.d vd, j, sk8, un1` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vstelm_d(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk8,
- uint32_t un1)
+static void __attribute__((unused)) tcg_out_opc_vstelm_d(TCGContext *s,
+ TCGReg vd, TCGReg j,
+ int32_t sk8,
+ uint32_t un1)
{
tcg_out32(s, encode_vdjsk8un1_insn(OPC_VSTELM_D, vd, j, sk8, un1));
}
/* Emits the `vstelm.w vd, j, sk8, un2` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vstelm_w(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk8,
- uint32_t un2)
+static void __attribute__((unused)) tcg_out_opc_vstelm_w(TCGContext *s,
+ TCGReg vd, TCGReg j,
+ int32_t sk8,
+ uint32_t un2)
{
tcg_out32(s, encode_vdjsk8un2_insn(OPC_VSTELM_W, vd, j, sk8, un2));
}
/* Emits the `vstelm.h vd, j, sk8, un3` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vstelm_h(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk8,
- uint32_t un3)
+static void __attribute__((unused)) tcg_out_opc_vstelm_h(TCGContext *s,
+ TCGReg vd, TCGReg j,
+ int32_t sk8,
+ uint32_t un3)
{
tcg_out32(s, encode_vdjsk8un3_insn(OPC_VSTELM_H, vd, j, sk8, un3));
}
/* Emits the `vstelm.b vd, j, sk8, un4` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vstelm_b(TCGContext *s, TCGReg vd, TCGReg j, int32_t sk8,
- uint32_t un4)
+static void __attribute__((unused)) tcg_out_opc_vstelm_b(TCGContext *s,
+ TCGReg vd, TCGReg j,
+ int32_t sk8,
+ uint32_t un4)
{
tcg_out32(s, encode_vdjsk8un4_insn(OPC_VSTELM_B, vd, j, sk8, un4));
}
@@ -2137,306 +2163,310 @@ tcg_out_opc_xvldrepl_b(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk12)
}
/* Emits the `xvstelm.d xd, j, sk8, un2` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvstelm_d(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk8,
- uint32_t un2)
+static void __attribute__((unused)) tcg_out_opc_xvstelm_d(TCGContext *s,
+ TCGReg xd, TCGReg j,
+ int32_t sk8,
+ uint32_t un2)
{
tcg_out32(s, encode_xdjsk8un2_insn(OPC_XVSTELM_D, xd, j, sk8, un2));
}
/* Emits the `xvstelm.w xd, j, sk8, un3` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvstelm_w(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk8,
- uint32_t un3)
+static void __attribute__((unused)) tcg_out_opc_xvstelm_w(TCGContext *s,
+ TCGReg xd, TCGReg j,
+ int32_t sk8,
+ uint32_t un3)
{
tcg_out32(s, encode_xdjsk8un3_insn(OPC_XVSTELM_W, xd, j, sk8, un3));
}
/* Emits the `xvstelm.h xd, j, sk8, un4` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvstelm_h(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk8,
- uint32_t un4)
+static void __attribute__((unused)) tcg_out_opc_xvstelm_h(TCGContext *s,
+ TCGReg xd, TCGReg j,
+ int32_t sk8,
+ uint32_t un4)
{
tcg_out32(s, encode_xdjsk8un4_insn(OPC_XVSTELM_H, xd, j, sk8, un4));
}
/* Emits the `xvstelm.b xd, j, sk8, un5` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvstelm_b(TCGContext *s, TCGReg xd, TCGReg j, int32_t sk8,
- uint32_t un5)
+static void __attribute__((unused)) tcg_out_opc_xvstelm_b(TCGContext *s,
+ TCGReg xd, TCGReg j,
+ int32_t sk8,
+ uint32_t un5)
{
tcg_out32(s, encode_xdjsk8un5_insn(OPC_XVSTELM_B, xd, j, sk8, un5));
}
/* Emits the `ldx.b d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ldx_b(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_ldx_b(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_B, d, j, k));
}
/* Emits the `ldx.h d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ldx_h(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_ldx_h(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_H, d, j, k));
}
/* Emits the `ldx.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ldx_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_ldx_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_W, d, j, k));
}
/* Emits the `ldx.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ldx_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_ldx_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_D, d, j, k));
}
/* Emits the `stx.b d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_stx_b(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_stx_b(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_STX_B, d, j, k));
}
/* Emits the `stx.h d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_stx_h(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_stx_h(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_STX_H, d, j, k));
}
/* Emits the `stx.w d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_stx_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_stx_w(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_STX_W, d, j, k));
}
/* Emits the `stx.d d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_stx_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_stx_d(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_STX_D, d, j, k));
}
/* Emits the `ldx.bu d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ldx_bu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_ldx_bu(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_BU, d, j, k));
}
/* Emits the `ldx.hu d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ldx_hu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_ldx_hu(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_HU, d, j, k));
}
/* Emits the `ldx.wu d, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ldx_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_ldx_wu(TCGContext *s, TCGReg d,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_WU, d, j, k));
}
/* Emits the `fldx.s fd, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_fldx_s(TCGContext *s, TCGReg fd, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_fldx_s(TCGContext *s, TCGReg fd,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_fdjk_insn(OPC_FLDX_S, fd, j, k));
}
/* Emits the `fldx.d fd, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_fldx_d(TCGContext *s, TCGReg fd, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_fldx_d(TCGContext *s, TCGReg fd,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_fdjk_insn(OPC_FLDX_D, fd, j, k));
}
/* Emits the `fstx.s fd, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_fstx_s(TCGContext *s, TCGReg fd, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_fstx_s(TCGContext *s, TCGReg fd,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_fdjk_insn(OPC_FSTX_S, fd, j, k));
}
/* Emits the `fstx.d fd, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_fstx_d(TCGContext *s, TCGReg fd, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_fstx_d(TCGContext *s, TCGReg fd,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_fdjk_insn(OPC_FSTX_D, fd, j, k));
}
/* Emits the `vldx vd, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vldx(TCGContext *s, TCGReg vd, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_vldx(TCGContext *s, TCGReg vd,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_vdjk_insn(OPC_VLDX, vd, j, k));
}
/* Emits the `vstx vd, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vstx(TCGContext *s, TCGReg vd, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_vstx(TCGContext *s, TCGReg vd,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_vdjk_insn(OPC_VSTX, vd, j, k));
}
/* Emits the `xvldx xd, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvldx(TCGContext *s, TCGReg xd, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_xvldx(TCGContext *s, TCGReg xd,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_xdjk_insn(OPC_XVLDX, xd, j, k));
}
/* Emits the `xvstx xd, j, k` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvstx(TCGContext *s, TCGReg xd, TCGReg j, TCGReg k)
+static void __attribute__((unused)) tcg_out_opc_xvstx(TCGContext *s, TCGReg xd,
+ TCGReg j, TCGReg k)
{
tcg_out32(s, encode_xdjk_insn(OPC_XVSTX, xd, j, k));
}
/* Emits the `dbar ud15` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_dbar(TCGContext *s, uint32_t ud15)
+static void __attribute__((unused)) tcg_out_opc_dbar(TCGContext *s,
+ uint32_t ud15)
{
tcg_out32(s, encode_ud15_insn(OPC_DBAR, ud15));
}
/* Emits the `jiscr0 sd5k16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_jiscr0(TCGContext *s, int32_t sd5k16)
+static void __attribute__((unused)) tcg_out_opc_jiscr0(TCGContext *s,
+ int32_t sd5k16)
{
tcg_out32(s, encode_sd5k16_insn(OPC_JISCR0, sd5k16));
}
/* Emits the `jiscr1 sd5k16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_jiscr1(TCGContext *s, int32_t sd5k16)
+static void __attribute__((unused)) tcg_out_opc_jiscr1(TCGContext *s,
+ int32_t sd5k16)
{
tcg_out32(s, encode_sd5k16_insn(OPC_JISCR1, sd5k16));
}
/* Emits the `jirl d, j, sk16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_jirl(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
+static void __attribute__((unused)) tcg_out_opc_jirl(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_JIRL, d, j, sk16));
}
/* Emits the `b sd10k16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_b(TCGContext *s, int32_t sd10k16)
+static void __attribute__((unused)) tcg_out_opc_b(TCGContext *s,
+ int32_t sd10k16)
{
tcg_out32(s, encode_sd10k16_insn(OPC_B, sd10k16));
}
/* Emits the `bl sd10k16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_bl(TCGContext *s, int32_t sd10k16)
+static void __attribute__((unused)) tcg_out_opc_bl(TCGContext *s,
+ int32_t sd10k16)
{
tcg_out32(s, encode_sd10k16_insn(OPC_BL, sd10k16));
}
/* Emits the `beq d, j, sk16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_beq(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
+static void __attribute__((unused)) tcg_out_opc_beq(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BEQ, d, j, sk16));
}
/* Emits the `bne d, j, sk16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_bne(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
+static void __attribute__((unused)) tcg_out_opc_bne(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BNE, d, j, sk16));
}
/* Emits the `bgt d, j, sk16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_bgt(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
+static void __attribute__((unused)) tcg_out_opc_bgt(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BGT, d, j, sk16));
}
/* Emits the `ble d, j, sk16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_ble(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
+static void __attribute__((unused)) tcg_out_opc_ble(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BLE, d, j, sk16));
}
/* Emits the `bgtu d, j, sk16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_bgtu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
+static void __attribute__((unused)) tcg_out_opc_bgtu(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BGTU, d, j, sk16));
}
/* Emits the `bleu d, j, sk16` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_bleu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
+static void __attribute__((unused)) tcg_out_opc_bleu(TCGContext *s, TCGReg d,
+ TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BLEU, d, j, sk16));
}
/* Emits the `vseq.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vseq_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vseq_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSEQ_B, vd, vj, vk));
}
/* Emits the `vseq.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vseq_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vseq_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSEQ_H, vd, vj, vk));
}
/* Emits the `vseq.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vseq_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vseq_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSEQ_W, vd, vj, vk));
}
/* Emits the `vseq.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vseq_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vseq_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSEQ_D, vd, vj, vk));
}
/* Emits the `vsle.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsle_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsle_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLE_B, vd, vj, vk));
}
/* Emits the `vsle.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsle_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsle_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLE_H, vd, vj, vk));
}
/* Emits the `vsle.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsle_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsle_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLE_W, vd, vj, vk));
}
/* Emits the `vsle.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsle_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsle_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLE_D, vd, vj, vk));
}
@@ -2470,29 +2500,29 @@ tcg_out_opc_vsle_du(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
}
/* Emits the `vslt.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vslt_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vslt_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLT_B, vd, vj, vk));
}
/* Emits the `vslt.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vslt_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vslt_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLT_H, vd, vj, vk));
}
/* Emits the `vslt.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vslt_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vslt_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLT_W, vd, vj, vk));
}
/* Emits the `vslt.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vslt_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vslt_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLT_D, vd, vj, vk));
}
@@ -2526,57 +2556,57 @@ tcg_out_opc_vslt_du(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
}
/* Emits the `vadd.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vadd_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vadd_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VADD_B, vd, vj, vk));
}
/* Emits the `vadd.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vadd_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vadd_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VADD_H, vd, vj, vk));
}
/* Emits the `vadd.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vadd_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vadd_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VADD_W, vd, vj, vk));
}
/* Emits the `vadd.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vadd_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vadd_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VADD_D, vd, vj, vk));
}
/* Emits the `vsub.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsub_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsub_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSUB_B, vd, vj, vk));
}
/* Emits the `vsub.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsub_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsub_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSUB_H, vd, vj, vk));
}
/* Emits the `vsub.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsub_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsub_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSUB_W, vd, vj, vk));
}
/* Emits the `vsub.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsub_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsub_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSUB_D, vd, vj, vk));
}
@@ -2694,57 +2724,57 @@ tcg_out_opc_vssub_du(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
}
/* Emits the `vmax.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmax_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmax_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMAX_B, vd, vj, vk));
}
/* Emits the `vmax.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmax_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmax_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMAX_H, vd, vj, vk));
}
/* Emits the `vmax.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmax_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmax_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMAX_W, vd, vj, vk));
}
/* Emits the `vmax.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmax_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmax_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMAX_D, vd, vj, vk));
}
/* Emits the `vmin.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmin_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmin_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMIN_B, vd, vj, vk));
}
/* Emits the `vmin.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmin_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmin_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMIN_H, vd, vj, vk));
}
/* Emits the `vmin.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmin_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmin_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMIN_W, vd, vj, vk));
}
/* Emits the `vmin.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmin_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmin_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMIN_D, vd, vj, vk));
}
@@ -2806,113 +2836,113 @@ tcg_out_opc_vmin_du(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
}
/* Emits the `vmul.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmul_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmul_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMUL_B, vd, vj, vk));
}
/* Emits the `vmul.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmul_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmul_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMUL_H, vd, vj, vk));
}
/* Emits the `vmul.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmul_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmul_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMUL_W, vd, vj, vk));
}
/* Emits the `vmul.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vmul_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vmul_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VMUL_D, vd, vj, vk));
}
/* Emits the `vsll.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsll_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsll_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLL_B, vd, vj, vk));
}
/* Emits the `vsll.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsll_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsll_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLL_H, vd, vj, vk));
}
/* Emits the `vsll.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsll_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsll_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLL_W, vd, vj, vk));
}
/* Emits the `vsll.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsll_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsll_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSLL_D, vd, vj, vk));
}
/* Emits the `vsrl.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsrl_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsrl_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSRL_B, vd, vj, vk));
}
/* Emits the `vsrl.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsrl_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsrl_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSRL_H, vd, vj, vk));
}
/* Emits the `vsrl.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsrl_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsrl_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSRL_W, vd, vj, vk));
}
/* Emits the `vsrl.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsrl_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsrl_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSRL_D, vd, vj, vk));
}
/* Emits the `vsra.b vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsra_b(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsra_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSRA_B, vd, vj, vk));
}
/* Emits the `vsra.h vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsra_h(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsra_h(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSRA_H, vd, vj, vk));
}
/* Emits the `vsra.w vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsra_w(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsra_w(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSRA_W, vd, vj, vk));
}
/* Emits the `vsra.d vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vsra_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vsra_d(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VSRA_D, vd, vj, vk));
}
@@ -2974,29 +3004,29 @@ tcg_out_opc_vreplve_d(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg k)
}
/* Emits the `vand.v vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vand_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vand_v(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VAND_V, vd, vj, vk));
}
/* Emits the `vor.v vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vor_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vor_v(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VOR_V, vd, vj, vk));
}
/* Emits the `vxor.v vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vxor_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vxor_v(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VXOR_V, vd, vj, vk));
}
/* Emits the `vnor.v vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vnor_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vnor_v(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VNOR_V, vd, vj, vk));
}
@@ -3009,8 +3039,8 @@ tcg_out_opc_vandn_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
}
/* Emits the `vorn.v vd, vj, vk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vorn_v(TCGContext *s, TCGReg vd, TCGReg vj, TCGReg vk)
+static void __attribute__((unused)) tcg_out_opc_vorn_v(TCGContext *s, TCGReg vd,
+ TCGReg vj, TCGReg vk)
{
tcg_out32(s, encode_vdvjvk_insn(OPC_VORN_V, vd, vj, vk));
}
@@ -3324,29 +3354,29 @@ tcg_out_opc_vmini_du(TCGContext *s, TCGReg vd, TCGReg vj, uint32_t uk5)
}
/* Emits the `vneg.b vd, vj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vneg_b(TCGContext *s, TCGReg vd, TCGReg vj)
+static void __attribute__((unused)) tcg_out_opc_vneg_b(TCGContext *s, TCGReg vd,
+ TCGReg vj)
{
tcg_out32(s, encode_vdvj_insn(OPC_VNEG_B, vd, vj));
}
/* Emits the `vneg.h vd, vj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vneg_h(TCGContext *s, TCGReg vd, TCGReg vj)
+static void __attribute__((unused)) tcg_out_opc_vneg_h(TCGContext *s, TCGReg vd,
+ TCGReg vj)
{
tcg_out32(s, encode_vdvj_insn(OPC_VNEG_H, vd, vj));
}
/* Emits the `vneg.w vd, vj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vneg_w(TCGContext *s, TCGReg vd, TCGReg vj)
+static void __attribute__((unused)) tcg_out_opc_vneg_w(TCGContext *s, TCGReg vd,
+ TCGReg vj)
{
tcg_out32(s, encode_vdvj_insn(OPC_VNEG_W, vd, vj));
}
/* Emits the `vneg.d vd, vj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vneg_d(TCGContext *s, TCGReg vd, TCGReg vj)
+static void __attribute__((unused)) tcg_out_opc_vneg_d(TCGContext *s, TCGReg vd,
+ TCGReg vj)
{
tcg_out32(s, encode_vdvj_insn(OPC_VNEG_D, vd, vj));
}
@@ -3702,8 +3732,8 @@ tcg_out_opc_vandi_b(TCGContext *s, TCGReg vd, TCGReg vj, uint32_t uk8)
}
/* Emits the `vori.b vd, vj, uk8` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vori_b(TCGContext *s, TCGReg vd, TCGReg vj, uint32_t uk8)
+static void __attribute__((unused)) tcg_out_opc_vori_b(TCGContext *s, TCGReg vd,
+ TCGReg vj, uint32_t uk8)
{
tcg_out32(s, encode_vdvjuk8_insn(OPC_VORI_B, vd, vj, uk8));
}
@@ -3723,8 +3753,8 @@ tcg_out_opc_vnori_b(TCGContext *s, TCGReg vd, TCGReg vj, uint32_t uk8)
}
/* Emits the `vldi vd, sj13` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_vldi(TCGContext *s, TCGReg vd, int32_t sj13)
+static void __attribute__((unused)) tcg_out_opc_vldi(TCGContext *s, TCGReg vd,
+ int32_t sj13)
{
tcg_out32(s, encode_vdsj13_insn(OPC_VLDI, vd, sj13));
}
@@ -4325,8 +4355,8 @@ tcg_out_opc_xvand_v(TCGContext *s, TCGReg xd, TCGReg xj, TCGReg xk)
}
/* Emits the `xvor.v xd, xj, xk` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvor_v(TCGContext *s, TCGReg xd, TCGReg xj, TCGReg xk)
+static void __attribute__((unused)) tcg_out_opc_xvor_v(TCGContext *s, TCGReg xd,
+ TCGReg xj, TCGReg xk)
{
tcg_out32(s, encode_xdxjxk_insn(OPC_XVOR_V, xd, xj, xk));
}
@@ -4668,29 +4698,29 @@ tcg_out_opc_xvmini_du(TCGContext *s, TCGReg xd, TCGReg xj, uint32_t uk5)
}
/* Emits the `xvneg.b xd, xj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvneg_b(TCGContext *s, TCGReg xd, TCGReg xj)
+static void __attribute__((unused)) tcg_out_opc_xvneg_b(TCGContext *s,
+ TCGReg xd, TCGReg xj)
{
tcg_out32(s, encode_xdxj_insn(OPC_XVNEG_B, xd, xj));
}
/* Emits the `xvneg.h xd, xj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvneg_h(TCGContext *s, TCGReg xd, TCGReg xj)
+static void __attribute__((unused)) tcg_out_opc_xvneg_h(TCGContext *s,
+ TCGReg xd, TCGReg xj)
{
tcg_out32(s, encode_xdxj_insn(OPC_XVNEG_H, xd, xj));
}
/* Emits the `xvneg.w xd, xj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvneg_w(TCGContext *s, TCGReg xd, TCGReg xj)
+static void __attribute__((unused)) tcg_out_opc_xvneg_w(TCGContext *s,
+ TCGReg xd, TCGReg xj)
{
tcg_out32(s, encode_xdxj_insn(OPC_XVNEG_W, xd, xj));
}
/* Emits the `xvneg.d xd, xj` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvneg_d(TCGContext *s, TCGReg xd, TCGReg xj)
+static void __attribute__((unused)) tcg_out_opc_xvneg_d(TCGContext *s,
+ TCGReg xd, TCGReg xj)
{
tcg_out32(s, encode_xdxj_insn(OPC_XVNEG_D, xd, xj));
}
@@ -5060,8 +5090,8 @@ tcg_out_opc_xvnori_b(TCGContext *s, TCGReg xd, TCGReg xj, uint32_t uk8)
}
/* Emits the `xvldi xd, sj13` instruction. */
-static void __attribute__((unused))
-tcg_out_opc_xvldi(TCGContext *s, TCGReg xd, int32_t sj13)
+static void __attribute__((unused)) tcg_out_opc_xvldi(TCGContext *s, TCGReg xd,
+ int32_t sj13)
{
tcg_out32(s, encode_xdsj13_insn(OPC_XVLDI, xd, sj13));
}
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 11/11] tcg/loongarch64: Implement revbit{32,64}
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
` (9 preceding siblings ...)
2026-07-31 0:05 ` [PATCH 10/11] tcg/loongarch64: Import REVBIT insns Richard Henderson
@ 2026-07-31 0:05 ` Richard Henderson
2026-08-03 14:59 ` Philippe Mathieu-Daudé
2026-08-10 12:15 ` Anton Johansson via qemu development
2026-08-10 10:46 ` Anton Johansson via
11 siblings, 2 replies; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 0:05 UTC (permalink / raw)
To: qemu-devel; +Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index a5cd3c3b1e..9072a447ed 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1866,12 +1866,30 @@ static const TCGOutOpUnary outop_bswap64 = {
.out_rr = tgen_bswap64,
};
+static void tgen_revbit32(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, unsigned flags)
+{
+ tcg_out_opc_revbit_w(s, a0, a1);
+
+ /* All 32-bit values are computed sign-extended in the register. */
+ if (type == TCG_TYPE_I64 && (flags & TCG_BSWAP_OZ)) {
+ tcg_out_ext32u(s, a0, a0);
+ }
+}
+
static const TCGOutOpBswap outop_revbit32 = {
- .base.static_constraint = C_NotImplemented,
+ .base.static_constraint = C_O1_I1(r, r),
+ .out_rr = tgen_revbit32,
};
+static void tgen_revbit64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
+{
+ tcg_out_opc_revbit_d(s, a0, a1);
+}
+
static const TCGOutOpUnary outop_revbit64 = {
- .base.static_constraint = C_NotImplemented,
+ .base.static_constraint = C_O1_I1(r, r),
+ .out_rr = tgen_revbit64,
};
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
--
2.43.0
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64}
2026-07-31 0:04 ` [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64} Richard Henderson
@ 2026-07-31 6:08 ` Philippe Mathieu-Daudé
2026-07-31 6:41 ` Philippe Mathieu-Daudé
2026-07-31 6:49 ` Philippe Mathieu-Daudé
2026-08-10 11:15 ` Anton Johansson via qemu development
2 siblings, 1 reply; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-31 6:08 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
On 31/7/26 02:04, Richard Henderson wrote:
> Add generic expanders for reversing bits within a word.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-op-common.h | 3 ++
> include/tcg/tcg-op.h | 5 ++++
> tcg/tcg-op.c | 59 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 67 insertions(+)
Missing listing in docs/devel/tcg-ops.rst, otherwise:
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 03/11] target/arm: Use generic tcg_gen_revbit*
2026-07-31 0:04 ` [PATCH 03/11] target/arm: Use generic tcg_gen_revbit* Richard Henderson
@ 2026-07-31 6:08 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-31 6:08 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
On 31/7/26 02:04, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/helper-a64-defs.h | 1 -
> target/arm/tcg/helper-defs.h | 1 -
> target/arm/tcg/helper-a64.c | 5 -----
> target/arm/tcg/op_helper.c | 5 -----
> target/arm/tcg/translate-a64.c | 4 ++--
> target/arm/tcg/translate.c | 2 +-
> 6 files changed, 3 insertions(+), 15 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 04/11] target/loongarch: Use generic tcg_gen_revbit*
2026-07-31 0:04 ` [PATCH 04/11] target/loongarch: " Richard Henderson
@ 2026-07-31 6:10 ` Philippe Mathieu-Daudé
2026-08-05 9:16 ` Song Gao
1 sibling, 0 replies; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-31 6:10 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
On 31/7/26 02:04, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/loongarch/tcg/helper.h | 2 --
> target/loongarch/tcg/op_helper.c | 10 ----------
> target/loongarch/tcg/insn_trans/trans_bit.c.inc | 9 +++++++--
> 3 files changed, 7 insertions(+), 14 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64}
2026-07-31 6:08 ` Philippe Mathieu-Daudé
@ 2026-07-31 6:41 ` Philippe Mathieu-Daudé
2026-07-31 8:55 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-31 6:41 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
On 31/7/26 08:08, Philippe Mathieu-Daudé wrote:
> On 31/7/26 02:04, Richard Henderson wrote:
>> Add generic expanders for reversing bits within a word.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> include/tcg/tcg-op-common.h | 3 ++
>> include/tcg/tcg-op.h | 5 ++++
>> tcg/tcg-op.c | 59 +++++++++++++++++++++++++++++++++++++
>> 3 files changed, 67 insertions(+)
>
> Missing listing in docs/devel/tcg-ops.rst,
I now see that in "tcg: Add revbit{32,64} opcodes" in patch #7.
Since they are for frontends I'd expect them documented in this
patch, not #7 (backends).
> otherwise:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64}
2026-07-31 0:04 ` [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64} Richard Henderson
2026-07-31 6:08 ` Philippe Mathieu-Daudé
@ 2026-07-31 6:49 ` Philippe Mathieu-Daudé
2026-07-31 14:29 ` Richard Henderson
2026-08-10 11:15 ` Anton Johansson via qemu development
2 siblings, 1 reply; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-31 6:49 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd,
Pierrick Bouvier
Hi Richard,
On 31/7/26 02:04, Richard Henderson wrote:
> Add generic expanders for reversing bits within a word.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-op-common.h | 3 ++
> include/tcg/tcg-op.h | 5 ++++
> tcg/tcg-op.c | 59 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 67 insertions(+)
>
> diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
> index 1fe342db0d..91f59dc11e 100644
> --- a/include/tcg/tcg-op-common.h
> +++ b/include/tcg/tcg-op-common.h
> @@ -275,6 +276,8 @@ void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
> void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
> void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
> void tcg_gen_abs_i64(TCGv_i64, TCGv_i64);
> +void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
> +void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg);
Could the bswap flag be defined once per target?
- output sign-extended (TCG_BSWAP_OS):
alpha, hppa, loongarch, m68k, mips, riscv, rx, sh4, tricore
- output zero-extended (TCG_BSWAP_OZ):
arm, avr, hexagon, microblaze, openrisc, ppc, sparc, x86, xtensa
- input/output zero-extended (TCG_BSWAP_IZ | TCG_BSWAP_OZ):
s390x
Having to manually encode it on each frontend doesn't sound optimal.
Note, we have some target-specific TCG information in TCGCPUOps
(useful at runtime for heterogeneous emulation).
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 07/11] tcg: Add revbit{32,64} opcodes
2026-07-31 0:04 ` [PATCH 07/11] tcg: Add revbit{32,64} opcodes Richard Henderson
@ 2026-07-31 7:02 ` Philippe Mathieu-Daudé
2026-08-10 12:15 ` Anton Johansson via
1 sibling, 0 replies; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-31 7:02 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
On 31/7/26 02:04, Richard Henderson wrote:
> Add the plumbing, but not yet implemented for any host.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-opc.h | 2 ++
> tcg/tcg-op.c | 43 +++++++++++++++++++++++---------
> tcg/tcg.c | 6 +++++
> docs/devel/tcg-ops.rst | 11 ++++++++
> tcg/aarch64/tcg-target.c.inc | 8 ++++++
> tcg/loongarch64/tcg-target.c.inc | 8 ++++++
> tcg/ppc64/tcg-target.c.inc | 8 ++++++
> tcg/riscv64/tcg-target.c.inc | 8 ++++++
> tcg/s390x/tcg-target.c.inc | 8 ++++++
> tcg/sparc64/tcg-target.c.inc | 8 ++++++
> tcg/tci/tcg-target.c.inc | 8 ++++++
> tcg/x86_64/tcg-target.c.inc | 8 ++++++
> 12 files changed, 114 insertions(+), 12 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 09/11] tcg/aarch64: Implement revbit{32,64}
2026-07-31 0:05 ` [PATCH 09/11] tcg/aarch64: Implement revbit{32,64} Richard Henderson
@ 2026-07-31 7:12 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-31 7:12 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
On 31/7/26 02:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target.c.inc | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> +static void tgen_revbit32(TCGContext *s, TCGType type,
> + TCGReg a0, TCGReg a1, unsigned flags)
> +{
> + tcg_out_insn(s, rr_sf, RBIT, TCG_TYPE_I32, a0, a1);
> + if (flags & TCG_BSWAP_OS) {
> + tcg_out_ext32s(s, a0, a0);
Back to my comment in patch #1 about having bswap flags defined once
per target, that would allow that kind of change to be done once in
common code, not per-target once. In the lines of:
if (backend_default_flag & TCG_BSWAP_OZ
&& frontend_requested_flag & TCG_BSWAP_OS) {
tcg_out_ext32s(s, a0, a0);
} ...
> + }
> +}
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64}
2026-07-31 6:41 ` Philippe Mathieu-Daudé
@ 2026-07-31 8:55 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-31 8:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
On 31/7/26 08:41, Philippe Mathieu-Daudé wrote:
> On 31/7/26 08:08, Philippe Mathieu-Daudé wrote:
>> On 31/7/26 02:04, Richard Henderson wrote:
>>> Add generic expanders for reversing bits within a word.
>>>
>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>> include/tcg/tcg-op-common.h | 3 ++
>>> include/tcg/tcg-op.h | 5 ++++
>>> tcg/tcg-op.c | 59 +++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 67 insertions(+)
>>
>> Missing listing in docs/devel/tcg-ops.rst,
>
> I now see that in "tcg: Add revbit{32,64} opcodes" in patch #7.
> Since they are for frontends I'd expect them documented in this
> patch, not #7 (backends).
I guess I keep misunderstanding this document; I refer to it with
frontends but it might be for backends. I also guess you already
explained that to me. Nevermind.
>
>> otherwise:
>> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>>
>>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64}
2026-07-31 6:49 ` Philippe Mathieu-Daudé
@ 2026-07-31 14:29 ` Richard Henderson
0 siblings, 0 replies; 41+ messages in thread
From: Richard Henderson @ 2026-07-31 14:29 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd,
Pierrick Bouvier
On 7/30/26 23:49, Philippe Mathieu-Daudé wrote:
>> +void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
>> +void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg);
>
> Could the bswap flag be defined once per target?
It is not intended for bswap (or revbit) to have a set interpretation for any target, but
to be contextually correct for the usage.
For instance, TCG_BSWAP_IZ would generally be only known at the call-site, because of how
one has prepared the input. It's usage within s390x follows forced zero-extension:
C(0xe31f, LRVH, RXY_a, Z, 0, m2_16u, new, r1_16, rev16, 0)
...
C(0xe33f, STRVH, RXY_a, Z, la2, r1_16u, new, m1_16, rev16, 0)
Annoyingly, s390x should have these memory insns updated to perform the "reversed"
load/store via MO_BSWAP.
> - output sign-extended (TCG_BSWAP_OS):
>
> alpha, hppa, loongarch, m68k, mips, riscv, rx, sh4, tricore
>
> - output zero-extended (TCG_BSWAP_OZ):
>
> arm, avr, hexagon, microblaze, openrisc, ppc, sparc, x86, xtensa
But note that arm uses both OS (aarch32 REVSH) and OZ (aarch64 REV32).
r~
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 08/11] tcg/optimize: Handle revbit{32,64}
2026-07-31 0:05 ` [PATCH 08/11] tcg/optimize: Handle revbit{32,64} Richard Henderson
@ 2026-08-03 14:58 ` Philippe Mathieu-Daudé
2026-08-10 10:44 ` Anton Johansson via qemu development
1 sibling, 0 replies; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-03 14:58 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
On 31/7/26 02:05, Richard Henderson wrote:
> These are nearly identical to bswap, so reuse fold_bswap.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 48 +++++++++++++++++++++++++-----------------------
> 1 file changed, 25 insertions(+), 23 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 11/11] tcg/loongarch64: Implement revbit{32,64}
2026-07-31 0:05 ` [PATCH 11/11] tcg/loongarch64: Implement revbit{32,64} Richard Henderson
@ 2026-08-03 14:59 ` Philippe Mathieu-Daudé
2026-08-10 12:15 ` Anton Johansson via qemu development
1 sibling, 0 replies; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-03 14:59 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
On 31/7/26 02:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/loongarch64/tcg-target.c.inc | 22 ++++++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 10/11] tcg/loongarch64: Import REVBIT insns
2026-07-31 0:05 ` [PATCH 10/11] tcg/loongarch64: Import REVBIT insns Richard Henderson
@ 2026-08-03 15:06 ` Philippe Mathieu-Daudé
2026-08-03 17:26 ` Richard Henderson
0 siblings, 1 reply; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-03 15:06 UTC (permalink / raw)
To: Richard Henderson, git, qemu-devel
Cc: anjo, qemu-arm, 17746591750, maobibo, lixianglai, philmd,
Jiaxun Yang
Hi Richard,
On 31/7/26 02:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/loongarch64/tcg-insn-defs.c.inc | 944 ++++++++++++++--------------
> 1 file changed, 487 insertions(+), 457 deletions(-)
>
> diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-insn-defs.c.inc
> index 6bb8656fd8..c308b770ef 100644
> --- a/tcg/loongarch64/tcg-insn-defs.c.inc
> +++ b/tcg/loongarch64/tcg-insn-defs.c.inc
> @@ -4,7 +4,7 @@
> *
> * This file is auto-generated by genqemutcgdefs from
> * https://github.com/loongson-community/loongarch-opcodes,
> - * from commit 7f353fb69bd99ce6edfad7ad63948c4bb526f0bf.
> + * from commit 40ea52087699392ad911387b666541891d33da31.
I couldn't find it then noticed your
https://github.com/loongson-community/loongarch-opcodes/pull/10,
so pending it to be merged?
> * DO NOT EDIT.
> */
>
> @@ -18,6 +18,8 @@ typedef enum {
> OPC_REVB_2H = 0x00003000,
> OPC_REVB_2W = 0x00003800,
> OPC_REVB_D = 0x00003c00,
> + OPC_REVBIT_W = 0x00005000,
> + OPC_REVBIT_D = 0x00005400,
> OPC_SEXT_H = 0x00005800,
> OPC_SEXT_B = 0x00005c00,
> OPC_ADD_W = 0x00100000,
> @@ -545,14 +547,14 @@ typedef enum {
> OPC_XVLDI = 0x77e00000,
> } LoongArchInsn;
>
> -static int32_t __attribute__((unused))
> -encode_d_slot(LoongArchInsn opc, uint32_t d)
> +static int32_t __attribute__((unused)) encode_d_slot(LoongArchInsn opc,
> + uint32_t d)
What triggered this code churn? Could we commit before generating for
REVBIT opcodes?
> {
> return opc | d;
> }
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 01/11] tcg: Fix opcode dump for bswap
2026-07-31 0:04 ` [PATCH 01/11] tcg: Fix opcode dump for bswap Richard Henderson
@ 2026-08-03 15:08 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-03 15:08 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, 17746591750, maobibo, lixianglai, philmd
On 31/7/26 02:04, Richard Henderson wrote:
> We use an array of char for bswap_flag_name, so some
> entries in the array are non-null but empty. Check that.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tcg.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Fixes: 587195bd590 ("tcg: Add flags argument to bswap opcodes")
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 10/11] tcg/loongarch64: Import REVBIT insns
2026-08-03 15:06 ` Philippe Mathieu-Daudé
@ 2026-08-03 17:26 ` Richard Henderson
2026-08-04 2:51 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 41+ messages in thread
From: Richard Henderson @ 2026-08-03 17:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, git, qemu-devel
Cc: anjo, qemu-arm, 17746591750, maobibo, lixianglai, philmd,
Jiaxun Yang
On 8/3/26 08:06, Philippe Mathieu-Daudé wrote:
>> * This file is auto-generated by genqemutcgdefs from
>> * https://github.com/loongson-community/loongarch-opcodes,
>> - * from commit 7f353fb69bd99ce6edfad7ad63948c4bb526f0bf.
>> + * from commit 40ea52087699392ad911387b666541891d33da31.
>
> I couldn't find it then noticed your
> https://github.com/loongson-community/loongarch-opcodes/pull/10,
> so pending it to be merged?
Yes.
>> -static int32_t __attribute__((unused))
>> -encode_d_slot(LoongArchInsn opc, uint32_t d)
>> +static int32_t __attribute__((unused)) encode_d_slot(LoongArchInsn opc,
>> + uint32_t d)
>
> What triggered this code churn? Could we commit before generating for
> REVBIT opcodes?
It looks like the program passes off to clang-format. Perhaps a version change in the
year since last regenerated?
r~
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 10/11] tcg/loongarch64: Import REVBIT insns
2026-08-03 17:26 ` Richard Henderson
@ 2026-08-04 2:51 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 41+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-04 2:51 UTC (permalink / raw)
To: Richard Henderson, git, qemu-devel
Cc: anjo, qemu-arm, 17746591750, maobibo, lixianglai, philmd,
Jiaxun Yang
On 3/8/26 19:26, Richard Henderson wrote:
> On 8/3/26 08:06, Philippe Mathieu-Daudé wrote:
>>> * This file is auto-generated by genqemutcgdefs from
>>> * https://github.com/loongson-community/loongarch-opcodes,
>>> - * from commit 7f353fb69bd99ce6edfad7ad63948c4bb526f0bf.
>>> + * from commit 40ea52087699392ad911387b666541891d33da31.
>>
>> I couldn't find it then noticed your
>> https://github.com/loongson-community/loongarch-opcodes/pull/10,
>> so pending it to be merged?
>
> Yes.
>
>>> -static int32_t __attribute__((unused))
>>> -encode_d_slot(LoongArchInsn opc, uint32_t d)
>>> +static int32_t __attribute__((unused)) encode_d_slot(LoongArchInsn opc,
>>> + uint32_t d)
>>
>> What triggered this code churn? Could we commit before generating for
>> REVBIT opcodes?
>
> It looks like the program passes off to clang-format. Perhaps a version
> change in the year since last regenerated?
Then maybe call genqemutcgdefs to regenerate clang-formatted in a
preliminary patch? Would also help reverts.
>
>
> r~
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 04/11] target/loongarch: Use generic tcg_gen_revbit*
2026-07-31 0:04 ` [PATCH 04/11] target/loongarch: " Richard Henderson
2026-07-31 6:10 ` Philippe Mathieu-Daudé
@ 2026-08-05 9:16 ` Song Gao
1 sibling, 0 replies; 41+ messages in thread
From: Song Gao @ 2026-08-05 9:16 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, maobibo, lixianglai, philmd
在 2026/7/31 上午8:04, Richard Henderson 写道:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/loongarch/tcg/helper.h | 2 --
> target/loongarch/tcg/op_helper.c | 10 ----------
> target/loongarch/tcg/insn_trans/trans_bit.c.inc | 9 +++++++--
> 3 files changed, 7 insertions(+), 14 deletions(-)
Reviewed-by: Song Gao <17746591750@163.com>
Thanks.
Song Gao
> diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h
> index 8a6c62f116..4b0fc81db6 100644
> --- a/target/loongarch/tcg/helper.h
> +++ b/target/loongarch/tcg/helper.h
> @@ -5,8 +5,6 @@
>
> DEF_HELPER_2(raise_exception, noreturn, env, i32)
>
> -DEF_HELPER_FLAGS_1(bitrev_w, TCG_CALL_NO_RWG_SE, tl, tl)
> -DEF_HELPER_FLAGS_1(bitrev_d, TCG_CALL_NO_RWG_SE, tl, tl)
> DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
>
> DEF_HELPER_FLAGS_3(asrtle_d, TCG_CALL_NO_WG, void, env, tl, tl)
> diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c
> index e63ac66daa..37afa8e92d 100644
> --- a/target/loongarch/tcg/op_helper.c
> +++ b/target/loongarch/tcg/op_helper.c
> @@ -22,16 +22,6 @@ void helper_raise_exception(CPULoongArchState *env, uint32_t exception)
> do_raise_exception(env, exception, GETPC());
> }
>
> -target_ulong helper_bitrev_w(target_ulong rj)
> -{
> - return (int32_t)revbit32(rj);
> -}
> -
> -target_ulong helper_bitrev_d(target_ulong rj)
> -{
> - return revbit64(rj);
> -}
> -
> target_ulong helper_bitswap(target_ulong v)
> {
> v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
> diff --git a/target/loongarch/tcg/insn_trans/trans_bit.c.inc b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
> index ee5fa003ce..3d24e320ce 100644
> --- a/target/loongarch/tcg/insn_trans/trans_bit.c.inc
> +++ b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
> @@ -178,6 +178,11 @@ static void gen_masknez(TCGv dest, TCGv src1, TCGv src2)
> tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, zero, zero, src1);
> }
>
> +static void gen_bitrev_w(TCGv dest, TCGv src)
> +{
> + tcg_gen_revbit32_tl(dest, src, TCG_BSWAP_OS);
> +}
> +
> TRANS(ext_w_h, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext16s_tl)
> TRANS(ext_w_b, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext8s_tl)
> TRANS(clo_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w)
> @@ -196,8 +201,8 @@ TRANS(revh_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
> TRANS(revh_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
> TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)
> TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)
> -TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w)
> -TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d)
> +TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_bitrev_w)
> +TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_revbit64_i64)
> TRANS(maskeqz, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
> TRANS(masknez, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
> TRANS(bytepick_w, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 05/11] target/loongarch: Expand bitswap inline
2026-07-31 0:04 ` [PATCH 05/11] target/loongarch: Expand bitswap inline Richard Henderson
@ 2026-08-05 9:17 ` Song Gao
0 siblings, 0 replies; 41+ messages in thread
From: Song Gao @ 2026-08-05 9:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: anjo, qemu-arm, git, maobibo, lixianglai, philmd
在 2026/7/31 上午8:04, Richard Henderson 写道:
> The bitrev_[48]b instructions reverse bits within each byte.
> This may be accomplished by reversing bits within the entire
> word followed by reversing the bytes with the entire word.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/loongarch/tcg/helper.h | 2 --
> target/loongarch/tcg/op_helper.c | 11 ----------
> .../loongarch/tcg/insn_trans/trans_bit.c.inc | 20 +++++++++++++++++--
> 3 files changed, 18 insertions(+), 15 deletions(-)
Reviewed-by: Song Gao <17746591750@163.com>
Thanks.
Song Gao
> diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h
> index 4b0fc81db6..e76c73c775 100644
> --- a/target/loongarch/tcg/helper.h
> +++ b/target/loongarch/tcg/helper.h
> @@ -5,8 +5,6 @@
>
> DEF_HELPER_2(raise_exception, noreturn, env, i32)
>
> -DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
> -
> DEF_HELPER_FLAGS_3(asrtle_d, TCG_CALL_NO_WG, void, env, tl, tl)
> DEF_HELPER_FLAGS_3(asrtgt_d, TCG_CALL_NO_WG, void, env, tl, tl)
>
> diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c
> index 37afa8e92d..f41f0cb1e6 100644
> --- a/target/loongarch/tcg/op_helper.c
> +++ b/target/loongarch/tcg/op_helper.c
> @@ -22,17 +22,6 @@ void helper_raise_exception(CPULoongArchState *env, uint32_t exception)
> do_raise_exception(env, exception, GETPC());
> }
>
> -target_ulong helper_bitswap(target_ulong v)
> -{
> - v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
> - ((v & (target_ulong)0x5555555555555555ULL) << 1);
> - v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
> - ((v & (target_ulong)0x3333333333333333ULL) << 2);
> - v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
> - ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
> - return v;
> -}
> -
> /* loongarch assert op */
> void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
> {
> diff --git a/target/loongarch/tcg/insn_trans/trans_bit.c.inc b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
> index 3d24e320ce..1200f931fa 100644
> --- a/target/loongarch/tcg/insn_trans/trans_bit.c.inc
> +++ b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
> @@ -178,6 +178,22 @@ static void gen_masknez(TCGv dest, TCGv src1, TCGv src2)
> tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, zero, zero, src1);
> }
>
> +static void gen_bitrev_4b(TCGv dest, TCGv src)
> +{
> + TCGv_i32 t = tcg_temp_new_i32();
> +
> + tcg_gen_trunc_tl_i32(t, src);
> + tcg_gen_revbit32_i32(t, t);
> + tcg_gen_bswap32_i32(t, t);
> + tcg_gen_ext_i32_tl(dest, t);
> +}
> +
> +static void gen_bitrev_8b(TCGv dest, TCGv src)
> +{
> + tcg_gen_revbit_tl(dest, src);
> + tcg_gen_bswap_tl(dest, dest);
> +}
> +
> static void gen_bitrev_w(TCGv dest, TCGv src)
> {
> tcg_gen_revbit32_tl(dest, src, TCG_BSWAP_OS);
> @@ -199,8 +215,8 @@ TRANS(revb_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)
> TRANS(revb_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)
> TRANS(revh_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
> TRANS(revh_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
> -TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)
> -TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)
> +TRANS(bitrev_4b, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_bitrev_4b)
> +TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, gen_bitrev_8b)
> TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_bitrev_w)
> TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_revbit64_i64)
> TRANS(maskeqz, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 08/11] tcg/optimize: Handle revbit{32,64}
2026-07-31 0:05 ` [PATCH 08/11] tcg/optimize: Handle revbit{32,64} Richard Henderson
@ 2026-08-10 10:44 ` Anton Johansson via qemu development
2026-08-10 10:44 ` Anton Johansson via qemu development
1 sibling, 0 replies; 41+ messages in thread
From: Anton Johansson via @ 2026-08-10 10:44 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> These are nearly identical to bswap, so reuse fold_bswap.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 48 +++++++++++++++++++++++++-----------------------
> 1 file changed, 25 insertions(+), 23 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 08/11] tcg/optimize: Handle revbit{32,64}
@ 2026-08-10 10:44 ` Anton Johansson via qemu development
0 siblings, 0 replies; 41+ messages in thread
From: Anton Johansson via qemu development @ 2026-08-10 10:44 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> These are nearly identical to bswap, so reuse fold_bswap.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/optimize.c | 48 +++++++++++++++++++++++++-----------------------
> 1 file changed, 25 insertions(+), 23 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/11] tcg: Add revbit opcodes
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
@ 2026-08-10 10:46 ` Anton Johansson via
2026-07-31 0:04 ` [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64} Richard Henderson
` (10 subsequent siblings)
11 siblings, 0 replies; 41+ messages in thread
From: Anton Johansson via qemu development @ 2026-08-10 10:46 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> Adding these have been at the back of my mind for a while. Most recently
> tickled by the Octeon additions, and Anton's helper-to-tcg work.
>
> I didn't add a 16-bit function or opcode because no host implements it.
> The 16-bit reverse that the hexagon target does can be implemented with
> a 32-bit reverse plus a shift.
>
>
> r~
Thanks for adding these!:) I just came back from some time off, will take
a look now.
// Anton
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/11] tcg: Add revbit opcodes
@ 2026-08-10 10:46 ` Anton Johansson via
0 siblings, 0 replies; 41+ messages in thread
From: Anton Johansson via @ 2026-08-10 10:46 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> Adding these have been at the back of my mind for a while. Most recently
> tickled by the Octeon additions, and Anton's helper-to-tcg work.
>
> I didn't add a 16-bit function or opcode because no host implements it.
> The 16-bit reverse that the hexagon target does can be implemented with
> a 32-bit reverse plus a shift.
>
>
> r~
Thanks for adding these!:) I just came back from some time off, will take
a look now.
// Anton
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64}
2026-07-31 0:04 ` [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64} Richard Henderson
@ 2026-08-10 11:15 ` Anton Johansson via qemu development
2026-07-31 6:49 ` Philippe Mathieu-Daudé
2026-08-10 11:15 ` Anton Johansson via qemu development
2 siblings, 0 replies; 41+ messages in thread
From: Anton Johansson via @ 2026-08-10 11:15 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> Add generic expanders for reversing bits within a word.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-op-common.h | 3 ++
> include/tcg/tcg-op.h | 5 ++++
> tcg/tcg-op.c | 59 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 67 insertions(+)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64}
@ 2026-08-10 11:15 ` Anton Johansson via qemu development
0 siblings, 0 replies; 41+ messages in thread
From: Anton Johansson via qemu development @ 2026-08-10 11:15 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> Add generic expanders for reversing bits within a word.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-op-common.h | 3 ++
> include/tcg/tcg-op.h | 5 ++++
> tcg/tcg-op.c | 59 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 67 insertions(+)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 06/11] target/mips: Expand octeon reflections inline
2026-07-31 0:04 ` [PATCH 06/11] target/mips: Expand octeon reflections inline Richard Henderson
@ 2026-08-10 11:29 ` Anton Johansson via qemu development
0 siblings, 0 replies; 41+ messages in thread
From: Anton Johansson via @ 2026-08-10 11:29 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> Use tcg_gen_revbit64_i64 instead of out-of-line helpers.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/mips/helper.h | 7 -----
> target/mips/tcg/octeon_crypto.c | 35 ---------------------
> target/mips/tcg/octeon_translate.c | 49 ++++++++++++++++++++++++++----
> 3 files changed, 43 insertions(+), 48 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 06/11] target/mips: Expand octeon reflections inline
@ 2026-08-10 11:29 ` Anton Johansson via qemu development
0 siblings, 0 replies; 41+ messages in thread
From: Anton Johansson via qemu development @ 2026-08-10 11:29 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> Use tcg_gen_revbit64_i64 instead of out-of-line helpers.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/mips/helper.h | 7 -----
> target/mips/tcg/octeon_crypto.c | 35 ---------------------
> target/mips/tcg/octeon_translate.c | 49 ++++++++++++++++++++++++++----
> 3 files changed, 43 insertions(+), 48 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 11/11] tcg/loongarch64: Implement revbit{32,64}
2026-07-31 0:05 ` [PATCH 11/11] tcg/loongarch64: Implement revbit{32,64} Richard Henderson
@ 2026-08-10 12:15 ` Anton Johansson via qemu development
2026-08-10 12:15 ` Anton Johansson via qemu development
1 sibling, 0 replies; 41+ messages in thread
From: Anton Johansson via @ 2026-08-10 12:15 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/loongarch64/tcg-target.c.inc | 22 ++++++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 11/11] tcg/loongarch64: Implement revbit{32,64}
@ 2026-08-10 12:15 ` Anton Johansson via qemu development
0 siblings, 0 replies; 41+ messages in thread
From: Anton Johansson via qemu development @ 2026-08-10 12:15 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/loongarch64/tcg-target.c.inc | 22 ++++++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 07/11] tcg: Add revbit{32,64} opcodes
2026-07-31 0:04 ` [PATCH 07/11] tcg: Add revbit{32,64} opcodes Richard Henderson
@ 2026-08-10 12:15 ` Anton Johansson via
2026-08-10 12:15 ` Anton Johansson via
1 sibling, 0 replies; 41+ messages in thread
From: Anton Johansson via qemu development @ 2026-08-10 12:15 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> Add the plumbing, but not yet implemented for any host.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-opc.h | 2 ++
> tcg/tcg-op.c | 43 +++++++++++++++++++++++---------
> tcg/tcg.c | 6 +++++
> docs/devel/tcg-ops.rst | 11 ++++++++
> tcg/aarch64/tcg-target.c.inc | 8 ++++++
> tcg/loongarch64/tcg-target.c.inc | 8 ++++++
> tcg/ppc64/tcg-target.c.inc | 8 ++++++
> tcg/riscv64/tcg-target.c.inc | 8 ++++++
> tcg/s390x/tcg-target.c.inc | 8 ++++++
> tcg/sparc64/tcg-target.c.inc | 8 ++++++
> tcg/tci/tcg-target.c.inc | 8 ++++++
> tcg/x86_64/tcg-target.c.inc | 8 ++++++
> 12 files changed, 114 insertions(+), 12 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 07/11] tcg: Add revbit{32,64} opcodes
@ 2026-08-10 12:15 ` Anton Johansson via
0 siblings, 0 replies; 41+ messages in thread
From: Anton Johansson via @ 2026-08-10 12:15 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, qemu-arm, git, 17746591750, maobibo, lixianglai,
philmd
On 31/07/26, Richard Henderson wrote:
> Add the plumbing, but not yet implemented for any host.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-opc.h | 2 ++
> tcg/tcg-op.c | 43 +++++++++++++++++++++++---------
> tcg/tcg.c | 6 +++++
> docs/devel/tcg-ops.rst | 11 ++++++++
> tcg/aarch64/tcg-target.c.inc | 8 ++++++
> tcg/loongarch64/tcg-target.c.inc | 8 ++++++
> tcg/ppc64/tcg-target.c.inc | 8 ++++++
> tcg/riscv64/tcg-target.c.inc | 8 ++++++
> tcg/s390x/tcg-target.c.inc | 8 ++++++
> tcg/sparc64/tcg-target.c.inc | 8 ++++++
> tcg/tci/tcg-target.c.inc | 8 ++++++
> tcg/x86_64/tcg-target.c.inc | 8 ++++++
> 12 files changed, 114 insertions(+), 12 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2026-08-10 12:11 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-07-31 0:04 [PATCH 00/11] tcg: Add revbit opcodes Richard Henderson
2026-07-31 0:04 ` [PATCH 01/11] tcg: Fix opcode dump for bswap Richard Henderson
2026-08-03 15:08 ` Philippe Mathieu-Daudé
2026-07-31 0:04 ` [PATCH 02/11] tcg: Add tcg_gen_revbit{32,64} Richard Henderson
2026-07-31 6:08 ` Philippe Mathieu-Daudé
2026-07-31 6:41 ` Philippe Mathieu-Daudé
2026-07-31 8:55 ` Philippe Mathieu-Daudé
2026-07-31 6:49 ` Philippe Mathieu-Daudé
2026-07-31 14:29 ` Richard Henderson
2026-08-10 11:15 ` Anton Johansson via
2026-08-10 11:15 ` Anton Johansson via qemu development
2026-07-31 0:04 ` [PATCH 03/11] target/arm: Use generic tcg_gen_revbit* Richard Henderson
2026-07-31 6:08 ` Philippe Mathieu-Daudé
2026-07-31 0:04 ` [PATCH 04/11] target/loongarch: " Richard Henderson
2026-07-31 6:10 ` Philippe Mathieu-Daudé
2026-08-05 9:16 ` Song Gao
2026-07-31 0:04 ` [PATCH 05/11] target/loongarch: Expand bitswap inline Richard Henderson
2026-08-05 9:17 ` Song Gao
2026-07-31 0:04 ` [PATCH 06/11] target/mips: Expand octeon reflections inline Richard Henderson
2026-08-10 11:29 ` Anton Johansson via
2026-08-10 11:29 ` Anton Johansson via qemu development
2026-07-31 0:04 ` [PATCH 07/11] tcg: Add revbit{32,64} opcodes Richard Henderson
2026-07-31 7:02 ` Philippe Mathieu-Daudé
2026-08-10 12:15 ` Anton Johansson via qemu development
2026-08-10 12:15 ` Anton Johansson via
2026-07-31 0:05 ` [PATCH 08/11] tcg/optimize: Handle revbit{32,64} Richard Henderson
2026-08-03 14:58 ` Philippe Mathieu-Daudé
2026-08-10 10:44 ` Anton Johansson via
2026-08-10 10:44 ` Anton Johansson via qemu development
2026-07-31 0:05 ` [PATCH 09/11] tcg/aarch64: Implement revbit{32,64} Richard Henderson
2026-07-31 7:12 ` Philippe Mathieu-Daudé
2026-07-31 0:05 ` [PATCH 10/11] tcg/loongarch64: Import REVBIT insns Richard Henderson
2026-08-03 15:06 ` Philippe Mathieu-Daudé
2026-08-03 17:26 ` Richard Henderson
2026-08-04 2:51 ` Philippe Mathieu-Daudé
2026-07-31 0:05 ` [PATCH 11/11] tcg/loongarch64: Implement revbit{32,64} Richard Henderson
2026-08-03 14:59 ` Philippe Mathieu-Daudé
2026-08-10 12:15 ` Anton Johansson via
2026-08-10 12:15 ` Anton Johansson via qemu development
2026-08-10 10:46 ` [PATCH 00/11] tcg: Add revbit opcodes Anton Johansson via qemu development
2026-08-10 10:46 ` Anton Johansson via
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