From: Zhao Liu <zhao1.liu@intel.com>
To: Tina Zhang <zhang_wei@open-hieco.net>
Cc: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
kvm@vger.kernel.org, "Michael S . Tsirkin" <mst@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>,
Yanjing Zhou <zhouyanjing@hygon.cn>
Subject: Re: [PATCH v3 05/10] target/i386/kvm: Classify PMU vendor families
Date: Mon, 24 Aug 2026 13:38:59 +0800 [thread overview]
Message-ID: <aovY88W/XD0fQeTH@intel.com> (raw)
In-Reply-To: <20260824045314.162941-6-zhang_wei@open-hieco.net>
On Mon, Aug 24, 2026 at 12:53:09PM +0800, Tina Zhang wrote:
> Date: Mon, 24 Aug 2026 12:53:09 +0800
> From: Tina Zhang <zhang_wei@open-hieco.net>
> Subject: [PATCH v3 05/10] target/i386/kvm: Classify PMU vendor families
> X-Mailer: git-send-email 2.43.7
>
> The Intel and Zhaoxin PMU architectures are compatible, while AMD uses
> a separate PMU CPUID/MSR layout. KVM's PMU initialization, host/guest
> compatibility, and MSR save/restore paths open-code these vendor checks
> in several places.
>
> Introduce X86PMUVendor and helpers that classify the existing CPU and
> host vendors by PMU architecture. Use the classification consistently
> for the compatibility check, PMU initialization, and PMU MSR paths.
>
> This is a refactoring with no functional change.
>
> Signed-off-by: Tina Zhang <zhang_wei@open-hieco.net>
> ---
> target/i386/kvm/kvm.c | 72 +++++++++++++++++++++++++++++++++----------
> 1 file changed, 55 insertions(+), 17 deletions(-)
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
next prev parent reply other threads:[~2026-08-24 5:39 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-24 4:53 [PATCH v3 00/10] target/i386: Fix Hygon vendor-specific CPU behavior Tina Zhang
2026-08-24 4:53 ` [PATCH v3 01/10] target/i386: Sync AMD CPUID aliases for Hygon Tina Zhang
2026-08-24 5:36 ` Zhao Liu
2026-08-24 4:53 ` [PATCH v3 02/10] target/i386: Hide Intel cache CPUID leaves " Tina Zhang
2026-08-24 4:53 ` [PATCH v3 03/10] target/i386: Hide ARCH_CAPABILITIES " Tina Zhang
2026-08-24 4:53 ` [PATCH v3 04/10] target/i386/kvm: Use AMD MCE status encoding " Tina Zhang
2026-08-24 4:53 ` [PATCH v3 05/10] target/i386/kvm: Classify PMU vendor families Tina Zhang
2026-08-24 5:38 ` Zhao Liu [this message]
2026-08-24 4:53 ` [PATCH v3 06/10] target/i386/kvm: Use AMD PMU MSR paths for Hygon Tina Zhang
2026-08-24 5:39 ` Zhao Liu
2026-08-24 4:53 ` [PATCH v3 07/10] target/i386: Do not broadcast injected MCEs " Tina Zhang
2026-08-24 4:53 ` [PATCH v3 08/10] hw/i386: Reserve AMD IOMMU HT GPA range " Tina Zhang
2026-08-24 5:40 ` Zhao Liu
2026-08-24 4:53 ` [PATCH v3 09/10] target/i386: Use AMD legacy cache fallback " Tina Zhang
2026-08-24 4:53 ` [PATCH v3 10/10] target/i386: Use AMD ucode-rev default " Tina Zhang
2026-09-01 3:41 ` [PATCH v3 00/10] target/i386: Fix Hygon vendor-specific CPU behavior Tina Zhang
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