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From: Zhao Liu <zhao1.liu@intel.com>
To: Tina Zhang <zhang_wei@open-hieco.net>
Cc: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
	kvm@vger.kernel.org, "Michael S . Tsirkin" <mst@redhat.com>,
	Marcelo Tosatti <mtosatti@redhat.com>,
	Yanjing Zhou <zhouyanjing@hygon.cn>
Subject: Re: [PATCH v3 08/10] hw/i386: Reserve AMD IOMMU HT GPA range for Hygon
Date: Mon, 24 Aug 2026 13:40:46 +0800	[thread overview]
Message-ID: <aovZXpnT+Qc2MFtn@intel.com> (raw)
In-Reply-To: <20260824045314.162941-9-zhang_wei@open-hieco.net>

On Mon, Aug 24, 2026 at 12:53:12PM +0800, Tina Zhang wrote:
> Date: Mon, 24 Aug 2026 12:53:12 +0800
> From: Tina Zhang <zhang_wei@open-hieco.net>
> Subject: [PATCH v3 08/10] hw/i386: Reserve AMD IOMMU HT GPA range for Hygon
> X-Mailer: git-send-email 2.43.7
> 
> pc_memory_init() avoids the AMD IOMMU HyperTransport range below 1 TiB
> only for AMD vCPUs.  Dhyana therefore allows RAM, hotplug address space,
> or 64-bit PCI MMIO to overlap 0xfd00000000-0xffffffffff.
> 
> Linux supports Dhyana platforms in the AMD IOMMU driver.  The driver
> reports this range as reserved unless the IOMMU advertises
> FEATURE_HT_RANGE_IGNORE.  A VFIO device cannot DMA to guest addresses
> that QEMU places in the reserved range: VFIO_DMA_MAP may fail with
> -EINVAL, or the IOMMU may report an INVALID_DEVICE_REQUEST fault.
> 
> Apply the AMD IOMMU HT GPA layout to Hygon vCPUs.  When the possible
> address space reaches the reserved range, move RAM above 4 GiB to 1 TiB;
> also expose the range as reserved in E820 when the vCPU can address it.
> 
> Changing the GPA layout affects migration, so enable the Hygon behavior
> through x-hygon-vendor-abi-fixes.  pc-11.1 and older machine types retain
> their previous Hygon layout.  The existing enforce_amd_1tb_hole setting
> continues to preserve the AMD layout of pc/q35 machine types through 7.0.
> 
> Add functional tests for Dhyana with pc-q35-11.2 and with pc-q35-11.1
> compatibility.
> 
> Signed-off-by: Yanjing Zhou <zhouyanjing@hygon.cn>
> Signed-off-by: Tina Zhang <zhang_wei@open-hieco.net>
> ---
>  hw/i386/pc.c                                  | 26 ++++++++++----
>  .../functional/x86_64/test_mem_addr_space.py  | 36 +++++++++++++++++++
>  2 files changed, 55 insertions(+), 7 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>



  reply	other threads:[~2026-08-24  5:41 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-24  4:53 [PATCH v3 00/10] target/i386: Fix Hygon vendor-specific CPU behavior Tina Zhang
2026-08-24  4:53 ` [PATCH v3 01/10] target/i386: Sync AMD CPUID aliases for Hygon Tina Zhang
2026-08-24  5:36   ` Zhao Liu
2026-08-24  4:53 ` [PATCH v3 02/10] target/i386: Hide Intel cache CPUID leaves " Tina Zhang
2026-08-24  4:53 ` [PATCH v3 03/10] target/i386: Hide ARCH_CAPABILITIES " Tina Zhang
2026-08-24  4:53 ` [PATCH v3 04/10] target/i386/kvm: Use AMD MCE status encoding " Tina Zhang
2026-08-24  4:53 ` [PATCH v3 05/10] target/i386/kvm: Classify PMU vendor families Tina Zhang
2026-08-24  5:38   ` Zhao Liu
2026-08-24  4:53 ` [PATCH v3 06/10] target/i386/kvm: Use AMD PMU MSR paths for Hygon Tina Zhang
2026-08-24  5:39   ` Zhao Liu
2026-08-24  4:53 ` [PATCH v3 07/10] target/i386: Do not broadcast injected MCEs " Tina Zhang
2026-08-24  4:53 ` [PATCH v3 08/10] hw/i386: Reserve AMD IOMMU HT GPA range " Tina Zhang
2026-08-24  5:40   ` Zhao Liu [this message]
2026-08-24  4:53 ` [PATCH v3 09/10] target/i386: Use AMD legacy cache fallback " Tina Zhang
2026-08-24  4:53 ` [PATCH v3 10/10] target/i386: Use AMD ucode-rev default " Tina Zhang
2026-09-01  3:41 ` [PATCH v3 00/10] target/i386: Fix Hygon vendor-specific CPU behavior Tina Zhang

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