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From: Zhao Liu <zhao1.liu@intel.com>
To: Tina Zhang <zhang_wei@open-hieco.net>
Cc: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
	kvm@vger.kernel.org, "Michael S . Tsirkin" <mst@redhat.com>,
	Marcelo Tosatti <mtosatti@redhat.com>,
	Yanjing Zhou <zhouyanjing@hygon.cn>,
	Yongwei Xu <xuyongwei@open-hieco.net>
Subject: Re: [PATCH v3 01/10] target/i386: Sync AMD CPUID aliases for Hygon
Date: Mon, 24 Aug 2026 13:36:43 +0800	[thread overview]
Message-ID: <aovYayjaps1GBb7H@intel.com> (raw)
In-Reply-To: <20260824045314.162941-2-zhang_wei@open-hieco.net>

On Mon, Aug 24, 2026 at 12:53:05PM +0800, Tina Zhang wrote:
> Date: Mon, 24 Aug 2026 12:53:05 +0800
> From: Tina Zhang <zhang_wei@open-hieco.net>
> Subject: [PATCH v3 01/10] target/i386: Sync AMD CPUID aliases for Hygon
> X-Mailer: git-send-email 2.43.7
> 
> AMD defines CPUID[0x80000001].EDX bits as aliases for a subset of
> CPUID[1].EDX.  QEMU currently synchronizes those aliases only when the
> guest CPU vendor is AuthenticAMD.
> 
> Hygon Dhyana uses the HygonGenuine vendor string, but implements the
> same AMD-compatible extended CPUID feature aliases.  This can leave QEMU
> advertising a feature in CPUID[1].EDX while the matching extended alias
> in CPUID[0x80000001].EDX stays clear.  This inconsistent CPUID state can
> confuse guest OS feature detection.
> 
> Apply the alias synchronization to Hygon CPUs as well.  Gate the new
> behavior with x-hygon-vendor-abi-fixes and disable it for pc-11.1 and
> older machine types, because the CPUID result is guest-visible ABI and
> must remain migration-compatible.
> 
> Add qtest coverage for the Dhyana model, including the compat property.
> 
> Signed-off-by: Tina Zhang <zhang_wei@open-hieco.net>
> Tested-by: Yongwei Xu <xuyongwei@open-hieco.net>
> ---
>  hw/i386/pc.c                        |  4 +-
>  target/i386/cpu.c                   | 10 ++--
>  target/i386/cpu.h                   | 12 +++++
>  tests/qtest/test-x86-cpuid-compat.c | 76 +++++++++++++++++++++++++++++
>  4 files changed, 98 insertions(+), 4 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>



  reply	other threads:[~2026-08-24  5:37 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-24  4:53 [PATCH v3 00/10] target/i386: Fix Hygon vendor-specific CPU behavior Tina Zhang
2026-08-24  4:53 ` [PATCH v3 01/10] target/i386: Sync AMD CPUID aliases for Hygon Tina Zhang
2026-08-24  5:36   ` Zhao Liu [this message]
2026-08-24  4:53 ` [PATCH v3 02/10] target/i386: Hide Intel cache CPUID leaves " Tina Zhang
2026-08-24  4:53 ` [PATCH v3 03/10] target/i386: Hide ARCH_CAPABILITIES " Tina Zhang
2026-08-24  4:53 ` [PATCH v3 04/10] target/i386/kvm: Use AMD MCE status encoding " Tina Zhang
2026-08-24  4:53 ` [PATCH v3 05/10] target/i386/kvm: Classify PMU vendor families Tina Zhang
2026-08-24  5:38   ` Zhao Liu
2026-08-24  4:53 ` [PATCH v3 06/10] target/i386/kvm: Use AMD PMU MSR paths for Hygon Tina Zhang
2026-08-24  5:39   ` Zhao Liu
2026-08-24  4:53 ` [PATCH v3 07/10] target/i386: Do not broadcast injected MCEs " Tina Zhang
2026-08-24  4:53 ` [PATCH v3 08/10] hw/i386: Reserve AMD IOMMU HT GPA range " Tina Zhang
2026-08-24  5:40   ` Zhao Liu
2026-08-24  4:53 ` [PATCH v3 09/10] target/i386: Use AMD legacy cache fallback " Tina Zhang
2026-08-24  4:53 ` [PATCH v3 10/10] target/i386: Use AMD ucode-rev default " Tina Zhang
2026-09-01  3:41 ` [PATCH v3 00/10] target/i386: Fix Hygon vendor-specific CPU behavior Tina Zhang

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