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From: Gerd Hoffmann <kraxel@redhat.com>
To: David Vrabel <david.vrabel@nutanix.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	 Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	 Zhao Liu <zhao1.liu@intel.com>,
	Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [PATCH v2 1/4] hw/pci-bridge: Add generic PCIe switch upstream and downstream ports
Date: Wed, 9 Sep 2026 17:14:07 +0200	[thread overview]
Message-ID: <aqF26NFTUtPDaLA9@sirius.home.kraxel.org> (raw)
In-Reply-To: <20260908155223.164787-2-david.vrabel@nutanix.com>

  Hi,

> +#define GEN_PCIE_DOWNSTREAM_PORT_VENDOR_ID       0x1b36
> +#define GEN_PCIE_DOWNSTREAM_PORT_DEVICE_ID       0x0016

These #defines are maintained in include/hw/pci/pci.h,
please add them there next to the existing ones.

Also make sure to update docs/specs/pci-ids.rst
when allocating a new ID from the range for qemu.

take care,
  Gerd



  parent reply	other threads:[~2026-09-09 15:14 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-08 15:52 [PATCH v2 0/4] hw/pci-bridge: Configurable apparent bandwidth for the PCIe topology David Vrabel
2026-09-08 15:52 ` [PATCH v2 2/4] hw/pci-bridge: Make speed and width for PCIe ports non-experimental David Vrabel
2026-09-08 15:52 ` [PATCH v2 1/4] hw/pci-bridge: Add generic PCIe switch upstream and downstream ports David Vrabel
2026-09-08 16:05   ` David Vrabel
2026-09-09 15:14   ` Gerd Hoffmann [this message]
2026-09-08 15:52 ` [PATCH v2 3/4] hw/pci-bridge: Default the generic PCIe root port as Gen6 capable David Vrabel
2026-09-08 15:52 ` [PATCH v2 4/4] hw/pci: Ensure PCIe link speed/width is consistent between both ends David Vrabel

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